1/** @file 2 Thunderbolt ACPI methods 3 4Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR> 5SPDX-License-Identifier: BSD-2-Clause-Patent 6 7**/ 8 9#define DTBT_CONTROLLER 0x00 10#define DTBT_TYPE_PCH 0x01 11#define DTBT_TYPE_PEG 0x02 12#define DTBT_SMI_HANDLER_NUMBER 0xF7 13#define TBT_SMI_ENUMERATION_FUNCTION 21 14#define TBT_SMI_RESET_SWITCH_FUNCTION 22 15#define TBT_SMI_DISABLE_MSI_FUNCTION 23 16#ifndef BIT29 17#define BIT29 0x20000000 18#endif 19 20Name(LDLY, 300) //300 ms 21Name (TNVB, 0xFFFF0000) // TBT NVS Base address 22Name (TNVL, 0xAA55) // TBT NVS Length 23Include ("Acpi/TbtNvs.asl") 24 25External(\_SB.PCI0.RP02.L23D, MethodObj) 26External(\_SB.PCI0.RP03.L23D, MethodObj) 27External(\_SB.PCI0.RP04.L23D, MethodObj) 28External(\_SB.PCI0.RP05.L23D, MethodObj) 29External(\_SB.PCI0.RP06.L23D, MethodObj) 30External(\_SB.PCI0.RP07.L23D, MethodObj) 31External(\_SB.PCI0.RP08.L23D, MethodObj) 32External(\_SB.PCI0.RP09.L23D, MethodObj) 33External(\_SB.PCI0.RP10.L23D, MethodObj) 34External(\_SB.PCI0.RP11.L23D, MethodObj) 35External(\_SB.PCI0.RP12.L23D, MethodObj) 36External(\_SB.PCI0.RP13.L23D, MethodObj) 37External(\_SB.PCI0.RP14.L23D, MethodObj) 38External(\_SB.PCI0.RP15.L23D, MethodObj) 39External(\_SB.PCI0.RP16.L23D, MethodObj) 40External(\_SB.PCI0.RP17.L23D, MethodObj) 41External(\_SB.PCI0.RP18.L23D, MethodObj) 42External(\_SB.PCI0.RP19.L23D, MethodObj) 43External(\_SB.PCI0.RP20.L23D, MethodObj) 44External(\_SB.PCI0.RP21.L23D, MethodObj) 45External(\_SB.PCI0.RP22.L23D, MethodObj) 46External(\_SB.PCI0.RP23.L23D, MethodObj) 47External(\_SB.PCI0.RP24.L23D, MethodObj) 48 49External(\_SB.PCI0.RP01.DL23, MethodObj) 50External(\_SB.PCI0.RP02.DL23, MethodObj) 51External(\_SB.PCI0.RP03.DL23, MethodObj) 52External(\_SB.PCI0.RP04.DL23, MethodObj) 53External(\_SB.PCI0.RP05.DL23, MethodObj) 54External(\_SB.PCI0.RP06.DL23, MethodObj) 55External(\_SB.PCI0.RP07.DL23, MethodObj) 56External(\_SB.PCI0.RP08.DL23, MethodObj) 57External(\_SB.PCI0.RP09.DL23, MethodObj) 58External(\_SB.PCI0.RP10.DL23, MethodObj) 59External(\_SB.PCI0.RP11.DL23, MethodObj) 60External(\_SB.PCI0.RP12.DL23, MethodObj) 61External(\_SB.PCI0.RP13.DL23, MethodObj) 62External(\_SB.PCI0.RP14.DL23, MethodObj) 63External(\_SB.PCI0.RP15.DL23, MethodObj) 64External(\_SB.PCI0.RP16.DL23, MethodObj) 65External(\_SB.PCI0.RP17.DL23, MethodObj) 66External(\_SB.PCI0.RP18.DL23, MethodObj) 67External(\_SB.PCI0.RP19.DL23, MethodObj) 68External(\_SB.PCI0.RP20.DL23, MethodObj) 69External(\_SB.PCI0.RP21.DL23, MethodObj) 70External(\_SB.PCI0.RP22.DL23, MethodObj) 71External(\_SB.PCI0.RP23.DL23, MethodObj) 72External(\_SB.PCI0.RP24.DL23, MethodObj) 73 74External(\_SB.PCI0.RTEN, MethodObj) 75External(\_SB.PCI0.RTDS, MethodObj) 76External(\_SB.PCI0.RP01.PON, MethodObj) 77External(\_SB.PCI0.RP02.PON, MethodObj) 78External(\_SB.PCI0.RP03.PON, MethodObj) 79External(\_SB.PCI0.RP04.PON, MethodObj) 80External(\_SB.PCI0.RP05.PON, MethodObj) 81External(\_SB.PCI0.RP06.PON, MethodObj) 82External(\_SB.PCI0.RP07.PON, MethodObj) 83External(\_SB.PCI0.RP08.PON, MethodObj) 84External(\_SB.PCI0.RP09.PON, MethodObj) 85External(\_SB.PCI0.RP10.PON, MethodObj) 86External(\_SB.PCI0.RP11.PON, MethodObj) 87External(\_SB.PCI0.RP12.PON, MethodObj) 88External(\_SB.PCI0.RP13.PON, MethodObj) 89External(\_SB.PCI0.RP14.PON, MethodObj) 90External(\_SB.PCI0.RP15.PON, MethodObj) 91External(\_SB.PCI0.RP16.PON, MethodObj) 92External(\_SB.PCI0.RP17.PON, MethodObj) 93External(\_SB.PCI0.RP18.PON, MethodObj) 94External(\_SB.PCI0.RP19.PON, MethodObj) 95External(\_SB.PCI0.RP20.PON, MethodObj) 96External(\_SB.PCI0.RP21.PON, MethodObj) 97External(\_SB.PCI0.RP22.PON, MethodObj) 98External(\_SB.PCI0.RP23.PON, MethodObj) 99External(\_SB.PCI0.RP24.PON, MethodObj) 100External(\_SB.PCI0.PEG0.PG00._ON, MethodObj) 101External(\_SB.PCI0.PEG1.PG01._ON, MethodObj) 102External(\_SB.PCI0.PEG2.PG02._ON, MethodObj) 103 104Name(TRDO, 0) // 1 during TBT RTD3 _ON 105Name(TRD3, 0) // 1 during TBT RTD3 _OFF 106Name(TBPE, 0) // Reflects RTD3_PWR_EN value 107Name(TOFF, 0) // param to TBT _OFF method 108 109 Method (TBON, 0, Serialized) { 110 // TBT On process before entering Sx state. 111 Store(1, TRDO) 112 Switch (ToInteger(\RPS0)) { // TBT Root port Selector 113 Case (1) { 114 If (CondRefOf(\_SB.PCI0.RP01.PON)) { 115 \_SB.PCI0.RP01.PON() 116 } 117 } 118 Case (2) { 119 If (CondRefOf(\_SB.PCI0.RP02.PON)) { 120 \_SB.PCI0.RP02.PON() 121 } 122 } 123 Case (3) { 124 If (CondRefOf(\_SB.PCI0.RP03.PON)) { 125 \_SB.PCI0.RP03.PON() 126 } 127 } 128 Case (4) { 129 If (CondRefOf(\_SB.PCI0.RP04.PON)) { 130 \_SB.PCI0.RP04.PON() 131 } 132 } 133 Case (5) { 134 If (CondRefOf(\_SB.PCI0.RP05.PON)) { 135 \_SB.PCI0.RP05.PON() 136 } 137 } 138 Case (6) { 139 If (CondRefOf(\_SB.PCI0.RP06.PON)) { 140 \_SB.PCI0.RP06.PON() 141 } 142 } 143 Case (7) { 144 If (CondRefOf(\_SB.PCI0.RP07.PON)) { 145 \_SB.PCI0.RP07.PON() 146 } 147 } 148 Case (8) { 149 If (CondRefOf(\_SB.PCI0.RP08.PON)) { 150 \_SB.PCI0.RP08.PON() 151 } 152 } 153 Case (9) { 154 If (CondRefOf(\_SB.PCI0.RP09.PON)) { 155 \_SB.PCI0.RP09.PON() 156 } 157 } 158 Case (10) { 159 If (CondRefOf(\_SB.PCI0.RP10.PON)) { 160 \_SB.PCI0.RP10.PON() 161 } 162 } 163 Case (11) { 164 If (CondRefOf(\_SB.PCI0.RP11.PON)) { 165 \_SB.PCI0.RP11.PON() 166 } 167 } 168 Case (12) { 169 If (CondRefOf(\_SB.PCI0.RP12.PON)) { 170 \_SB.PCI0.RP12.PON() 171 } 172 } 173 Case (13) { 174 If (CondRefOf(\_SB.PCI0.RP13.PON)) { 175 \_SB.PCI0.RP13.PON() 176 } 177 } 178 Case (14) { 179 If (CondRefOf(\_SB.PCI0.RP14.PON)) { 180 \_SB.PCI0.RP14.PON() 181 } 182 } 183 Case (15) { 184 If (CondRefOf(\_SB.PCI0.RP15.PON)) { 185 \_SB.PCI0.RP15.PON() 186 } 187 } 188 Case (16) { 189 If (CondRefOf(\_SB.PCI0.RP16.PON)) { 190 \_SB.PCI0.RP16.PON() 191 } 192 } 193 Case (17) { 194 If (CondRefOf(\_SB.PCI0.RP17.PON)) { 195 \_SB.PCI0.RP17.PON() 196 } 197 } 198 Case (18) { 199 If (CondRefOf(\_SB.PCI0.RP18.PON)) { 200 \_SB.PCI0.RP18.PON() 201 } 202 } 203 Case (19) { 204 If (CondRefOf(\_SB.PCI0.RP19.PON)) { 205 \_SB.PCI0.RP19.PON() 206 } 207 } 208 Case (20) { 209 If (CondRefOf(\_SB.PCI0.RP20.PON)) { 210 \_SB.PCI0.RP20.PON() 211 } 212 } 213 Case (21) { 214 If (CondRefOf(\_SB.PCI0.RP21.PON)) { 215 \_SB.PCI0.RP21.PON() 216 } 217 } 218 Case (22) { 219 If (CondRefOf(\_SB.PCI0.RP22.PON)) { 220 \_SB.PCI0.RP22.PON() 221 } 222 } 223 Case (23) { 224 If (CondRefOf(\_SB.PCI0.RP23.PON)) { 225 \_SB.PCI0.RP23.PON() 226 } 227 } 228 Case (24) { 229 If (CondRefOf(\_SB.PCI0.RP24.PON)) { 230 \_SB.PCI0.RP24.PON() 231 } 232 } 233 }//Switch(ToInteger(RPS0)) // TBT Selector 234 Store(0, TRDO) 235 } // End of TBON 236 // 237 // Name: TBTD 238 // Description: Function to return the TBT RP# device no 239 // Input: Arg0 -> Tbt Root Port value from Tbt NVS 240 // Input: Arg1 -> Tbt port type value from Tbt NVS 241 // Return: TBT RP# device no 242 // 243 Method(TBTD,2) 244 { 245 ADBG("TBTD") 246 If (LEqual(Arg1, DTBT_TYPE_PCH)) { 247 Switch(ToInteger(Arg0)) 248 { 249 Case (Package () {1, 2, 3, 4, 5, 6, 7, 8}) 250 { 251 Store(0x1C, Local0) //Device28-Function0...Function7 = 11100.000...111 252 } 253 Case (Package () {9, 10, 11, 12, 13, 14, 15, 16}) 254 { 255 Store(0x1D, Local0) //Device29-Function0...Function7 = 11101.000...111 256 } 257 Case (Package () {17, 18, 19, 20, 21, 22, 23, 24}) 258 { 259 Store(0x1B, Local0) //Device27-Function0...Function3 = 11011.000...011 260 } 261 } 262 } ElseIf (LEqual(Arg1, DTBT_TYPE_PEG)) { 263 Switch(ToInteger(Arg0)) 264 { 265 Case (Package () {1, 2, 3}) 266 { 267 Store(0x1, Local0) //Device1-Function0...Function2 = 00001.000...010 268 } 269#ifndef CPU_CFL 270 Case (Package () {4}) 271 { 272 Store(0x6, Local0) //Device6-Function0 = 00110.000 273 } 274#endif 275 } 276 } Else { 277 Store(0xFF, Local0) 278 } 279 280 ADBG("Device no") 281 ADBG(Local0) 282 283 Return(Local0) 284 } // End of Method(TBTD,1) 285 286 // 287 // Name: TBTF 288 // Description: Function to return the TBT RP# function no 289 // Input: Arg0 -> Tbt Root Port value from Tbt NVS 290 // Input: Arg1 -> Tbt port type value from Tbt NVS 291 // Return: TBT RP# function no 292 // 293 Method(TBTF,2) 294 { 295 ADBG("TBTF") 296 If (LEqual(Arg1, DTBT_TYPE_PCH)) { 297 Switch(ToInteger(Arg0)) 298 { 299 Case (1) 300 { 301 Store(And(\RPA1,0xF), Local0) //Device28-Function0 = 11100.000 302 } 303 Case (2) 304 { 305 Store(And(\RPA2,0xF), Local0) //Device28-Function1 = 11100.001 306 } 307 Case (3) 308 { 309 Store(And(\RPA3,0xF), Local0) //Device28-Function2 = 11100.010 310 } 311 Case (4) 312 { 313 Store(And(\RPA4,0xF), Local0) //Device28-Function3 = 11100.011 314 } 315 Case (5) 316 { 317 Store(And(\RPA5,0xF), Local0) //Device28-Function4 = 11100.100 318 } 319 Case (6) 320 { 321 Store(And(\RPA6,0xF), Local0) //Device28-Function5 = 11100.101 322 } 323 Case (7) 324 { 325 Store(And(\RPA7,0xF), Local0) //Device28-Function6 = 11100.110 326 } 327 Case (8) 328 { 329 Store(And(\RPA8,0xF), Local0) //Device28-Function7 = 11100.111 330 } 331 Case (9) 332 { 333 Store(And(\RPA9,0xF), Local0) //Device29-Function0 = 11101.000 334 } 335 Case (10) 336 { 337 Store(And(\RPAA,0xF), Local0) //Device29-Function1 = 11101.001 338 } 339 Case (11) 340 { 341 Store(And(\RPAB,0xF), Local0) //Device29-Function2 = 11101.010 342 } 343 Case (12) 344 { 345 Store(And(\RPAC,0xF), Local0) //Device29-Function3 = 11101.011 346 } 347 Case (13) 348 { 349 Store(And(\RPAD,0xF), Local0) //Device29-Function4 = 11101.100 350 } 351 Case (14) 352 { 353 Store(And(\RPAE,0xF), Local0) //Device29-Function5 = 11101.101 354 } 355 Case (15) 356 { 357 Store(And(\RPAF,0xF), Local0) //Device29-Function6 = 11101.110 358 } 359 Case (16) 360 { 361 Store(And(\RPAG,0xF), Local0) //Device29-Function7 = 11101.111 362 } 363 Case (17) 364 { 365 Store(And(\RPAH,0xF), Local0) //Device27-Function0 = 11011.000 366 } 367 Case (18) 368 { 369 Store(And(\RPAI,0xF), Local0) //Device27-Function1 = 11011.001 370 } 371 Case (19) 372 { 373 Store(And(\RPAJ,0xF), Local0) //Device27-Function2 = 11011.010 374 } 375 Case (20) 376 { 377 Store(And(\RPAK,0xF), Local0) //Device27-Function3 = 11011.011 378 } 379 Case (21) 380 { 381 Store(And(\RPAL,0xF), Local0) //Device27-Function4 = 11011.100 382 } 383 Case (22) 384 { 385 Store(And(\RPAM,0xF), Local0) //Device27-Function5 = 11011.101 386 } 387 Case (23) 388 { 389 Store(And(\RPAN,0xF), Local0) //Device27-Function6 = 11011.110 390 } 391 Case (24) 392 { 393 Store(And(\RPAO,0xF), Local0) //Device27-Function7 = 11011.111 394 } 395 } 396 } ElseIf (LEqual(Arg1, DTBT_TYPE_PEG)) { 397 Switch(ToInteger(Arg0)) 398 { 399 Case (1) 400 { 401 Store(0x0, Local0) //Device1-Function0 = 00001.000 402 } 403 Case (2) 404 { 405 Store(0x1, Local0) //Device1-Function1 = 00001.001 406 } 407 Case (3) 408 { 409 Store(0x2, Local0) //Device1-Function2 = 00001.010 410 } 411#ifndef CPU_CFL 412 Case (4) 413 { 414 Store(0x0, Local0) //Device6-Function0 = 00110.000 415 } 416#endif 417 } 418 } Else { 419 Store(0xFF, Local0) 420 } 421 422 ADBG("Function no") 423 ADBG(Local0) 424 425 Return(Local0) 426 } // End of Method(TBTF,1) 427 428 // 429 // Name: MMRP 430 // Description: Function to return the Pci base address of TBT rootport 431 // Input: Arg0 -> Tbt Root Port value from Tbt NVS 432 // Input: Arg1 -> Tbt port type value from Tbt NVS 433 // 434 435 Method(MMRP, 2, Serialized) 436 { 437 Store(\_SB.PCI0.GPCB(), Local0) // MMIO Base address 438 Add(Local0, ShiftLeft(TBTD(Arg0, Arg1), 15), Local0) // Device no 439 Add(Local0, ShiftLeft(TBTF(Arg0, Arg1), 12), Local0) // Function no 440 441 Return(Local0) 442 } // End of Method(MMRP) 443 444 // 445 // Name: MMRP 446 // Description: Function to return the Pci base address of TBT Up stream port 447 // Input: Arg0 -> Tbt Root Port value from Tbt NVS 448 // Input: Arg1 -> Tbt port type value from Tbt NVS 449 // 450 Method(MMTB, 2, Serialized) 451 { 452 ADBG("MMTB") 453 454 Store(\_SB.PCI0.GPCB(), Local0) // MMIO Base address 455 456 Add(Local0, ShiftLeft(TBTD(Arg0, Arg1), 15), Local0) // Device no 457 Add(Local0, ShiftLeft(TBTF(Arg0, Arg1), 12), Local0) // Function no 458 459 OperationRegion (MMMM, SystemMemory, Local0, 0x1A) 460 Field (MMMM, AnyAcc, NoLock, Preserve) 461 { 462 Offset(0x19), 463 SBUS, 8 464 } 465 Store(SBUS, Local2) 466 Store(\_SB.PCI0.GPCB(), Local0) 467 Multiply(Local2, 0x100000, Local2) 468 Add(Local2, Local0, Local0) // TBT HR US port 469 470 ADBG("TBT-US-ADR") 471 ADBG(Local0) 472 473 Return(Local0) 474 } // End of Method(MMTB, 1, Serialized) 475 // 476 // Name: FFTB 477 // Description: Function to Check for FFFF in TBT PCIe 478 // Input: Arg0 -> Tbt Root Port value from Tbt NVS 479 // Input: Arg1 -> Tbt port type value from Tbt NVS 480 // Return: 1 if TBT PCIe space has value FFFF, 0 if not 481 // 482 Method(FFTB, 2, Serialized) 483 { 484 ADBG("FFTB") 485 486 Add(MMTB(Arg0, Arg1), 0x548, Local0) 487 OperationRegion(PXVD,SystemMemory,Local0,0x08) 488 Field(PXVD,DWordAcc, NoLock, Preserve) 489 { 490 TB2P, 32, 491 P2TB, 32 492 } 493 494 Store(TB2P, Local1) 495 496 If(LEqual(Local1, 0xFFFFFFFF)) 497 { 498 ADBG("FFTb 1") 499 Return (1) 500 } 501 Else 502 { 503 ADBG("FFTb 0") 504 Return (0) 505 } 506 } // End of Method(FFTB) 507 508Name(TDMA, 0x80000000) // Address of Thunderbolt(TM) debug memory buffer, fixed up during POST 509 510Scope(\_GPE) 511{ 512 // 513 // 514 //OS up Mail Box command execution to host router upstream port each time 515 //exiting from Sx State .Avoids intermediate 516 //PCIe Scan by OS during resorce allocation 517 // Arg0 : PCIe Base address 518 // Arg1 : Controller Type 0x00 : DTBT 519 //Developer notes: Called twice 520 // 1. During OS INIT (booting to OS from S3-S5/Reboot) 521 // 2. Up on Hot plug 522 // 523 Method(OSUP, 2, Serialized) 524 { 525 ADBG("OSUP") 526 527 Add(Arg0, 0x540, Local0) 528 OperationRegion(PXVD,SystemMemory,Local0,0x10) 529 Field(PXVD,DWordAcc, NoLock, Preserve) 530 { 531 IT2P, 32, 532 IP2T, 32, 533 DT2P, 32, 534 DP2T, 32 535 } 536 537 Store(100, Local1) 538 Store(0x0D, DP2T) // Write OS_Up to PCIe2TBT 539 540 While(LGreater(Local1, 0)) 541 { 542 Store(Subtract(Local1, 1), Local1) 543 Store(DT2P, Local2) 544 545 If(LAnd(LEqual(Local2, 0xFFFFFFFF),LEqual(Arg1, DTBT_CONTROLLER)))// Device gone 546 { 547 ADBG("Dev gone") 548 Return(2) 549 } 550 If(And(Local2, 1)) // Done 551 { 552 ADBG("Cmd acknowledged") 553 break 554 } 555 Sleep(50) 556 } 557 If(LEqual(TRWA,1)) 558 { 559 Store(0xC, DP2T) // Write OSUP to PCIe2TBT 560 } 561 Else 562 { 563 Store(0x0, DP2T) // Write 0 to PCIe2TBT 564 } 565 566 //Store(0x00, P2TB) // Write 0 to PCIe2TBT 567 568 ADBG("End-of-OSUP") 569 570 Return(1) 571 } // End of Method(OSUP, 1, Serialized) 572 573 // 574 // Check for FFFF in TBT 575 // Input: Arg0 -> Tbt Root Port value from Tbt NVS 576 // Input: Arg1 -> Tbt port type value from Tbt NVS 577 // 578 579 Method(TBFF, 2, Serialized) 580 { 581 ADBG("TBFF") 582 583 Store(MMTB(Arg0, Arg1), Local0) 584 OperationRegion (PXVD, SystemMemory, Local0, 0x8) 585 Field (PXVD, DWordAcc, NoLock, Preserve) { 586 VEDI, 32, // Vendor/Device ID 587 CMDR, 32 // CMD register 588 } 589 590 Store(VEDI, Local1) 591 592 If (LEqual(Local1, 0xFFFFFFFF)) { 593 If (LNotEqual(\TWIN, 0)) { // TBT Enumeration is Native mode? 594 If (LEqual(CMDR, 0xFFFFFFFF)) { // Device Gone 595 Return (2)// Notify only 596 } 597 Return (1)// Exit w/o notify 598 } Else { 599 Return (OSUP(Local0, DTBT_CONTROLLER)) 600 } 601 } Else 602 { 603 ADBG("Dev Present") 604 Return (0) 605 } 606 } // End of Method(TBFF, 1, Serialized) 607 608 // 609 // Secondary bus of TBT RP 610 // Input: Arg0 -> Tbt Root Port value from Tbt NVS 611 // Input: Arg1 -> Tbt port type value from Tbt NVS 612 // 613 614 Method(TSUB, 2, Serialized) 615 { 616 ADBG("TSUB") 617 618 Store(\_SB.PCI0.GPCB(), Local0) // MMIO Base address 619 620 Add(Local0, ShiftLeft(TBTD(Arg0, Arg1), 15), Local0) // Device no 621 Add(Local0, ShiftLeft(TBTF(Arg0, Arg1), 12), Local0) // Function no 622 623 ADBG("ADR") 624 ADBG(Local0) 625 626 OperationRegion (MMMM, SystemMemory, Local0, 0x1A) 627 Field (MMMM, AnyAcc, NoLock, Preserve) 628 { 629 Offset(0x19), 630 SBUS, 8 631 } 632 633 ADBG("Sec Bus") 634 ADBG(SBUS) 635 636 Return(SBUS) 637 } // End of Method(TSUB, 0, Serialized) 638 639 // 640 // Pmem of TBT RP 641 // Input: Arg0 -> Tbt Root Port value from Tbt NVS 642 // Input: Arg1 -> Tbt port type value from Tbt NVS 643 // 644 645 Method(TSUP, 2, Serialized) 646 { 647 ADBG("TSUB") 648 649 Store(\_SB.PCI0.GPCB(), Local0) // MMIO Base address 650 651 Add(Local0, ShiftLeft(TBTD(Arg0, Arg1), 15), Local0) // Device no 652 Add(Local0, ShiftLeft(TBTF(Arg0, Arg1), 12), Local0) // Function no 653 654 ADBG("ADR:") 655 ADBG(Local0) 656 657 OperationRegion (MMMM, SystemMemory, Local0, 0x30) 658 Field (MMMM, AnyAcc, NoLock, Preserve) 659 { 660 CMDS, 32, 661 Offset(0x19), 662 SBUS, 8, 663 SBU5, 8, 664 Offset(0x1C), 665 SEIO, 32, 666 MMBL, 32, 667 PMBL, 32, 668 669 } 670 671 ADBG("Pmem of TBT RP:") 672 ADBG(PMBL) 673 674 Return(PMBL) 675 } // End of Method(TSUP, 0, Serialized) 676 677 // 678 // Wait for secondary bus in TBT RP 679 // Input: Arg0 -> Tbt Root Port value from Tbt NVS 680 // Input: Arg1 -> Tbt port type value from Tbt NVS 681 // 682 683 Method(WSUB, 2, Serialized) 684 { 685 ADBG(Concatenate("WSUB=", ToHexString(Arg0))) 686 ADBG(ToHexString(Timer)) 687 688 Store(0, Local0) 689 Store(0, Local1) 690 While(1) 691 { 692 Store(TSUP(Arg0, Arg1), Local1) 693 If(LGreater(Local1, 0x1FFF1)) 694 { 695 ADBG("WSUB-Finished") 696 Break 697 } 698 Else 699 { 700 Add(Local0, 1, Local0) 701 If(LGreater(Local0, 1000)) 702 { 703 Sleep(1000) 704 ADBG("WSUB-Deadlock") 705 } 706 Else 707 { 708 Sleep(16) 709 } 710 } 711 } 712 ADBG(Concatenate("WSUb=", ToHexString(Local1))) 713 } // End of Method(WSUB) 714 715 // Wait for _WAK finished 716 Method(WWAK) 717 { 718 ADBG("WWAK") 719 720 Wait(WFEV, 0xFFFF) 721 Signal(WFEV) // Set it, to enter on next HP 722 } // End of Method(WWAK) 723 724 Method(NTFY, 2, Serialized) 725 { 726 ADBG("NTFY") 727 728 If(LEqual(NOHP,1)) 729 { 730 If (LEqual(Arg1, DTBT_TYPE_PCH)) { 731 Switch(ToInteger(Arg0)) // TBT Selector 732 { 733 Case (1) 734 { 735 ADBG("Notify RP01") 736 Notify(\_SB.PCI0.RP01,0) 737 } 738 Case (2) 739 { 740 ADBG("Notify RP02") 741 Notify(\_SB.PCI0.RP02,0) 742 } 743 Case (3) 744 { 745 ADBG("Notify RP03") 746 Notify(\_SB.PCI0.RP03,0) 747 } 748 Case (4) 749 { 750 ADBG("Notify RP04") 751 Notify(\_SB.PCI0.RP04,0) 752 } 753 Case (5) 754 { 755 ADBG("Notify RP05") 756 Notify(\_SB.PCI0.RP05,0) 757 } 758 Case (6) 759 { 760 ADBG("Notify RP06") 761 Notify(\_SB.PCI0.RP06,0) 762 } 763 Case (7) 764 { 765 ADBG("Notify RP07") 766 Notify(\_SB.PCI0.RP07,0) 767 } 768 Case (8) 769 { 770 ADBG("Notify RP08") 771 Notify(\_SB.PCI0.RP08,0) 772 } 773 Case (9) 774 { 775 ADBG("Notify RP09") 776 Notify(\_SB.PCI0.RP09,0) 777 } 778 Case (10) 779 { 780 ADBG("Notify RP10") 781 Notify(\_SB.PCI0.RP10,0) 782 } 783 Case (11) 784 { 785 ADBG("Notify RP11") 786 Notify(\_SB.PCI0.RP11,0) 787 } 788 Case (12) 789 { 790 ADBG("Notify RP12") 791 Notify(\_SB.PCI0.RP12,0) 792 } 793 Case (13) 794 { 795 ADBG("Notify RP13") 796 Notify(\_SB.PCI0.RP13,0) 797 } 798 Case (14) 799 { 800 ADBG("Notify RP14") 801 Notify(\_SB.PCI0.RP14,0) 802 } 803 Case (15) 804 { 805 ADBG("Notify RP15") 806 Notify(\_SB.PCI0.RP15,0) 807 } 808 Case (16) 809 { 810 ADBG("Notify RP16") 811 Notify(\_SB.PCI0.RP16,0) 812 } 813 Case (17) 814 { 815 ADBG("Notify RP17") 816 Notify(\_SB.PCI0.RP17,0) 817 } 818 Case (18) 819 { 820 ADBG("Notify RP18") 821 Notify(\_SB.PCI0.RP18,0) 822 } 823 Case (19) 824 { 825 ADBG("Notify RP19") 826 Notify(\_SB.PCI0.RP19,0) 827 } 828 Case (20) 829 { 830 ADBG("Notify RP20") 831 Notify(\_SB.PCI0.RP20,0) 832 } 833 Case (21) 834 { 835 ADBG("Notify RP21") 836 Notify(\_SB.PCI0.RP21,0) 837 } 838 Case (22) 839 { 840 ADBG("Notify RP22") 841 Notify(\_SB.PCI0.RP22,0) 842 } 843 Case (23) 844 { 845 ADBG("Notify RP23") 846 Notify(\_SB.PCI0.RP23,0) 847 } 848 Case (24) 849 { 850 ADBG("Notify RP24") 851 Notify(\_SB.PCI0.RP24,0) 852 } 853 }//Switch(ToInteger(TBSS)) // TBT Selector 854 } ElseIf (LEqual(Arg1, DTBT_TYPE_PEG)) { 855 Switch(ToInteger(Arg0)) 856 { 857 Case (1) 858 { 859 ADBG("Notify PEG0") 860 Notify(\_SB.PCI0.PEG0,0) 861 } 862 Case (2) 863 { 864 ADBG("Notify PEG1") 865 Notify(\_SB.PCI0.PEG1,0) 866 } 867 Case (3) 868 { 869 ADBG("Notify PEG2") 870 Notify(\_SB.PCI0.PEG2,0) 871 } 872#ifndef CPU_CFL 873 Case (4) 874 { 875 ADBG("Notify PEG3") 876 Notify(\_SB.PCI0.PEG3,0) 877 } 878#endif 879 } 880 }//Switch(ToInteger(TBSS)) // TBT Selector 881 }//If(NOHP()) 882 P8XH(0,0xC2) 883 P8XH(1,0xC2) 884 }// End of Method(NTFY) 885 886// 887// TBT BIOS, GPIO 5 filtering, 888// Hot plug of 12V USB devices, into TBT host router, cause electrical noise on PCH GPIOs, 889// This noise cause false hot-plug events, and negatively influence BIOS assisted hot-plug. 890// SKL-PCH GPIO does not implement Glitch Filter logic (refer to GPIO HAS) on any GPIO pad. Native functions have to implement their own digital glitch-filter logic 891// if needed. As HW filter was not implemented on SKL PCH, because of that SW workaround should be implemented in BIOS. 892// Register 0x544(Bios mailbox) bit 0 definition: 893// if BIOS reads bit as 1, BIOS will clear the bit and continue normal flow, if bit is 0 BIOS will exit from method 894// 895 896 Method(GNIS,2, Serialized) 897 { 898 899 ADBG("GNIS") 900 If(LEqual(GP5F, 0)) 901 { 902 ADBG("GNIS_Dis=0") 903 Return(0) 904 } 905 // 906 // BIOS mailbox command for GPIO filter 907 // 908 Add(MMTB(Arg0, Arg1), 0x544, Local0) 909 OperationRegion(PXVD,SystemMemory,Local0,0x08) 910 911 Field(PXVD,DWordAcc, NoLock, Preserve) 912 { 913 HPFI, 1, 914 Offset(0x4), 915 TB2P, 32 916 } 917 Store(TB2P, Local1) 918 ADBG(Concatenate("TB2P=", ToHexString(Local1))) 919 If(LEqual(Local1, 0xFFFFFFFF)) // Disconnect? 920 { 921 ADBG("GNIS=0") 922 Return(0) 923 } 924 Store(HPFI, Local2) 925 ADBG(Concatenate("HPFI=", ToHexString(Local2))) 926 If(LEqual(Local2, 0x01)) 927 { 928 Store(0x00, HPFI) 929 ADBG("GNIS=0") 930 Return(0) 931 } 932 // Any other values treated as a GPIO noise 933 ADBG("GNIS=1") 934 Return(1) 935 } 936 937 Method(CHKP,2, Serialized) 938 { 939 Add(MMTB(Arg0, Arg1), 0x544, Local0) 940 OperationRegion(PXVE,SystemMemory,Local0,0x08) 941 942 Field(PXVE,DWordAcc, NoLock, Preserve) 943 { 944 HPFI, 1, 945 Offset(0x4), 946 TB2P, 32 947 } 948 Store(TB2P, Local1) 949 And(Local1,BIT29,Local1) 950 ADBG(Concatenate("Local1=", ToHexString(Local1))) 951 //ADBG(Concatenate("BIT29=", ToHexString(LAnd(Local1,BIT29)))) 952 If(LEqual(Local1, BIT29)) 953 { 954 Return(1) 955 } 956 Else 957 { 958 Return(0) 959 } 960 } 961 962 // 963 // Method to Handle enumerate PCIe structure through 964 // SMI for Thunderbolt(TM) devices 965 // 966 Method(XTBT,2, Serialized) 967 { 968 ADBG("XTBT") 969 ADBG("RP :") 970 ADBG(Arg0) 971 Store(Arg0, DTCP) // Root port to enumerate 972 Store(Arg1, DTPT) // Root port Type 973 If(LEqual(Arg0, RPS0)) { 974 Store (1, Local0) 975 } ElseIf (LEqual(Arg0, RPS1)) { 976 Store (2, Local0) 977 } Else { 978 Store (0, Local0) 979 Return () 980 } 981 982 If (TRDO) { 983 ADBG("Durng TBT_ON") 984 Return () 985 } 986 987 If (TRD3) { 988 ADBG("During TBT_OFF") 989 Return () 990 } 991 WWAK() 992 WSUB(Arg0, Arg1) 993 If(GNIS(Arg0, Arg1)) 994 { 995 Return() 996 } 997 998 OperationRegion(SPRT,SystemIO, 0xB2,2) 999 Field (SPRT, ByteAcc, Lock, Preserve) 1000 { 1001 SSMP, 8 1002 } 1003 1004 ADBG("TBT-HP-Handler") 1005 1006 Acquire(OSUM, 0xFFFF) 1007 Store(TBFF(Arg0, Arg1), Local1) 1008 If(LEqual(Local1, 1))// Only HR 1009 { 1010 Sleep(16) 1011 Release(OSUM) 1012 ADBG("OS_Up_Received") 1013 Return () 1014 } 1015 If(LEqual(Local1, 2)) // Disconnect 1016 { 1017 NTFY(Arg0, Arg1) 1018 Sleep(16) 1019 Release(OSUM) 1020 ADBG("Disconnect") 1021 Return () 1022 } 1023 1024 // HR and EP 1025 If(LEqual(SOHP, 1)) 1026 { 1027 // Trigger SMI to enumerate PCIe Structure 1028 ADBG("TBT SW SMI") 1029 Store(21, TBSF) 1030 Store(0xF7, SSMP) 1031 } 1032 NTFY(Arg0, Arg1) 1033 Sleep(16) 1034 Release(OSUM) 1035 1036 ADBG("End-of-XTBT") 1037 } // End of Method(XTBT) 1038 1039 // 1040 // Calling Method to Handle enumerate PCIe structure through 1041 // SMI for Thunderbolt(TM) devices for Tier 1 GPIOs 1042 // Used in Two ways , 1043 // If CIO GPIO(1 Tier) is Different for the Controllers, this will be used as 1 Tier GPIO Handler for 1st controller 1044 // If CIO GPIO(1 Tier) is Same for all the controllers, this will be used as 1 Tier GPIO Handler for All the controllers 1045 // 1046 Method(ATBT) 1047 { 1048 ADBG("ATBT") 1049 // 1050 // Calling Method to Handle enumerate PCIe structure through 1051 // 1052 If(LEqual(CGST,0)) { // If GPIO is Different for each controller 1053 If(LEqual(RPN0,1)) 1054 { 1055 XTBT(RPS0, RPT0) 1056 } 1057 } Else { 1058 If(LEqual(RPN0,1)) 1059 { 1060 XTBT(RPS0, RPT0) 1061 } 1062 ElseIf(LEqual(RPN1,1)) 1063 { 1064 XTBT(RPS1, RPT1) 1065 } 1066 } 1067 ADBG("End-of-ATBT") 1068 } // End of Method(ATBT) 1069 1070 Method(BTBT) 1071 { 1072 ADBG("BTBT") 1073 // 1074 // Calling Method to Handle enumerate PCIe structure through 1075 // 1076 If(LEqual(CGST,0)) { // If GPIO is Different for each controller 1077 If(LEqual(RPN1,1)) 1078 { 1079 XTBT(RPS1, RPT1) 1080 } 1081 } 1082 ADBG("End-of-BTBT") 1083 } // End of Method(BTBT) 1084 // 1085 // Method to call OSPU Mail box command 1086 // Arg0 : Controller type 0x00 : Discrete 0x80 : Integrated TBT 1087 // Arg1 : TBT RP Selector / DMA 1088 // Arg2 : TBT Type (PCH or PEG) 1089 // 1090 Method(TINI, 3, Serialized) 1091 { 1092 ADBG("TINI") 1093 If(Lequal (Arg0, DTBT_CONTROLLER)) 1094 { 1095 //ADBG("DTBT") 1096 Store(MMRP(Arg1, Arg2), Local0) 1097 OperationRegion(RP_X,SystemMemory,Local0,0x20) 1098 Field(RP_X,DWordAcc, NoLock, Preserve) 1099 { 1100 REG0, 32, 1101 REG1, 32, 1102 REG2, 32, 1103 REG3, 32, 1104 REG4, 32, 1105 REG5, 32, 1106 REG6, 32, 1107 REG7, 32 1108 } 1109 Store(REG6, Local1) 1110 Store(0x00F0F000, REG6) 1111 Store(MMTB(Arg1, Arg2), Local2) 1112 OSUP(Local2, DTBT_CONTROLLER) 1113 Store(Local1, REG6) 1114 } 1115 ADBG("End-of-TINI") 1116 } 1117 1118} // End of Scope (\_GPE) 1119 1120Scope (\_SB) 1121{ 1122 // 1123 // The code needs to be executed for TBT Hotplug Handler event (2-tier GPI GPE event architecture) is presented here 1124 // 1125 Method(THDR, 3, Serialized) 1126 { 1127 ADBG("THDR") 1128 \_SB.CAGS(Arg0) 1129 \_GPE.XTBT(Arg1, Arg2) 1130 } // End of Method(THDR, 3, Serialized) 1131} // End of Scope(\_SB) 1132 1133Scope (\_SB) 1134{ 1135 // 1136 // Name: CGWR [Combined GPIO Write] 1137 // Description: Function to write into GPIO 1138 // Input: Arg0 -> GpioPad / Expander pin 1139 // Arg1 -> Value 1140 // Return: Nothing 1141 // 1142 Method(CGWR, 2, Serialized) 1143 { 1144 // PCH 1145 If (CondRefOf(\_SB.SGOV)) 1146 { 1147 \_SB.SGOV(Arg0, Arg1) 1148 } 1149 } // End of Method(CGWR, 4, Serialized) 1150 1151 // 1152 // Name: CGRD [Combined GPIO Read] 1153 // Description: Function to read from GPIO 1154 // Input: Arg0 -> GpioPad / Expander pin 1155 // Arg1 -> 0: GPO [GPIO TX State] 1156 // 1: GPI [GPIO RX State] 1157 // Return: Value 1158 // 1159 Method(CGRD, 2, Serialized) 1160 { 1161 Store(1, Local0) 1162 // PCH 1163 If (LEqual(Arg1, 0)) 1164 { 1165 // GPIO TX State 1166 If (CondRefOf(\_SB.GGOV)) 1167 { 1168 Store(\_SB.GGOV(Arg0), Local0) 1169 } 1170 } 1171 ElseIf (LEqual(Arg1, 1)) 1172 { 1173 // GPIO RX State 1174 If (CondRefOf(\_SB.GGIV)) 1175 { 1176 Store(\_SB.GGIV(Arg0), Local0) 1177 } 1178 } 1179 Return(Local0) 1180 } // End of Method(CGRD, 4, Serialized) 1181 // 1182 // Name: WRGP [GPIO Write] 1183 // Description: Function to write into GPIO 1184 // Input: Arg0 -> COMMON_GPIO_CONFIG GpioInfo 1185 // Arg1 -> Value 1186 // Return: Nothing 1187 // 1188 Method(WRGP, 2, Serialized) 1189 { 1190 Store(Arg0, Local0) 1191 Store(Arg0, Local1) 1192 And(Local0, 0xFFFFFFFF, Local0) // Low 32 bits (31:00) 1193 ShiftRight(Local1, 32, Local1) // High 32 bits (63:32) 1194 If (LEqual(And(Local0, 0xFF), 1)) 1195 { 1196 // PCH 1197 \_SB.CGWR(Local1, Arg1) 1198 } 1199 } // End of Method(WRGP, 2, Serialized) 1200 1201 // 1202 // Name: RDGP [GPIO Read] 1203 // Description: Function to write into GPIO 1204 // Input: Arg0 -> COMMON_GPIO_CONFIG GpioInfo 1205 // Arg1 -> In case of PCH Gpio Read {GPIO TX(0)/RX(1) State indicator} 1206 // Return: Value 1207 // 1208 Method(RDGP, 2, Serialized) 1209 { 1210 Store(1, Local7) 1211 Store(Arg0, Local0) 1212 Store(Arg0, Local1) 1213 And(Local0, 0xFFFFFFFF, Local0) // Low 32 bits (31:00) 1214 ShiftRight(Local1, 32, Local1) // High 32 bits (63:32) 1215 If (LEqual(And(Local0, 0xFF), 1)) 1216 { 1217 // PCH 1218 Store(\_SB.CGRD(Local1, Arg1), Local7) 1219 } 1220 Return(Local7) 1221 } // End of Method(RDGP, 2, Serialized) 1222 1223} // End of Scope(\_SB) 1224 1225Scope(\_SB) 1226{ 1227 // Asserts/De-asserts TBT force power 1228 Method(TBFP, 2) 1229 { 1230 If(Arg0) 1231 { 1232 // Implementation dependent way to assert TBT force power 1233 If(LEqual(Arg1, 1)) { 1234 CGWR(FPG0, FP0L) 1235 } 1236 Else { 1237 CGWR(FPG1, FP1L) 1238 } 1239 } 1240 Else 1241 { 1242 // Implementation dependent way to de-assert TBT force power 1243 If(LEqual(Arg1, 1)) { 1244 CGWR(FPG0, LNot(FP0L)) 1245 } 1246 Else { 1247 CGWR(FPG1, LNot(FP1L)) 1248 } 1249 } 1250 } 1251 1252 // WMI ACPI device to control TBT force power 1253 Device(WMTF) 1254 { 1255 // pnp0c14 is pnp id assigned to WMI mapper 1256 Name(_HID, "PNP0C14") 1257 Name(_UID, "TBFP") 1258 1259 Name(_WDG, Buffer() { 1260 // {86CCFD48-205E-4A77-9C48-2021CBEDE341} 1261 0x48, 0xFD, 0xCC, 0x86, 1262 0x5E, 0x20, 1263 0x77, 0x4A, 1264 0x9C, 0x48, 1265 0x20, 0x21, 0xCB, 0xED, 0xE3, 0x41, 1266 84, 70, // Object Id (TF) 1267 1, // Instance Count 1268 0x02 // Flags (WMIACPI_REGFLAG_METHOD) 1269 }) 1270 1271 // Set TBT force power 1272 // Arg2 is force power value 1273 Method(WMTF, 3) 1274 { 1275 CreateByteField(Arg2,0,FP) 1276 1277 If(FP) 1278 { 1279 TBFP(1, 1) 1280 } 1281 Else 1282 { 1283 TBFP(0, 1) 1284 } 1285 } 1286 } 1287} // End of Scope(\_SB) 1288 1289 1290If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 1),LEqual(RPS1, 1)))) 1291{ 1292 Scope(\_SB.PCI0.RP01) 1293 { 1294 Device(HRUS)// Host router Upstream port 1295 { 1296 Name(_ADR, 0x00000000) 1297 1298 Method(_RMV) 1299 { 1300 Return(TARS) 1301 } // end _RMV 1302 } 1303 }//End of Scope(\_SB.PCI0.RP01) 1304} 1305 1306If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 2),LEqual(RPS1, 2)))) 1307{ 1308 Scope(\_SB.PCI0.RP02) 1309 { 1310 Device(HRUS)// Host router Upstream port 1311 { 1312 Name(_ADR, 0x00000000) 1313 1314 Method(_RMV) 1315 { 1316 Return(TARS) 1317 } // end _RMV 1318 } 1319 }//End of Scope(\_SB.PCI0.RP02) 1320} 1321 1322If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 3),LEqual(RPS1, 3)))) 1323{ 1324 Scope(\_SB.PCI0.RP03) 1325 { 1326 Device(HRUS)// Host router Upstream port 1327 { 1328 Name(_ADR, 0x00000000) 1329 1330 Method(_RMV) 1331 { 1332 Return(TARS) 1333 } // end _RMV 1334 } 1335 }//End of Scope(\_SB.PCI0.RP03) 1336} 1337 1338If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 4),LEqual(RPS1, 4)))) 1339{ 1340 Scope(\_SB.PCI0.RP04) 1341 { 1342 Device(HRUS)// Host router Upstream port 1343 { 1344 Name(_ADR, 0x00000000) 1345 1346 Method(_RMV) 1347 { 1348 Return(TARS) 1349 } // end _RMV 1350 } 1351 }//End of Scope(\_SB.PCI0.RP04) 1352} 1353 1354If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 5),LEqual(RPS1, 5)))) 1355{ 1356 Scope(\_SB.PCI0.RP05) 1357 { 1358 Device(HRUS)// Host router Upstream port 1359 { 1360 Name(_ADR, 0x00000000) 1361 1362 Method(_RMV) 1363 { 1364 Return(TARS) 1365 } // end _RMV 1366 } 1367 }//End of Scope(\_SB.PCI0.RP05) 1368} 1369 1370If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 6),LEqual(RPS1, 6)))) 1371{ 1372 Scope(\_SB.PCI0.RP06) 1373 { 1374 Device(HRUS)// Host router Upstream port 1375 { 1376 Name(_ADR, 0x00000000) 1377 1378 Method(_RMV) 1379 { 1380 Return(TARS) 1381 } // end _RMV 1382 } 1383 }//End of Scope(\_SB.PCI0.RP06) 1384} 1385 1386If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 7),LEqual(RPS1, 7)))) 1387{ 1388 Scope(\_SB.PCI0.RP07) 1389 { 1390 Device(HRUS)// Host router Upstream port 1391 { 1392 Name(_ADR, 0x00000000) 1393 1394 Method(_RMV) 1395 { 1396 Return(TARS) 1397 } // end _RMV 1398 } 1399 }//End of Scope(\_SB.PCI0.RP07) 1400} 1401 1402If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 8),LEqual(RPS1, 8)))) 1403{ 1404 Scope(\_SB.PCI0.RP08) 1405 { 1406 Device(HRUS)// Host router Upstream port 1407 { 1408 Name(_ADR, 0x00000000) 1409 1410 Method(_RMV) 1411 { 1412 Return(TARS) 1413 } // end _RMV 1414 } 1415 }//End of Scope(\_SB.PCI0.RP08) 1416} 1417 1418If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 9),LEqual(RPS1, 9)))) 1419{ 1420 Scope(\_SB.PCI0.RP09) 1421 { 1422 Device(HRUS)// Host router Upstream port 1423 { 1424 Name(_ADR, 0x00000000) 1425 1426 Method(_RMV) 1427 { 1428 Return(TARS) 1429 } // end _RMV 1430 } 1431 }//End of Scope(\_SB.PCI0.RP09) 1432} 1433 1434If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 10),LEqual(RPS1, 10)))) 1435{ 1436 Scope(\_SB.PCI0.RP10) 1437 { 1438 Device(HRUS)// Host router Upstream port 1439 { 1440 Name(_ADR, 0x00000000) 1441 1442 Method(_RMV) 1443 { 1444 Return(TARS) 1445 } // end _RMV 1446 } 1447 }//End of Scope(\_SB.PCI0.RP10) 1448} 1449 1450If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 11),LEqual(RPS1, 11)))) 1451{ 1452 Scope(\_SB.PCI0.RP11) 1453 { 1454 Device(HRUS)// Host router Upstream port 1455 { 1456 Name(_ADR, 0x00000000) 1457 1458 Method(_RMV) 1459 { 1460 Return(TARS) 1461 } // end _RMV 1462 } 1463 }//End of Scope(\_SB.PCI0.RP11) 1464} 1465 1466If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 12),LEqual(RPS1, 12)))) 1467{ 1468 Scope(\_SB.PCI0.RP12) 1469 { 1470 Device(HRUS)// Host router Upstream port 1471 { 1472 Name(_ADR, 0x00000000) 1473 1474 Method(_RMV) 1475 { 1476 Return(TARS) 1477 } // end _RMV 1478 } 1479 }//End of Scope(\_SB.PCI0.RP12) 1480} 1481 1482If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 13),LEqual(RPS1, 13)))) 1483{ 1484 Scope(\_SB.PCI0.RP13) 1485 { 1486 Device(HRUS)// Host router Upstream port 1487 { 1488 Name(_ADR, 0x00000000) 1489 1490 Method(_RMV) 1491 { 1492 Return(TARS) 1493 } // end _RMV 1494 } 1495 }//End of Scope(\_SB.PCI0.RP13) 1496} 1497 1498If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 14),LEqual(RPS1, 14)))) 1499{ 1500 Scope(\_SB.PCI0.RP14) 1501 { 1502 Device(HRUS)// Host router Upstream port 1503 { 1504 Name(_ADR, 0x00000000) 1505 1506 Method(_RMV) 1507 { 1508 Return(TARS) 1509 } // end _RMV 1510 } 1511 }//End of Scope(\_SB.PCI0.RP14) 1512} 1513 1514If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 15),LEqual(RPS1, 15)))) 1515{ 1516 Scope(\_SB.PCI0.RP15) 1517 { 1518 Device(HRUS)// Host router Upstream port 1519 { 1520 Name(_ADR, 0x00000000) 1521 1522 Method(_RMV) 1523 { 1524 Return(TARS) 1525 } // end _RMV 1526 } 1527 }//End of Scope(\_SB.PCI0.RP15) 1528} 1529 1530If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 16),LEqual(RPS1, 16)))) 1531{ 1532 Scope(\_SB.PCI0.RP16) 1533 { 1534 Device(HRUS)// Host router Upstream port 1535 { 1536 Name(_ADR, 0x00000000) 1537 1538 Method(_RMV) 1539 { 1540 Return(TARS) 1541 } // end _RMV 1542 } 1543 }//End of Scope(\_SB.PCI0.RP16) 1544} 1545 1546If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 17),LEqual(RPS1, 17)))) 1547{ 1548 Scope(\_SB.PCI0.RP17) 1549 { 1550 Device(HRUS)// Host router Upstream port 1551 { 1552 Name(_ADR, 0x00000000) 1553 1554 Method(_RMV) 1555 { 1556 Return(TARS) 1557 } // end _RMV 1558 } 1559 }//End of Scope(\_SB.PCI0.RP17) 1560} 1561 1562If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 18),LEqual(RPS1, 18)))) 1563{ 1564 Scope(\_SB.PCI0.RP18) 1565 { 1566 Device(HRUS)// Host router Upstream port 1567 { 1568 Name(_ADR, 0x00000000) 1569 1570 Method(_RMV) 1571 { 1572 Return(TARS) 1573 } // end _RMV 1574 } 1575 }//End of Scope(\_SB.PCI0.RP18) 1576} 1577 1578If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 19),LEqual(RPS1, 19)))) 1579{ 1580 Scope(\_SB.PCI0.RP19) 1581 { 1582 Device(HRUS)// Host router Upstream port 1583 { 1584 Name(_ADR, 0x00000000) 1585 1586 Method(_RMV) 1587 { 1588 Return(TARS) 1589 } // end _RMV 1590 } 1591 }//End of Scope(\_SB.PCI0.RP19) 1592} 1593 1594If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 20),LEqual(RPS1, 20)))) 1595{ 1596 Scope(\_SB.PCI0.RP20) 1597 { 1598 Device(HRUS)// Host router Upstream port 1599 { 1600 Name(_ADR, 0x00000000) 1601 1602 Method(_RMV) 1603 { 1604 Return(TARS) 1605 } // end _RMV 1606 } 1607 }//End of Scope(\_SB.PCI0.RP20) 1608} 1609 1610If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 21),LEqual(RPS1, 21)))) 1611{ 1612 Scope(\_SB.PCI0.PEG0) 1613 { 1614 Device(HRUS)// Host router Upstream port 1615 { 1616 Name(_ADR, 0x00000000) 1617 1618 Method(_RMV) 1619 { 1620 Return(TARS) 1621 } // end _RMV 1622 } 1623 }//End of Scope(\_SB.PCI0.PEG0) 1624} 1625 1626If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 22),LEqual(RPS1, 22)))) 1627{ 1628 Scope(\_SB.PCI0.PEG1) 1629 { 1630 Device(HRUS)// Host router Upstream port 1631 { 1632 Name(_ADR, 0x00000000) 1633 1634 Method(_RMV) 1635 { 1636 Return(TARS) 1637 } // end _RMV 1638 } 1639 }//End of Scope(\_SB.PCI0.PEG1) 1640} 1641 1642If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 23),LEqual(RPS1, 23)))) 1643{ 1644 Scope(\_SB.PCI0.PEG2) 1645 { 1646 Device(HRUS)// Host router Upstream port 1647 { 1648 Name(_ADR, 0x00000000) 1649 1650 Method(_RMV) 1651 { 1652 Return(TARS) 1653 } // end _RMV 1654 } 1655 }//End of Scope(\_SB.PCI0.PEG2) 1656} 1657 1658Scope(\_SB) 1659{ 1660 // 1661 // Name: PERB 1662 // Description: Function to read a Byte from PCIE-MMIO 1663 // Input: Arg0 -> PCIE base address 1664 // Arg1 -> Bus 1665 // Arg2 -> Device 1666 // Arg3 -> Function 1667 // Arg4 -> Register offset 1668 // Return: Byte data read from PCIE-MMIO 1669 // 1670 Method(PERB,5,Serialized) 1671 { 1672 ADBG("PERB") 1673 1674 Store(Arg0, Local7) 1675 Or(Local7, ShiftLeft(Arg1, 20), Local7) 1676 Or(Local7, ShiftLeft(Arg2, 15), Local7) 1677 Or(Local7, ShiftLeft(Arg3, 12), Local7) 1678 Or(Local7, Arg4, Local7) 1679 1680 OperationRegion(PCI0, SystemMemory, Local7, 1) 1681 Field(PCI0, ByteAcc,NoLock,Preserve) 1682 { 1683 TEMP, 8 1684 } 1685 1686 Return(TEMP) 1687 } // End of Method(PERB,5,Serialized) 1688 1689 // 1690 // Name: PEWB 1691 // Description: Function to write a Byte into PCIE-MMIO 1692 // Input: Arg0 -> PCIE base address 1693 // Arg1 -> Bus 1694 // Arg2 -> Device 1695 // Arg3 -> Function 1696 // Arg4 -> Register offset 1697 // Arg5 -> Data 1698 // Return: Nothing 1699 // 1700 Method(PEWB,6,Serialized) 1701 { 1702 ADBG("PEWB") 1703 1704 Store(Arg0, Local7) 1705 Or(Local7, ShiftLeft(Arg1, 20), Local7) 1706 Or(Local7, ShiftLeft(Arg2, 15), Local7) 1707 Or(Local7, ShiftLeft(Arg3, 12), Local7) 1708 Or(Local7, Arg4, Local7) 1709 1710 OperationRegion(PCI0, SystemMemory, Local7, 1) 1711 Field(PCI0, ByteAcc,NoLock,Preserve) 1712 { 1713 TEMP, 8 1714 } 1715 1716 Store(Arg5,TEMP) 1717 } // End of Method(PEWB,6,Serialized) 1718 1719 // 1720 // Name: PERW 1721 // Description: Function to read a Word from PCIE-MMIO 1722 // Input: Arg0 -> PCIE base address 1723 // Arg1 -> Bus 1724 // Arg2 -> Device 1725 // Arg3 -> Function 1726 // Arg4 -> Register offset 1727 // Return: Word data read from PCIE-MMIO 1728 // 1729 Method(PERW,5,Serialized) 1730 { 1731 ADBG("PERW") 1732 1733 Store(Arg0, Local7) 1734 Or(Local7, ShiftLeft(Arg1, 20), Local7) 1735 Or(Local7, ShiftLeft(Arg2, 15), Local7) 1736 Or(Local7, ShiftLeft(Arg3, 12), Local7) 1737 Or(Local7, Arg4, Local7) 1738 1739 OperationRegion(PCI0, SystemMemory, Local7, 2) 1740 Field(PCI0, ByteAcc,NoLock,Preserve) 1741 { 1742 TEMP, 16 1743 } 1744 1745 Return(TEMP) 1746 } // End of Method(PERW,5,Serialized) 1747 1748 // 1749 // Name: PEWW 1750 // Description: Function to write a Word into PCIE-MMIO 1751 // Input: Arg0 -> PCIE base address 1752 // Arg1 -> Bus 1753 // Arg2 -> Device 1754 // Arg3 -> Function 1755 // Arg4 -> Register offset 1756 // Arg5 -> Data 1757 // Return: Nothing 1758 // 1759 Method(PEWW,6,Serialized) 1760 { 1761 ADBG("PEWW") 1762 1763 Store(Arg0, Local7) 1764 Or(Local7, ShiftLeft(Arg1, 20), Local7) 1765 Or(Local7, ShiftLeft(Arg2, 15), Local7) 1766 Or(Local7, ShiftLeft(Arg3, 12), Local7) 1767 Or(Local7, Arg4, Local7) 1768 1769 OperationRegion(PCI0, SystemMemory, Local7, 2) 1770 Field(PCI0, ByteAcc,NoLock,Preserve) 1771 { 1772 TEMP, 16 1773 } 1774 1775 Store(Arg5,TEMP) 1776 } // End of Method(PEWW,6,Serialized) 1777 1778 // 1779 // Name: PERD 1780 // Description: Function to read a Dword from PCIE-MMIO 1781 // Input: Arg0 -> PCIE base address 1782 // Arg1 -> Bus 1783 // Arg2 -> Device 1784 // Arg3 -> Function 1785 // Arg4 -> Register offset 1786 // Return: Dword data read from PCIE-MMIO 1787 // 1788 Method(PERD,5,Serialized) 1789 { 1790 ADBG("PERD") 1791 1792 Store(Arg0, Local7) 1793 Or(Local7, ShiftLeft(Arg1, 20), Local7) 1794 Or(Local7, ShiftLeft(Arg2, 15), Local7) 1795 Or(Local7, ShiftLeft(Arg3, 12), Local7) 1796 Or(Local7, Arg4, Local7) 1797 1798 OperationRegion(PCI0, SystemMemory, Local7, 4) 1799 Field(PCI0, ByteAcc,NoLock,Preserve) 1800 { 1801 TEMP, 32 1802 } 1803 1804 Return(TEMP) 1805 } // End of Method(PERD,5,Serialized) 1806 1807 // 1808 // Name: PEWD 1809 // Description: Function to write a Dword into PCIE-MMIO 1810 // Input: Arg0 -> PCIE base address 1811 // Arg1 -> Bus 1812 // Arg2 -> Device 1813 // Arg3 -> Function 1814 // Arg4 -> Register offset 1815 // Arg5 -> Data 1816 // Return: Nothing 1817 // 1818 Method(PEWD,6,Serialized) 1819 { 1820 ADBG("PEWD") 1821 1822 Store(Arg0, Local7) 1823 Or(Local7, ShiftLeft(Arg1, 20), Local7) 1824 Or(Local7, ShiftLeft(Arg2, 15), Local7) 1825 Or(Local7, ShiftLeft(Arg3, 12), Local7) 1826 Or(Local7, Arg4, Local7) 1827 1828 OperationRegion(PCI0, SystemMemory, Local7, 4) 1829 Field(PCI0, ByteAcc,NoLock,Preserve) 1830 { 1831 TEMP, 32 1832 } 1833 1834 Store(Arg5,TEMP) 1835 } // End of Method(PEWD,6,Serialized) 1836 1837 // 1838 // Name: STDC 1839 // Description: Function to get Standard Capability Register Offset 1840 // Input: Arg0 -> PCIE base address 1841 // Arg1 -> Bus 1842 // Arg2 -> Device 1843 // Arg3 -> Function 1844 // Arg4 -> Capability ID 1845 // Return: Capability Register Offset data 1846 // 1847 Method(STDC,5,Serialized) 1848 { 1849 ADBG("STDC") 1850 1851 //Check for Referenced device is present or not 1852 Store(PERW(Arg0, Arg1, Arg2, Arg3, 0x00), Local7) //Vendor ID register 1853 If(LEqual(Local7, 0xFFFF)) 1854 { 1855 ADBG("Referenced device is not present") 1856 Return(0) 1857 } 1858 1859 Store(PERW(Arg0, Arg1, Arg2, Arg3, 0x06), Local0) //Device Status register 1860 If (LEqual(And(Local0, 16), 0)) //Bit4 - Capabilities List 1861 { 1862 //No Capabilities linked list is available 1863 ADBG("No Capabilities linked list is available") 1864 Return(0) 1865 } 1866 1867 //Local1 is for storing CapabilityID 1868 //Local2 is for storing CapabilityPtr 1869 Store(PERB(Arg0, Arg1, Arg2, Arg3, 0x34), Local2) //CapabilityPtr 1870 1871 While(1) 1872 { 1873 And(Local2, 0xFC, Local2) //Each capability must be DWORD aligned 1874 1875 If(LEqual(Local2, 0)) //A pointer value of 00h is used to indicate the last capability in the list 1876 { 1877 ADBG("Capability ID is not found") 1878 Return(0) 1879 } 1880 1881 Store(PERB(Arg0, Arg1, Arg2, Arg3, Local2), Local1) //CapabilityID 1882 1883 If(LEqual(Arg4, Local1)) //CapabilityID match 1884 { 1885 ADBG("Capability ID is found") 1886 ADBG("Capability Offset : ") 1887 ADBG(Local2) 1888 Return(Local2) 1889 } 1890 Store(PERB(Arg0, Arg1, Arg2, Arg3, Add(Local2, 1)), Local2) //CapabilityPtr 1891 Return(0) 1892 } 1893 } // End of Method(STDC,5,Serialized) 1894 1895} // End Scope(\_SB) 1896