1 /** @file 2 Pcie root port policy 3 4 Copyright (c) 2019 Intel Corporation. All rights reserved. <BR> 5 6 SPDX-License-Identifier: BSD-2-Clause-Patent 7 **/ 8 9 #ifndef _PCH_PCIE_CONFIG_H_ 10 #define _PCH_PCIE_CONFIG_H_ 11 12 #include <PchLimits.h> 13 14 #define PCIE_RP_CONFIG_REVISION 3 15 #define PCIE_RP_PREMEM_CONFIG_REVISION 1 16 17 extern EFI_GUID gPcieRpConfigGuid; 18 extern EFI_GUID gPcieRpPreMemConfigGuid; 19 20 #pragma pack (push,1) 21 22 #define PCH_PCIE_SWEQ_COEFFS_MAX 5 23 24 typedef enum { 25 PchPcieOverrideDisabled = 0, 26 PchPcieL1L2Override = 0x01, 27 PchPcieL1SubstatesOverride = 0x02, 28 PchPcieL1L2AndL1SubstatesOverride = 0x03, 29 PchPcieLtrOverride = 0x04 30 } PCH_PCIE_OVERRIDE_CONFIG; 31 32 /** 33 PCIe device table entry entry 34 35 The PCIe device table is being used to override PCIe device ASPM settings. 36 To take effect table consisting of such entries must be instelled as PPI 37 on gPchPcieDeviceTablePpiGuid. 38 Last entry VendorId must be 0. 39 **/ 40 typedef struct { 41 UINT16 VendorId; ///< The vendor Id of Pci Express card ASPM setting override, 0xFFFF means any Vendor ID 42 UINT16 DeviceId; ///< The Device Id of Pci Express card ASPM setting override, 0xFFFF means any Device ID 43 UINT8 RevId; ///< The Rev Id of Pci Express card ASPM setting override, 0xFF means all steppings 44 UINT8 BaseClassCode; ///< The Base Class Code of Pci Express card ASPM setting override, 0xFF means all base class 45 UINT8 SubClassCode; ///< The Sub Class Code of Pci Express card ASPM setting override, 0xFF means all sub class 46 UINT8 EndPointAspm; ///< Override device ASPM (see: PCH_PCIE_ASPM_CONTROL) 47 ///< Bit 1 must be set in OverrideConfig for this field to take effect 48 UINT16 OverrideConfig; ///< The override config bitmap (see: PCH_PCIE_OVERRIDE_CONFIG). 49 /** 50 The L1Substates Capability Offset Override. (applicable if bit 2 is set in OverrideConfig) 51 This field can be zero if only the L1 Substate value is going to be override. 52 **/ 53 UINT16 L1SubstatesCapOffset; 54 /** 55 L1 Substate Capability Mask. (applicable if bit 2 is set in OverrideConfig) 56 Set to zero then the L1 Substate Capability [3:0] is ignored, and only L1s values are override. 57 Only bit [3:0] are applicable. Other bits are ignored. 58 **/ 59 UINT8 L1SubstatesCapMask; 60 /** 61 L1 Substate Port Common Mode Restore Time Override. (applicable if bit 2 is set in OverrideConfig) 62 L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue. 63 If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored, 64 and only L1SubstatesCapOffset is override. 65 **/ 66 UINT8 L1sCommonModeRestoreTime; 67 /** 68 L1 Substate Port Tpower_on Scale Override. (applicable if bit 2 is set in OverrideConfig) 69 L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue. 70 If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored, 71 and only L1SubstatesCapOffset is override. 72 **/ 73 UINT8 L1sTpowerOnScale; 74 /** 75 L1 Substate Port Tpower_on Value Override. (applicable if bit 2 is set in OverrideConfig) 76 L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue. 77 If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored, 78 and only L1SubstatesCapOffset is override. 79 **/ 80 UINT8 L1sTpowerOnValue; 81 82 /** 83 SnoopLatency bit definition 84 Note: All Reserved bits must be set to 0 85 86 BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid 87 When clear values in bits 9:0 will be ignored 88 BITS[14:13] - Reserved 89 BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits 90 000b - 1 ns 91 001b - 32 ns 92 010b - 1024 ns 93 011b - 32,768 ns 94 100b - 1,048,576 ns 95 101b - 33,554,432 ns 96 110b - Reserved 97 111b - Reserved 98 BITS[9:0] - Snoop Latency Value. The value in these bits will be multiplied with 99 the scale in bits 12:10 100 101 This field takes effect only if bit 3 is set in OverrideConfig. 102 **/ 103 UINT16 SnoopLatency; 104 /** 105 NonSnoopLatency bit definition 106 Note: All Reserved bits must be set to 0 107 108 BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid 109 When clear values in bits 9:0 will be ignored 110 BITS[14:13] - Reserved 111 BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits 112 000b - 1 ns 113 001b - 32 ns 114 010b - 1024 ns 115 011b - 32,768 ns 116 100b - 1,048,576 ns 117 101b - 33,554,432 ns 118 110b - Reserved 119 111b - Reserved 120 BITS[9:0] - Non Snoop Latency Value. The value in these bits will be multiplied with 121 the scale in bits 12:10 122 123 This field takes effect only if bit 3 is set in OverrideConfig. 124 **/ 125 UINT16 NonSnoopLatency; 126 127 /** 128 Forces LTR override to be permanent 129 The default way LTR override works is: 130 rootport uses LTR override values provided by BIOS until connected device sends an LTR message, then it will use values from the message 131 This settings allows force override of LTR mechanism. If it's enabled, then: 132 rootport will use LTR override values provided by BIOS forever; LTR messages sent from connected device will be ignored 133 **/ 134 UINT8 ForceLtrOverride; 135 UINT8 Reserved[3]; 136 } PCH_PCIE_DEVICE_OVERRIDE; 137 138 enum PCH_PCIE_SPEED { 139 PchPcieAuto, 140 PchPcieGen1, 141 PchPcieGen2, 142 PchPcieGen3 143 }; 144 145 /// 146 /// The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature 147 /// 148 typedef enum { 149 PchPcieAspmDisabled, 150 PchPcieAspmL0s, 151 PchPcieAspmL1, 152 PchPcieAspmL0sL1, 153 PchPcieAspmAutoConfig, 154 PchPcieAspmMax 155 } PCH_PCIE_ASPM_CONTROL; 156 157 /** 158 Refer to PCH EDS for the PCH implementation values corresponding 159 to below PCI-E spec defined ranges 160 **/ 161 typedef enum { 162 PchPcieL1SubstatesDisabled, 163 PchPcieL1SubstatesL1_1, 164 PchPcieL1SubstatesL1_1_2, 165 PchPcieL1SubstatesMax 166 } PCH_PCIE_L1SUBSTATES_CONTROL; 167 168 enum PCH_PCIE_MAX_PAYLOAD { 169 PchPcieMaxPayload128 = 0, 170 PchPcieMaxPayload256, 171 PchPcieMaxPayloadMax 172 }; 173 174 enum PCH_PCIE_COMPLETION_TIMEOUT { 175 PchPcieCompletionTO_Default, 176 PchPcieCompletionTO_50_100us, 177 PchPcieCompletionTO_1_10ms, 178 PchPcieCompletionTO_16_55ms, 179 PchPcieCompletionTO_65_210ms, 180 PchPcieCompletionTO_260_900ms, 181 PchPcieCompletionTO_1_3P5s, 182 PchPcieCompletionTO_4_13s, 183 PchPcieCompletionTO_17_64s, 184 PchPcieCompletionTO_Disabled 185 }; 186 187 typedef enum { 188 PchPcieEqDefault = 0, ///< @deprecated since revision 3. Behaves as PchPcieEqHardware. 189 PchPcieEqHardware = 1, ///< Hardware equalization 190 PchPcieEqStaticCoeff = 4 ///< Fixed equalization (requires Coefficient settings per lane) 191 } PCH_PCIE_EQ_METHOD; 192 193 /** 194 Represent lane specific PCIe Gen3 equalization parameters. 195 **/ 196 typedef struct { 197 UINT8 Cm; ///< Coefficient C-1 198 UINT8 Cp; ///< Coefficient C+1 199 UINT8 Rsvd0[2]; ///< Reserved bytes 200 } PCH_PCIE_EQ_LANE_PARAM, PCH_PCIE_EQ_PARAM; 201 202 203 /** 204 PCH_PCIE_CLOCK describes PCIe source clock generated by PCH. 205 **/ 206 typedef struct { 207 UINT8 Usage; ///< Purpose of given clock (see PCH_PCIE_CLOCK_USAGE). Default: Unused, 0xFF 208 UINT8 ClkReq; ///< ClkSrc - ClkReq mapping. Default: 1:1 mapping with Clock numbers 209 UINT8 RsvdBytes[2]; ///< Reserved byte 210 } PCH_PCIE_CLOCK; 211 212 /** 213 The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and capability of each PCH PCIe root port. 214 **/ 215 typedef struct { 216 UINT32 HotPlug : 1; ///< Indicate whether the root port is hot plug available. <b>0: Disable</b>; 1: Enable. 217 UINT32 PmSci : 1; ///< Indicate whether the root port power manager SCI is enabled. 0: Disable; <b>1: Enable</b>. 218 UINT32 ExtSync : 1; ///< Indicate whether the extended synch is enabled. <b>0: Disable</b>; 1: Enable. 219 UINT32 TransmitterHalfSwing : 1; ///< Indicate whether the Transmitter Half Swing is enabled. <b>0: Disable</b>; 1: Enable. 220 UINT32 AcsEnabled : 1; ///< Indicate whether the ACS is enabled. 0: Disable; <b>1: Enable</b>. 221 UINT32 RsvdBits0 : 11; ///< Reserved bits. 222 /** 223 Probe CLKREQ# signal before enabling CLKREQ# based power management. 224 Conforming device shall hold CLKREQ# low until CPM is enabled. This feature attempts 225 to verify CLKREQ# signal is connected by testing pad state before enabling CPM. 226 In particular this helps to avoid issues with open-ended PCIe slots. 227 This is only applicable to non hot-plug ports. 228 <b>0: Disable</b>; 1: Enable. 229 **/ 230 UINT32 ClkReqDetect : 1; 231 // 232 // Error handlings 233 // 234 UINT32 AdvancedErrorReporting : 1; ///< Indicate whether the Advanced Error Reporting is enabled. <b>0: Disable</b>; 1: Enable. 235 UINT32 UnsupportedRequestReport : 1; ///< Indicate whether the Unsupported Request Report is enabled. <b>0: Disable</b>; 1: Enable. 236 UINT32 FatalErrorReport : 1; ///< Indicate whether the Fatal Error Report is enabled. <b>0: Disable</b>; 1: Enable. 237 UINT32 NoFatalErrorReport : 1; ///< Indicate whether the No Fatal Error Report is enabled. <b>0: Disable</b>; 1: Enable. 238 UINT32 CorrectableErrorReport : 1; ///< Indicate whether the Correctable Error Report is enabled. <b>0: Disable</b>; 1: Enable. 239 UINT32 SystemErrorOnFatalError : 1; ///< Indicate whether the System Error on Fatal Error is enabled. <b>0: Disable</b>; 1: Enable. 240 UINT32 SystemErrorOnNonFatalError : 1; ///< Indicate whether the System Error on Non Fatal Error is enabled. <b>0: Disable</b>; 1: Enable. 241 UINT32 SystemErrorOnCorrectableError : 1; ///< Indicate whether the System Error on Correctable Error is enabled. <b>0: Disable</b>; 1: Enable. 242 /** 243 Max Payload Size supported, Default <b>128B</b>, see enum PCH_PCIE_MAX_PAYLOAD 244 Changes Max Payload Size Supported field in Device Capabilities of the root port. 245 **/ 246 UINT32 MaxPayload : 2; 247 UINT32 RsvdBits1 : 1; ///< Reserved fields for future expansion w/o protocol change 248 UINT32 DpcEnabled : 1; ///< Downstream Port Containment. 0: Disable; <b>1: Enable</b> 249 UINT32 RpDpcExtensionsEnabled : 1; ///< RP Extensions for Downstream Port Containment. 0: Disable; <b>1: Enable</b> 250 /** 251 Indicates how this root port is connected to endpoint. 0: built-in device; <b>1: slot</b> 252 Built-in is incompatible with hotplug-capable ports. 253 **/ 254 UINT32 SlotImplemented : 1; 255 UINT32 RsvdBits3 : 1; ///< Placeholder for deleted field 256 /** 257 Determines each PCIE Port speed capability. 258 <b>0: Auto</b>; 1: Gen1; 2: Gen2; 3: Gen3 (see: PCH_PCIE_SPEED) 259 **/ 260 UINT8 PcieSpeed; 261 /** 262 PCIe Gen3 Equalization Phase 3 Method (see PCH_PCIE_EQ_METHOD). 263 0: DEPRECATED, hardware equalization; <b>1: hardware equalization</b>; 4: Fixed Coefficients 264 **/ 265 UINT8 Gen3EqPh3Method; 266 267 UINT8 PhysicalSlotNumber; ///< Indicates the slot number for the root port. Default is the value as root port index. 268 UINT8 CompletionTimeout; ///< The completion timeout configuration of the root port (see: PCH_PCIE_COMPLETION_TIMEOUT). Default is <b>PchPcieCompletionTO_Default</b>. 269 /** 270 The PCH pin assigned to device PERST# signal if available, zero otherwise. 271 This entry is used mainly in Gen3 software equalization flow. It is necessary for some devices 272 (mainly some graphic adapters) to successfully complete the software equalization flow. 273 See also DeviceResetPadActiveHigh 274 **/ 275 UINT32 RsvdBytes0[2]; ///< Reserved bytes 276 // 277 // Power Management 278 // 279 UINT8 Aspm; ///< The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is <b>PchPcieAspmAutoConfig</b> for CNP-LP B1 it is limited to <b>PchPcieAspmL1</b>. 280 UINT8 L1Substates; ///< The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). Default is <b>PchPcieL1SubstatesL1_1_2</b>. 281 UINT8 LtrEnable; ///< Latency Tolerance Reporting Mechanism. <b>0: Disable</b>; 1: Enable. 282 UINT8 LtrConfigLock; ///< <b>0: Disable</b>; 1: Enable. 283 UINT16 LtrMaxSnoopLatency; ///< <b>(Test)</b> Latency Tolerance Reporting, Max Snoop Latency. 284 UINT16 LtrMaxNoSnoopLatency; ///< <b>(Test)</b> Latency Tolerance Reporting, Max Non-Snoop Latency. 285 UINT8 SnoopLatencyOverrideMode; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Mode. 286 UINT8 SnoopLatencyOverrideMultiplier; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Multiplier. 287 UINT16 SnoopLatencyOverrideValue; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Value. 288 UINT8 NonSnoopLatencyOverrideMode; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Mode. 289 UINT8 NonSnoopLatencyOverrideMultiplier; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. 290 UINT16 NonSnoopLatencyOverrideValue; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Value. 291 UINT32 SlotPowerLimitScale : 2; ///< <b>(Test)</b> Specifies scale used for slot power limit value. Leave as 0 to set to default. Default is <b>zero</b>. 292 UINT32 SlotPowerLimitValue : 12; ///< <b>(Test)</b> Specifies upper limit on power supplies by slot. Leave as 0 to set to default. Default is <b>zero</b>. 293 // 294 // Gen3 Equalization settings 295 // 296 UINT32 Uptp : 4; ///< <b>(Test)</b> Upstream Port Transmitter Preset used during Gen3 Link Equalization. Used for all lanes. Default is <b>5</b>. 297 UINT32 Dptp : 4; ///< <b>(Test)</b> Downstream Port Transmiter Preset used during Gen3 Link Equalization. Used for all lanes. Default is <b>7</b>. 298 /** 299 <b>(Test)</b> 300 Forces LTR override to be permanent 301 The default way LTR override works is: 302 rootport uses LTR override values provided by BIOS until connected device sends an LTR message, then it will use values from the message 303 This settings allows force override of LTR mechanism. If it's enabled, then: 304 rootport will use LTR override values provided by BIOS forever; LTR messages sent from connected device will be ignored 305 **/ 306 UINT32 ForceLtrOverride : 1; 307 UINT32 EnableCpm : 1; ///< Enables Clock Power Management; even if disabled, CLKREQ# signal can still be controlled by L1 PM substates mechanism 308 UINT32 PtmEnabled : 1; ///< Enables PTM capability 309 UINT32 PcieRootPortGen2PllL1CgDisable : 1; ///< Disables Gen2PLL shutdown and L1 state controller power gating 310 UINT32 RsvdBits2 : 6; ///< Reserved Bits 311 /** 312 The number of milliseconds reference code will wait for link to exit Detect state for enabled ports 313 before assuming there is no device and potentially disabling the port. 314 It's assumed that the link will exit detect state before root port initialization (sufficient time 315 elapsed since PLTRST de-assertion) therefore default timeout is zero. However this might be useful 316 if device power-up seqence is controlled by BIOS or a specific device requires more time to detect. 317 In case of non-common clock enabled the default timout is 15ms. 318 <b>Default: 0</b> 319 **/ 320 UINT16 DetectTimeoutMs; 321 UINT16 RsvdBytes1[3]; ///< Reserved bytes 322 } PCH_PCIE_ROOT_PORT_CONFIG; 323 324 /** 325 The PCH_PCIE_CONFIG block describes the expected configuration of the PCH PCI Express controllers 326 327 <b>Revision 1</b>: 328 - Init version 329 <b>Revision 2</b>: 330 - Add policy PcieRootPortGen2PllL1CgDisable in PCH_PCIE_ROOT_PORT_CONFIG. 331 <b>Revision 3</b>: 332 - Deleted all items related to PCIe Gen3 software equalization: 333 DeviceResetPad, DeviceResetPadActiveHigh policies and two values from PCH_PCIE_EQ_METHOD enum used for Gen3EqPh3Method field 334 **/ 335 typedef struct { 336 CONFIG_BLOCK_HEADER Header; ///< Config Block Header 337 /// 338 /// These members describe the configuration of each PCH PCIe root port. 339 /// 340 PCH_PCIE_ROOT_PORT_CONFIG RootPort[PCH_MAX_PCIE_ROOT_PORTS]; 341 /// 342 /// Configuration of PCIe source clocks 343 /// 344 PCH_PCIE_CLOCK PcieClock[PCH_MAX_PCIE_CLOCKS]; 345 /// 346 /// Gen3 Equalization settings for physical PCIe lane, index 0 represents PCIe lane 1, etc. 347 /// Corresponding entries are used when root port EqPh3Method is PchPcieEqStaticCoeff (default). 348 /// 349 PCH_PCIE_EQ_LANE_PARAM EqPh3LaneParam[PCH_MAX_PCIE_ROOT_PORTS]; 350 /// 351 /// List of coefficients used during equalization (applicable to both software and hardware EQ) 352 /// 353 PCH_PCIE_EQ_PARAM SwEqCoeffList[PCH_PCIE_SWEQ_COEFFS_MAX]; 354 PCH_PCIE_EQ_PARAM Rsvd0[3]; 355 /// 356 /// <b>(Test)</b> This member describes whether PCIE root port Port 8xh Decode is enabled. <b>0: Disable</b>; 1: Enable. 357 /// 358 UINT32 EnablePort8xhDecode : 1; 359 /// 360 /// <b>(Test)</b> The Index of PCIe Port that is selected for Port8xh Decode (0 Based) 361 /// 362 UINT32 PchPciePort8xhDecodePortIndex : 5; 363 /// 364 /// This member describes whether the PCI Express Clock Gating for each root port 365 /// is enabled by platform modules. <b>0: Disable</b>; 1: Enable. 366 /// 367 UINT32 DisableRootPortClockGating : 1; 368 /// 369 /// This member describes whether Peer Memory Writes are enabled on the platform. <b>0: Disable</b>; 1: Enable. 370 /// 371 UINT32 EnablePeerMemoryWrite : 1; 372 /** 373 Compliance Test Mode shall be enabled when using Compliance Load Board. 374 <b>0: Disable</b>, 1: Enable 375 **/ 376 UINT32 ComplianceTestMode : 1; 377 /** 378 RpFunctionSwap allows BIOS to use root port function number swapping when root port of function 0 is disabled. 379 A PCIE device can have higher functions only when Function0 exists. To satisfy this requirement, 380 BIOS will always enable Function0 of a device that contains more than 0 enabled root ports. 381 - <b>Enabled: One of enabled root ports get assigned to Function0.</b> 382 This offers no guarantee that any particular root port will be available at a specific DevNr:FuncNr location 383 - Disabled: Root port that corresponds to Function0 will be kept visible even though it might be not used. 384 That way rootport - to - DevNr:FuncNr assignment is constant. This option will impact ports 1, 9, 17. 385 NOTE: This option will not work if ports 1, 9, 17 are fused or configured for RST PCIe storage or disabled through policy 386 In other words, it only affects ports that would become hidden because they have no device connected. 387 NOTE: Disabling function swap may have adverse impact on power management. This option should ONLY 388 be used when each one of root ports 1, 9, 17: 389 - is configured as PCIe and has correctly configured ClkReq signal, or 390 - does not own any mPhy lanes (they are configured as SATA or USB) 391 **/ 392 UINT32 RpFunctionSwap : 1; 393 394 UINT32 RsvdBits0 : 22; 395 /** 396 PCIe device override table 397 The PCIe device table is being used to override PCIe device ASPM settings. 398 This is a pointer points to a 32bit address. And it's only used in PostMem phase. 399 Please refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. 400 Last entry VendorId must be 0. 401 The prototype of this policy is: 402 PCH_PCIE_DEVICE_OVERRIDE *PcieDeviceOverrideTablePtr; 403 **/ 404 UINT32 PcieDeviceOverrideTablePtr; 405 406 } PCH_PCIE_CONFIG; 407 408 /** 409 The PCH_PCIE_RP_PREMEM_CONFIG block describes early configuration of the PCH PCI Express controllers 410 <b>Revision 1</b>: 411 - Init version 412 - Add RpEnable in premem phase. 413 **/ 414 typedef struct { 415 CONFIG_BLOCK_HEADER Header; ///< Config Block Header 416 /** 417 Root Port enabling mask. 418 Bit0 presents RP1, Bit1 presents RP2, and so on. 419 0: Disable; <b>1: Enable</b>. 420 **/ 421 UINT32 RpEnabledMask; 422 UINT16 PcieImrSize; ///< PCIe IMR size in megabytes 423 UINT8 PcieImrEnabled; ///< PCIe IMR. <b>0: Disable</b>; 1: Enable. 424 UINT8 ImrRpSelection; ///< Index of PCIe root port that is selected for IMR (0 based) 425 } PCH_PCIE_RP_PREMEM_CONFIG; 426 427 #pragma pack (pop) 428 429 #endif // _PCH_PCIE_CONFIG_H_ 430