1/**@file 2 3Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> 4SPDX-License-Identifier: BSD-2-Clause-Patent 5 6**/ 7 8 // 9 // Define SA NVS Area operatino region. 10 // 11 12 13 14 OperationRegion(SANV,SystemMemory, 0xFFFF0000,0xAA55) 15 Field(SANV,AnyAcc,Lock,Preserve) 16 { 17 Offset(0), ASLB, 32, // Offset(0), IGD OpRegion base address 18 Offset(4), IMON, 8, // Offset(4), IMON Current Value 19 Offset(5), IGDS, 8, // Offset(5), IGD State (Primary Display = 1) 20 Offset(6), IBTT, 8, // Offset(6), IGD Boot Display Device 21 Offset(7), IPAT, 8, // Offset(7), IGD Panel Type CMOS option 22 Offset(8), IPSC, 8, // Offset(8), IGD Panel Scaling 23 Offset(9), IBIA, 8, // Offset(9), IGD BIA Configuration 24 Offset(10), ISSC, 8, // Offset(10), IGD SSC Configuration 25 Offset(11), IDMS, 8, // Offset(11), IGD DVMT Memory Size 26 Offset(12), IF1E, 8, // Offset(12), IGD Function 1 Enable 27 Offset(13), HVCO, 8, // Offset(13), HPLL VCO 28 Offset(14), GSMI, 8, // Offset(14), GMCH SMI/SCI mode (0=SCI) 29 Offset(15), PAVP, 8, // Offset(15), IGD PAVP data 30 Offset(16), CADL, 8, // Offset(16), Current Attached Device List 31 Offset(17), CSTE, 16, // Offset(17), Current Display State 32 Offset(19), NSTE, 16, // Offset(19), Next Display State 33 Offset(21), NDID, 8, // Offset(21), Number of Valid Device IDs 34 Offset(22), DID1, 32, // Offset(22), Device ID 1 35 Offset(26), DID2, 32, // Offset(26), Device ID 2 36 Offset(30), DID3, 32, // Offset(30), Device ID 3 37 Offset(34), DID4, 32, // Offset(34), Device ID 4 38 Offset(38), DID5, 32, // Offset(38), Device ID 5 39 Offset(42), DID6, 32, // Offset(42), Device ID 6 40 Offset(46), DID7, 32, // Offset(46), Device ID 7 41 Offset(50), DID8, 32, // Offset(50), Device ID 8 42 Offset(54), DID9, 32, // Offset(54), Device ID 9 43 Offset(58), DIDA, 32, // Offset(58), Device ID 10 44 Offset(62), DIDB, 32, // Offset(62), Device ID 11 45 Offset(66), DIDC, 32, // Offset(66), Device ID 12 46 Offset(70), DIDD, 32, // Offset(70), Device ID 13 47 Offset(74), DIDE, 32, // Offset(74), Device ID 14 48 Offset(78), DIDF, 32, // Offset(78), Device ID 15 49 Offset(82), DIDX, 32, // Offset(82), Device ID for eDP device 50 Offset(86), NXD1, 32, // Offset(86), Next state DID1 for _DGS 51 Offset(90), NXD2, 32, // Offset(90), Next state DID2 for _DGS 52 Offset(94), NXD3, 32, // Offset(94), Next state DID3 for _DGS 53 Offset(98), NXD4, 32, // Offset(98), Next state DID4 for _DGS 54 Offset(102), NXD5, 32, // Offset(102), Next state DID5 for _DGS 55 Offset(106), NXD6, 32, // Offset(106), Next state DID6 for _DGS 56 Offset(110), NXD7, 32, // Offset(110), Next state DID7 for _DGS 57 Offset(114), NXD8, 32, // Offset(114), Next state DID8 for _DGS 58 Offset(118), NXDX, 32, // Offset(118), Next state DID for eDP 59 Offset(122), LIDS, 8, // Offset(122), Lid State (Lid Open = 1) 60 Offset(123), KSV0, 32, // Offset(123), First four bytes of AKSV (manufacturing mode) 61 Offset(127), KSV1, 8, // Offset(127), Fifth byte of AKSV (manufacturing mode) 62 Offset(128), BRTL, 8, // Offset(128), Brightness Level Percentage 63 Offset(129), ALSE, 8, // Offset(129), Ambient Light Sensor Enable 64 Offset(130), ALAF, 8, // Offset(130), Ambient Light Adjusment Factor 65 Offset(131), LLOW, 8, // Offset(131), LUX Low Value 66 Offset(132), LHIH, 8, // Offset(132), LUX High Value 67 Offset(133), ALFP, 8, // Offset(133), Active LFP 68 Offset(134), IMTP, 8, // Offset(134), IMGU ACPI device type 69 Offset(135), EDPV, 8, // Offset(135), Check for eDP display device 70 Offset(136), SGMD, 8, // Offset(136), SG Mode (0=Disabled, 1=SG Muxed, 2=SG Muxless, 3=DGPU Only) 71 Offset(137), SGFL, 8, // Offset(137), SG Feature List 72 Offset(138), SGGP, 8, // Offset(138), PCIe0 GPIO Support (0=Disabled, 1=PCH Based, 2=I2C Based) 73 Offset(139), HRE0, 8, // Offset(139), PCIe0 HLD RST IO Expander Number 74 Offset(140), HRG0, 32, // Offset(140), PCIe0 HLD RST GPIO Number 75 Offset(144), HRA0, 8, // Offset(144), PCIe0 HLD RST GPIO Active Information 76 Offset(145), PWE0, 8, // Offset(145), PCIe0 PWR Enable IO Expander Number 77 Offset(146), PWG0, 32, // Offset(146), PCIe0 PWR Enable GPIO Number 78 Offset(150), PWA0, 8, // Offset(150), PCIe0 PWR Enable GPIO Active Information 79 Offset(151), P1GP, 8, // Offset(151), PCIe1 GPIO Support (0=Disabled, 1=PCH Based, 2=I2C Based) 80 Offset(152), HRE1, 8, // Offset(152), PCIe1 HLD RST IO Expander Number 81 Offset(153), HRG1, 32, // Offset(153), PCIe1 HLD RST GPIO Number 82 Offset(157), HRA1, 8, // Offset(157), PCIe1 HLD RST GPIO Active Information 83 Offset(158), PWE1, 8, // Offset(158), PCIe1 PWR Enable IO Expander Number 84 Offset(159), PWG1, 32, // Offset(159), PCIe1 PWR Enable GPIO Number 85 Offset(163), PWA1, 8, // Offset(163), PCIe1 PWR Enable GPIO Active Information 86 Offset(164), P2GP, 8, // Offset(164), PCIe2 GPIO Support (0=Disabled, 1=PCH Based, 2=I2C Based) 87 Offset(165), HRE2, 8, // Offset(165), PCIe2 HLD RST IO Expander Number 88 Offset(166), HRG2, 32, // Offset(166), PCIe2 HLD RST GPIO Number 89 Offset(170), HRA2, 8, // Offset(170), PCIe2 HLD RST GPIO Active Information 90 Offset(171), PWE2, 8, // Offset(171), PCIe2 PWR Enable IO Expander Number 91 Offset(172), PWG2, 32, // Offset(172), PCIe2 PWR Enable GPIO Number 92 Offset(176), PWA2, 8, // Offset(176), PCIe2 PWR Enable GPIO Active Information 93 Offset(177), DLPW, 16, // Offset(177), Delay after power enable for PCIe 94 Offset(179), DLHR, 16, // Offset(179), Delay after Hold Reset for PCIe 95 Offset(181), EECP, 8, // Offset(181), PCIe0 Endpoint Capability Structure Offset 96 Offset(182), XBAS, 32, // Offset(182), Any Device's PCIe Config Space Base Address 97 Offset(186), GBAS, 16, // Offset(186), GPIO Base Address 98 Offset(188), NVGA, 32, // Offset(188), NVIG opregion address 99 Offset(192), NVHA, 32, // Offset(192), NVHM opregion address 100 Offset(196), AMDA, 32, // Offset(196), AMDA opregion address 101 Offset(200), LTRX, 8, // Offset(200), Latency Tolerance Reporting Enable 102 Offset(201), OBFX, 8, // Offset(201), Optimized Buffer Flush and Fill 103 Offset(202), LTRY, 8, // Offset(202), Latency Tolerance Reporting Enable 104 Offset(203), OBFY, 8, // Offset(203), Optimized Buffer Flush and Fill 105 Offset(204), LTRZ, 8, // Offset(204), Latency Tolerance Reporting Enable 106 Offset(205), OBFZ, 8, // Offset(205), Optimized Buffer Flush and Fill 107 Offset(206), SMSL, 16, // Offset(206), SA Peg Latency Tolerance Reporting Max Snoop Latency 108 Offset(208), SNSL, 16, // Offset(208), SA Peg Latency Tolerance Reporting Max No Snoop Latency 109 Offset(210), P0UB, 8, // Offset(210), Peg0 Unused Bundle Control 110 Offset(211), P1UB, 8, // Offset(211), Peg1 Unused Bundle Control 111 Offset(212), P2UB, 8, // Offset(212), Peg2 Unused Bundle Control 112 Offset(213), PCSL, 8, // Offset(213), The lowest C-state for the package 113 Offset(214), PBGE, 8, // Offset(214), Pegx Unused Bundle Control Global Enable (0=Disabled, 1=Enabled) 114 Offset(215), M64B, 64, // Offset(215), Base of above 4GB MMIO resource 115 Offset(223), M64L, 64, // Offset(223), Length of above 4GB MMIO resource 116 Offset(231), CPEX, 32, // Offset(231), CPU ID info to get Family Id or Stepping 117 Offset(235), EEC1, 8, // Offset(235), PCIe1 Endpoint Capability Structure Offset 118 Offset(236), EEC2, 8, // Offset(236), PCIe2 Endpoint Capability Structure Offset 119 Offset(237), SBN0, 8, // Offset(237), PCIe0 Secondary Bus Number (PCIe0 Endpoint Bus Number) 120 Offset(238), SBN1, 8, // Offset(238), PCIe1 Secondary Bus Number (PCIe0 Endpoint Bus Number) 121 Offset(239), SBN2, 8, // Offset(239), PCIe2 Secondary Bus Number (PCIe0 Endpoint Bus Number) 122 Offset(240), M32B, 32, // Offset(240), Base of below 4GB MMIO resource 123 Offset(244), M32L, 32, // Offset(244), Length of below 4GB MMIO resource 124 Offset(248), P0WK, 32, // Offset(248), PCIe0 RTD3 Device Wake GPIO Number 125 Offset(252), P1WK, 32, // Offset(252), PCIe1 RTD3 Device Wake GPIO Number 126 Offset(256), P2WK, 32, // Offset(256), PCIe2 RTD3 Device Wake GPIO Number 127 Offset (500), // Offset(260) : Offset(499), Reserved bytes 128 Offset (503), // Offset(500) : Offset(502), Reserved bytes 129 } 130