1 /** 2 **/ 3 /** 4 5 Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved 6 7 SPDX-License-Identifier: BSD-2-Clause-Patent 8 9 10 11 @file 12 PchPlatformPolicy.h 13 14 @brief 15 PCH policy protocol produced by a platform driver specifying various 16 expected PCH settings. This protocol is consumed by the PCH drivers. 17 18 **/ 19 #ifndef _PCH_PLATFORM_POLICY_H_ 20 #define _PCH_PLATFORM_POLICY_H_ 21 22 23 // 24 #include "PchRegs.h" 25 #ifndef ECP_FLAG 26 #include "Uefi.h" 27 #endif 28 29 #define DXE_PCH_PLATFORM_POLICY_PROTOCOL_GUID \ 30 { \ 31 0x4b0165a9, 0x61d6, 0x4e23, 0xa0, 0xb5, 0x3e, 0xc7, 0x9c, 0x2e, 0x30, 0xd5 \ 32 } 33 extern EFI_GUID gDxePchPlatformPolicyProtocolGuid; 34 35 /// 36 /// Forward reference for ANSI C compatibility 37 /// 38 typedef struct _DXE_PCH_PLATFORM_POLICY_PROTOCOL DXE_PCH_PLATFORM_POLICY_PROTOCOL; 39 40 /// 41 /// Protocol revision number 42 /// Any backwards compatible changes to this protocol will result in an update in the revision number 43 /// Major changes will require publication of a new protocol 44 /// 45 /// Revision 1: Original version 46 /// 47 #define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_1 1 48 #define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_2 2 49 #define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_3 3 50 #define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_4 4 51 #define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_5 5 52 #define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_6 6 53 #define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_7 7 54 #define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_8 8 55 #define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_9 9 56 #define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_10 10 57 #define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_11 11 58 #define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_12 12 59 60 /// 61 /// Generic definitions for device enabling/disabling used by PCH code. 62 /// 63 #define PCH_DEVICE_ENABLE 1 64 #define PCH_DEVICE_DISABLE 0 65 66 /// 67 /// ---------------------------- Device Enabling ------------------------------ 68 /// 69 /// PCH Device enablings 70 /// 71 typedef struct { 72 UINT8 Lan : 1; /// 0: Disable; 1: Enable 73 UINT8 Azalia : 2; /// 0: Disable; 1: Enable; 2: Auto 74 UINT8 Sata : 1; /// 0: Disable; 1: Enable 75 UINT8 Smbus : 1; /// 0: Disable; 1: Enable 76 UINT8 LpeEnabled : 2; /// 0: Disabled; 1: PCI Mode 2: ACPI Mode 77 UINT8 Reserved[1]; /// Reserved fields for future expansion w/o protocol change 78 } PCH_DEVICE_ENABLING; 79 80 /// 81 /// ---------------------------- USB Config ----------------------------- 82 /// 83 /// 84 /// Overcurrent pins 85 /// 86 typedef enum { 87 PchUsbOverCurrentPin0 = 0, 88 PchUsbOverCurrentPin1, 89 PchUsbOverCurrentPin2, 90 PchUsbOverCurrentPin3, 91 PchUsbOverCurrentPin4, 92 PchUsbOverCurrentPin5, 93 PchUsbOverCurrentPin6, 94 PchUsbOverCurrentPin7, 95 PchUsbOverCurrentPinSkip, 96 PchUsbOverCurrentPinMax 97 } PCH_USB_OVERCURRENT_PIN; 98 99 typedef struct { 100 UINT8 Enable : 1; /// 0: Disable; 1: Enable. This would take effect while UsbPerPortCtl is enabled 101 UINT8 Panel : 1; /// 0: Back Panel Port; 1: Front Panel Port. 102 UINT8 Dock : 1; /// 0: Not docking port; 1: Docking Port. 103 UINT8 Rsvdbits : 5; 104 } PCH_USB_PORT_SETTINGS; 105 106 typedef struct { 107 UINT8 Enable : 1; /// 0: Disable; 1: Enable 108 UINT8 Rsvdbits : 7; 109 } PCH_USB20_CONTROLLER_SETTINGS; 110 111 typedef struct { 112 UINT8 Enable : 2; /// 0: 0: Disabled; 1: PCI Mode 2: ACPI Mode 113 UINT8 Rsvdbits : 6; 114 } PCH_USBOTG_CONTROLLER_SETTINGS; 115 116 #define PCH_XHCI_MODE_OFF 0 117 #define PCH_XHCI_MODE_ON 1 118 #define PCH_XHCI_MODE_AUTO 2 119 #define PCH_XHCI_MODE_SMARTAUTO 3 120 121 #define PCH_EHCI_DEBUG_OFF 0 122 #define PCH_EHCI_DEBUG_ON 1 123 124 #define PCH_USB_FRONT_PANEL 1 125 #define PCH_USB_BACK_PANEL 0 126 127 typedef struct { 128 UINT8 Mode : 2; /// 0: Disable; 1: Enable, 2: Auto, 3: Smart Auto 129 UINT8 PreBootSupport : 1; /// 0: No xHCI driver available; 1: xHCI driver available 130 UINT8 XhciStreams : 1; /// 0: Disable; 1: Enable 131 UINT8 Rsvdbits : 4; 132 } PCH_USB30_CONTROLLER_SETTINGS; 133 134 typedef struct { 135 UINT8 UsbPerPortCtl : 1; /// 0: Disable; 1: Enable Per-port enable control 136 UINT8 Ehci1Usbr : 1; /// 0: Disable; 1: Enable EHCI 1 USBR 137 UINT8 RsvdBits : 6; 138 PCH_USB_PORT_SETTINGS PortSettings[PCH_USB_MAX_PHYSICAL_PORTS]; 139 PCH_USB20_CONTROLLER_SETTINGS Usb20Settings[PchEhciControllerMax]; 140 PCH_USB30_CONTROLLER_SETTINGS Usb30Settings; 141 PCH_USBOTG_CONTROLLER_SETTINGS UsbOtgSettings; 142 PCH_USB_OVERCURRENT_PIN Usb20OverCurrentPins[PCH_USB_MAX_PHYSICAL_PORTS]; 143 PCH_USB_OVERCURRENT_PIN Usb30OverCurrentPins[PCH_XHCI_MAX_USB3_PORTS]; 144 /// 145 /// The length of Usb Port to configure the USB transmitter, 146 /// Bits [16:4] represents length of Usb Port in inches using octal format and [3:0] is for the decimal Point. 147 /// 148 UINT16 Usb20PortLength[PCH_EHCI_MAX_PORTS]; 149 UINT16 EhciDebug; 150 UINT16 UsbXhciLpmSupport; 151 152 } PCH_USB_CONFIG; 153 154 /// 155 /// ---------------------------- PCI Express Config ---------------------- 156 /// 157 /// The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature 158 /// 159 typedef enum { 160 PchPcieAspmDisabled, 161 PchPcieAspmL0s, 162 PchPcieAspmL1, 163 PchPcieAspmL0sL1, 164 PchPcieAspmAutoConfig, 165 PchPcieAspmMax 166 } PCH_PCI_EXPRESS_ASPM_CONTROL; 167 168 /// 169 /// Refer to PCH EDS for the PCH implementation values corresponding 170 /// to below PCI-E spec defined ranges 171 /// 172 typedef enum { 173 PchPciECompletionTO_Default, 174 PchPciECompletionTO_50_100us, 175 PchPciECompletionTO_1_10ms, 176 PchPciECompletionTO_16_55ms, 177 PchPciECompletionTO_65_210ms, 178 PchPciECompletionTO_260_900ms, 179 PchPciECompletionTO_1_3P5s, 180 PchPciECompletionTO_4_13s, 181 PchPciECompletionTO_17_64s, 182 PchPciECompletionTO_Disabled 183 } PCH_PCIE_COMPLETION_TIMEOUT; 184 185 typedef struct { 186 UINT8 Enable : 1; /// Root Port enabling, 0: Disable; 1: Enable. 187 UINT8 Hide : 1; /// Whether or not to hide the configuration space of this port 188 UINT8 SlotImplemented : 1; 189 UINT8 HotPlug : 1; 190 UINT8 PmSci : 1; 191 UINT8 ExtSync : 1; /// Extended Synch 192 UINT8 Rsvdbits : 2; 193 /// 194 /// Error handlings 195 /// 196 UINT8 UnsupportedRequestReport : 1; 197 UINT8 FatalErrorReport : 1; 198 UINT8 NoFatalErrorReport : 1; 199 UINT8 CorrectableErrorReport : 1; 200 UINT8 PmeInterrupt : 1; 201 UINT8 SystemErrorOnFatalError : 1; 202 UINT8 SystemErrorOnNonFatalError : 1; 203 UINT8 SystemErrorOnCorrectableError : 1; 204 205 UINT8 AdvancedErrorReporting : 1; 206 UINT8 TransmitterHalfSwing : 1; 207 UINT8 Reserved : 6; /// Reserved fields for future expansion w/o protocol change 208 209 UINT8 FunctionNumber; /// The function number this root port is mapped to. 210 UINT8 PhysicalSlotNumber; 211 PCH_PCIE_COMPLETION_TIMEOUT CompletionTimeout; 212 PCH_PCI_EXPRESS_ASPM_CONTROL Aspm; 213 } PCH_PCI_EXPRESS_ROOT_PORT_CONFIG; 214 215 typedef struct { 216 /** 217 VendorId 218 219 The vendor Id of Pci Express card ASPM setting override, 0xFFFF means any Vendor ID 220 221 DeviceId 222 223 The Device Id of Pci Express card ASPM setting override, 0xFFFF means any Device ID 224 225 RevId 226 227 The Rev Id of Pci Express card ASPM setting override, 0xFF means all steppings 228 229 BaseClassCode 230 231 The Base Class Code of Pci Express card ASPM setting override, 0xFF means all base class 232 233 SubClassCode 234 235 The Sub Class Code of Pci Express card ASPM setting override, 0xFF means all sub class 236 237 238 EndPointAspm 239 240 The override ASPM setting from End point 241 **/ 242 UINT16 VendorId; 243 UINT16 DeviceId; 244 UINT8 RevId; 245 UINT8 BaseClassCode; 246 UINT8 SubClassCode; 247 PCH_PCI_EXPRESS_ASPM_CONTROL EndPointAspm; 248 } PCH_PCIE_DEVICE_ASPM_OVERRIDE; 249 250 typedef struct { 251 UINT16 VendorId; ///< PCI configuration space offset 0 252 UINT16 DeviceId; ///< PCI configuration space offset 2 253 UINT8 RevId; ///< PCI configuration space offset 8; 0xFF means all steppings 254 /** 255 SnoopLatency bit definition 256 Note: All Reserved bits must be set to 0 257 258 BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid 259 When clear values in bits 9:0 will be ignored 260 BITS[14:13] - Reserved 261 BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits 262 000b - 1 ns 263 001b - 32 ns 264 010b - 1024 ns 265 011b - 32,768 ns 266 100b - 1,048,576 ns 267 101b - 33,554,432 ns 268 110b - Reserved 269 111b - Reserved 270 BITS[9:0] - Snoop Latency Value. The value in these bits will be multiplied with 271 the scale in bits 12:10 272 **/ 273 UINT16 SnoopLatency; 274 /** 275 NonSnoopLatency bit definition 276 Note: All Reserved bits must be set to 0 277 278 BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid 279 When clear values in bits 9:0 will be ignored 280 BITS[14:13] - Reserved 281 BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits 282 000b - 1 ns 283 001b - 32 ns 284 010b - 1024 ns 285 011b - 32,768 ns 286 100b - 1,048,576 ns 287 101b - 33,554,432 ns 288 110b - Reserved 289 111b - Reserved 290 BITS[9:0] - Non Snoop Latency Value. The value in these bits will be multiplied with 291 the scale in bits 12:10 292 **/ 293 UINT16 NonSnoopLatency; 294 } PCH_PCIE_DEVICE_LTR_OVERRIDE; 295 296 typedef struct { 297 /// 298 /// Temp Bus Number range available to be assigned to 299 /// each root port and its downstream devices for initialization 300 /// of these devices before PCI Bus enumeration 301 /// 302 UINT8 TempRootPortBusNumMin; 303 UINT8 TempRootPortBusNumMax; 304 PCH_PCI_EXPRESS_ROOT_PORT_CONFIG RootPort[PCH_PCIE_MAX_ROOT_PORTS]; 305 BOOLEAN RootPortClockGating; 306 UINT8 NumOfDevAspmOverride; /// Number of PCI Express card Aspm setting override 307 PCH_PCIE_DEVICE_ASPM_OVERRIDE *DevAspmOverride; /// The Pointer which is point to Pci Express card Aspm setting override 308 UINT8 PcieDynamicGating; /// Need PMC enable it first from PMC 0x3_12 MCU 318. 309 } PCH_PCI_EXPRESS_CONFIG; 310 311 312 /// 313 /// ---------------------------- SATA Config ----------------------------- 314 /// 315 typedef enum { 316 PchSataSpeedSupportGen1 = 1, 317 PchSataSpeedSupportGen2 318 } PCH_SATA_SPEED_SUPPORT; 319 320 typedef struct { 321 UINT8 Enable : 1; /// 0: Disable; 1: Enable 322 UINT8 HotPlug : 1; /// 0: Disable; 1: Enable 323 UINT8 MechSw : 1; /// 0: Disable; 1: Enable 324 UINT8 External : 1; /// 0: Disable; 1: Enable 325 UINT8 SpinUp : 1; /// 0: Disable; 1: Enable the COMRESET initialization Sequence to the device 326 UINT8 Rsvdbits : 3; /// Reserved fields for future expansion w/o protocol change 327 } PCH_SATA_PORT_SETTINGS; 328 329 typedef struct { 330 PCH_SATA_PORT_SETTINGS PortSettings[PCH_AHCI_MAX_PORTS]; 331 UINT8 RaidAlternateId : 1; /// 0: Disable; 1: Enable 332 UINT8 Raid0 : 1; /// 0: Disable; 1: Enable RAID0 333 UINT8 Raid1 : 1; /// 0: Disable; 1: Enable RAID1 334 UINT8 Raid10 : 1; /// 0: Disable; 1: Enable RAID10 335 UINT8 Raid5 : 1; /// 0: Disable; 1: Enable RAID5 336 UINT8 Irrt : 1; /// 0: Disable; 1: Enable Intel Rapid Recovery Technology 337 UINT8 OromUiBanner : 1; /// 0: Disable; 1: Enable OROM UI and BANNER 338 UINT8 HddUnlock : 1; /// 0: Disable; 1: Indicates that the HDD password unlock in the OS is enabled 339 340 UINT8 LedLocate : 1; /// 0: Disable; 1: Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS 341 UINT8 IrrtOnly : 1; /// 0: Disable; 1: Allow only IRRT drives to span internal and external ports 342 UINT8 TestMode : 1; /// 0: Disable; 1: Allow entrance to the PCH SATA test modes 343 UINT8 SalpSupport : 1; /// 0: Disable; 1: Enable Aggressive Link Power Management 344 UINT8 LegacyMode : 1; /// 0: Native PCI mode; 1: Legacy mode, when SATA controller is operating in IDE mode 345 UINT8 SpeedSupport : 4; /// Indicates the maximum speed the SATA controller can support 346 /// 1h: 1.5 Gb/s (Gen 1); 2h: 3 Gb/s(Gen 2) 347 348 UINT8 Rsvdbits : 7; // Reserved fields for future expansion w/o protocol change 349 } PCH_SATA_CONFIG; 350 /// 351 /// --------------------------- AZALIA Config ------------------------------ 352 /// 353 typedef struct { 354 UINT32 VendorDeviceId; 355 UINT16 SubSystemId; 356 UINT8 RevisionId; /// 0xFF applies to all steppings 357 UINT8 FrontPanelSupport; 358 UINT16 NumberOfRearJacks; 359 UINT16 NumberOfFrontJacks; 360 } PCH_AZALIA_VERB_TABLE_HEADER; 361 362 typedef struct { 363 PCH_AZALIA_VERB_TABLE_HEADER VerbTableHeader; 364 UINT32 *VerbTableData; 365 } PCH_AZALIA_VERB_TABLE; 366 367 typedef struct { 368 UINT8 Pme : 1; /// 0: Disable; 1: Enable 369 UINT8 DS : 1; /// 0: Docking is not supported; 1:Docking is supported 370 UINT8 DA : 1; /// 0: Docking is not attached; 1:Docking is attached 371 UINT8 HdmiCodec : 1; /// 0: Disable; 1: Enable 372 UINT8 AzaliaVCi : 1; /// 0: Disable; 1: Enable 373 UINT8 Rsvdbits : 3; 374 UINT8 AzaliaVerbTableNum; /// Number of verb tables provided by platform 375 PCH_AZALIA_VERB_TABLE *AzaliaVerbTable; /// Pointer to the actual verb table(s) 376 UINT16 ResetWaitTimer; /// The delay timer after Azalia reset, the value is number of microseconds 377 } PCH_AZALIA_CONFIG; 378 379 /// 380 /// --------------------------- Smbus Config ------------------------------ 381 /// 382 typedef struct { 383 UINT8 NumRsvdSmbusAddresses; 384 UINT8 *RsvdSmbusAddressTable; 385 } PCH_SMBUS_CONFIG; 386 387 /// 388 /// --------------------------- Miscellaneous PM Config ------------------------------ 389 /// 390 typedef struct { 391 UINT8 MeWakeSts : 1; 392 UINT8 MeHrstColdSts : 1; 393 UINT8 MeHrstWarmSts : 1; 394 UINT8 MeHostPowerDn : 1; 395 UINT8 WolOvrWkSts : 1; 396 UINT8 Rsvdbits : 3; 397 } PCH_POWER_RESET_STATUS; 398 399 typedef struct { 400 UINT8 PmeB0S5Dis : 1; 401 UINT8 WolEnableOverride : 1; 402 UINT8 Rsvdbits : 6; 403 } PCH_WAKE_CONFIG; 404 405 typedef enum { 406 PchSlpS360us, 407 PchSlpS31ms, 408 PchSlpS350ms, 409 PchSlpS32s 410 } PCH_SLP_S3_MIN_ASSERT; 411 412 typedef enum { 413 PchSlpS4PchTime, /// The time defined in EDS Power Sequencing and Reset Signal Timings table 414 PchSlpS41s, 415 PchSlpS42s, 416 PchSlpS43s, 417 PchSlpS44s 418 } PCH_SLP_S4_MIN_ASSERT; 419 420 typedef struct { 421 /// 422 /// Specify which Power/Reset bits need to be cleared by 423 /// the PCH Init Driver. 424 /// Usually platform drivers take care of these bits, but if 425 /// not, let PCH Init driver clear the bits. 426 /// 427 PCH_POWER_RESET_STATUS PowerResetStatusClear; 428 /// 429 /// Specify Wake Policy 430 /// 431 PCH_WAKE_CONFIG WakeConfig; 432 /// 433 /// SLP_XX Minimum Assertion Width Policy 434 /// 435 PCH_SLP_S3_MIN_ASSERT PchSlpS3MinAssert; 436 PCH_SLP_S4_MIN_ASSERT PchSlpS4MinAssert; 437 UINT8 SlpStrchSusUp : 1; /// Enable/Disable SLP_X Stretching After SUS Well Power Up 438 UINT8 SlpLanLowDc : 1; 439 UINT8 Rsvdbits : 6; 440 } PCH_MISC_PM_CONFIG; 441 442 /// 443 /// --------------------------- Subsystem Vendor ID / Subsystem ID Config ----- 444 /// 445 typedef struct { 446 UINT16 SubSystemVendorId; 447 UINT16 SubSystemId; 448 } PCH_DEFAULT_SVID_SID; 449 450 /// 451 /// --------------------------- Lock Down Config ------------------------------ 452 /// 453 typedef struct { 454 UINT8 GlobalSmi : 1; 455 UINT8 BiosInterface : 1; 456 UINT8 RtcLock : 1; 457 UINT8 BiosLock : 1; 458 UINT8 Rsvdbits : 4; 459 UINT8 PchBiosLockSwSmiNumber; 460 } PCH_LOCK_DOWN_CONFIG; 461 // 462 // --------------------------- Serial IRQ Config ------------------------------ 463 // 464 typedef enum { 465 PchQuietMode, 466 PchContinuousMode 467 } PCH_SIRQ_MODE; 468 /// 469 /// Refer to SoC EDS for the details of Start Frame Pulse Width in Continuous and Quiet mode 470 /// 471 472 typedef struct { 473 BOOLEAN SirqEnable; /// Determines if enable Serial IRQ 474 PCH_SIRQ_MODE SirqMode; /// Serial IRQ Mode Select 475 } PCH_LPC_SIRQ_CONFIG; 476 477 /// 478 /// --------------------------- Power Optimizer Config ------------------------------ 479 /// 480 typedef struct { 481 UINT8 NumOfDevLtrOverride; /// Number of Pci Express card listed in LTR override table 482 PCH_PCIE_DEVICE_LTR_OVERRIDE *DevLtrOverride; /// Pointer to Pci Express devices LTR override table 483 } PCH_PWR_OPT_CONFIG; 484 485 /// 486 /// --------------------- Low Power Input Output Config ------------------------ 487 /// 488 typedef struct { 489 UINT8 LpssPciModeEnabled : 1; /// Determines if LPSS PCI Mode enabled 490 UINT8 Dma0Enabled : 1; /// Determines if LPSS DMA1 enabled 491 UINT8 Dma1Enabled : 1; /// Determines if LPSS DMA2 enabled 492 UINT8 I2C0Enabled : 1; /// Determines if LPSS I2C #1 enabled 493 UINT8 I2C1Enabled : 1; /// Determines if LPSS I2C #2 enabled 494 UINT8 I2C2Enabled : 1; /// Determines if LPSS I2C #3 enabled 495 UINT8 I2C3Enabled : 1; /// Determines if LPSS I2C #4 enabled 496 UINT8 I2C4Enabled : 1; /// Determines if LPSS I2C #5 enabled 497 UINT8 I2C5Enabled : 1; /// Determines if LPSS I2C #6 enabled 498 UINT8 I2C6Enabled : 1; /// Determines if LPSS I2C #7 enabled 499 UINT8 Pwm0Enabled : 1; /// Determines if LPSS PWM #1 enabled 500 UINT8 Pwm1Enabled : 1; /// Determines if LPSS PWM #2 enabled 501 UINT8 Hsuart0Enabled : 1; /// Determines if LPSS HSUART #1 enabled 502 UINT8 Hsuart1Enabled : 1; /// Determines if LPSS HSUART #2 enabled 503 UINT8 SpiEnabled : 1; /// Determines if LPSS SPI enabled 504 UINT8 Rsvdbits : 2; 505 } PCH_LPSS_CONFIG; 506 507 /// 508 /// ----------------------------- SCC Config -------------------------------- 509 /// 510 typedef struct { 511 UINT8 eMMCEnabled : 1; /// Determines if SCC eMMC enabled 512 UINT8 SdioEnabled : 1; /// Determines if SCC SDIO enabled 513 UINT8 SdcardEnabled : 1; /// Determines if SCC SD Card enabled 514 UINT8 HsiEnabled : 1; /// Determines if SCC HSI enabled 515 UINT8 eMMC45Enabled : 1; /// Determines if SCC eMMC 4.5 enabled 516 UINT8 eMMC45DDR50Enabled : 1; /// Determines if DDR50 enabled for eMMC 4.5 517 UINT8 eMMC45HS200Enabled : 1; /// Determines if HS200nabled for eMMC 4.5 518 UINT8 Rsvdbits : 1; 519 UINT8 SdCardSDR25Enabled : 1; /// Determines if SDR25 for SD Card 520 UINT8 SdCardDDR50Enabled : 1; /// Determines if DDR50 for SD Card 521 UINT8 Rsvdbits1 : 6; 522 UINT8 eMMC45RetuneTimerValue; /// Determines retune timer value. 523 } PCH_SCC_CONFIG; 524 525 /// 526 /// ------------ General PCH Platform Policy protocol definition ------------ 527 /// 528 struct _DXE_PCH_PLATFORM_POLICY_PROTOCOL { 529 UINT8 Revision; 530 UINT8 BusNumber; /// PCI Bus Number of the PCH device 531 PCH_DEVICE_ENABLING *DeviceEnabling; 532 PCH_USB_CONFIG *UsbConfig; 533 PCH_PCI_EXPRESS_CONFIG *PciExpressConfig; 534 535 PCH_SATA_CONFIG *SataConfig; 536 PCH_AZALIA_CONFIG *AzaliaConfig; 537 PCH_SMBUS_CONFIG *SmbusConfig; 538 PCH_MISC_PM_CONFIG *MiscPmConfig; 539 PCH_DEFAULT_SVID_SID *DefaultSvidSid; 540 PCH_LOCK_DOWN_CONFIG *LockDownConfig; 541 PCH_LPC_SIRQ_CONFIG *SerialIrqConfig; 542 PCH_PWR_OPT_CONFIG *PwrOptConfig; 543 PCH_LPSS_CONFIG *LpssConfig; 544 PCH_SCC_CONFIG *SccConfig; 545 UINT8 IdleReserve; 546 UINT8 EhciPllCfgEnable; 547 UINT8 AcpiHWRed; //Hardware Reduced Mode 548 }; 549 550 #endif 551