1 /** @file 2 3 Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> 4 5 SPDX-License-Identifier: BSD-2-Clause-Patent 6 7 **/ 8 9 #ifndef __OMAP3530SDIO_H__ 10 #define __OMAP3530SDIO_H__ 11 12 //MMC/SD/SDIO1 register definitions. 13 #define MMCHS1BASE 0x4809C000 14 #define MMC_REFERENCE_CLK (96000000) 15 16 #define MMCHS_SYSCONFIG (MMCHS1BASE + 0x10) 17 #define SOFTRESET BIT1 18 #define ENAWAKEUP BIT2 19 20 #define MMCHS_SYSSTATUS (MMCHS1BASE + 0x14) 21 #define RESETDONE_MASK BIT0 22 #define RESETDONE BIT0 23 24 #define MMCHS_CSRE (MMCHS1BASE + 0x24) 25 #define MMCHS_SYSTEST (MMCHS1BASE + 0x28) 26 27 #define MMCHS_CON (MMCHS1BASE + 0x2C) 28 #define OD BIT0 29 #define NOINIT (0x0UL << 1) 30 #define INIT BIT1 31 #define HR BIT2 32 #define STR BIT3 33 #define MODE BIT4 34 #define DW8_1_4_BIT (0x0UL << 5) 35 #define DW8_8_BIT BIT5 36 #define MIT BIT6 37 #define CDP BIT7 38 #define WPP BIT8 39 #define CTPL BIT11 40 #define CEATA_OFF (0x0UL << 12) 41 #define CEATA_ON BIT12 42 43 #define MMCHS_PWCNT (MMCHS1BASE + 0x30) 44 45 #define MMCHS_BLK (MMCHS1BASE + 0x104) 46 #define BLEN_512BYTES (0x200UL << 0) 47 48 #define MMCHS_ARG (MMCHS1BASE + 0x108) 49 50 #define MMCHS_CMD (MMCHS1BASE + 0x10C) 51 #define DE_ENABLE BIT0 52 #define BCE_ENABLE BIT1 53 #define ACEN_ENABLE BIT2 54 #define DDIR_READ BIT4 55 #define DDIR_WRITE (0x0UL << 4) 56 #define MSBS_SGLEBLK (0x0UL << 5) 57 #define MSBS_MULTBLK BIT5 58 #define RSP_TYPE_MASK (0x3UL << 16) 59 #define RSP_TYPE_136BITS BIT16 60 #define RSP_TYPE_48BITS (0x2UL << 16) 61 #define CCCE_ENABLE BIT19 62 #define CICE_ENABLE BIT20 63 #define DP_ENABLE BIT21 64 #define INDX(CMD_INDX) ((CMD_INDX & 0x3F) << 24) 65 66 #define MMCHS_RSP10 (MMCHS1BASE + 0x110) 67 #define MMCHS_RSP32 (MMCHS1BASE + 0x114) 68 #define MMCHS_RSP54 (MMCHS1BASE + 0x118) 69 #define MMCHS_RSP76 (MMCHS1BASE + 0x11C) 70 #define MMCHS_DATA (MMCHS1BASE + 0x120) 71 72 #define MMCHS_PSTATE (MMCHS1BASE + 0x124) 73 #define CMDI_MASK BIT0 74 #define CMDI_ALLOWED (0x0UL << 0) 75 #define CMDI_NOT_ALLOWED BIT0 76 #define DATI_MASK BIT1 77 #define DATI_ALLOWED (0x0UL << 1) 78 #define DATI_NOT_ALLOWED BIT1 79 80 #define MMCHS_HCTL (MMCHS1BASE + 0x128) 81 #define DTW_1_BIT (0x0UL << 1) 82 #define DTW_4_BIT BIT1 83 #define SDBP_MASK BIT8 84 #define SDBP_OFF (0x0UL << 8) 85 #define SDBP_ON BIT8 86 #define SDVS_1_8_V (0x5UL << 9) 87 #define SDVS_3_0_V (0x6UL << 9) 88 #define IWE BIT24 89 90 #define MMCHS_SYSCTL (MMCHS1BASE + 0x12C) 91 #define ICE BIT0 92 #define ICS_MASK BIT1 93 #define ICS BIT1 94 #define CEN BIT2 95 #define CLKD_MASK (0x3FFUL << 6) 96 #define CLKD_80KHZ (0x258UL) //(96*1000/80)/2 97 #define CLKD_400KHZ (0xF0UL) 98 #define DTO_MASK (0xFUL << 16) 99 #define DTO_VAL (0xEUL << 16) 100 #define SRA BIT24 101 #define SRC_MASK BIT25 102 #define SRC BIT25 103 #define SRD BIT26 104 105 #define MMCHS_STAT (MMCHS1BASE + 0x130) 106 #define CC BIT0 107 #define TC BIT1 108 #define BWR BIT4 109 #define BRR BIT5 110 #define ERRI BIT15 111 #define CTO BIT16 112 #define DTO BIT20 113 #define DCRC BIT21 114 #define DEB BIT22 115 116 #define MMCHS_IE (MMCHS1BASE + 0x134) 117 #define CC_EN BIT0 118 #define TC_EN BIT1 119 #define BWR_EN BIT4 120 #define BRR_EN BIT5 121 #define CTO_EN BIT16 122 #define CCRC_EN BIT17 123 #define CEB_EN BIT18 124 #define CIE_EN BIT19 125 #define DTO_EN BIT20 126 #define DCRC_EN BIT21 127 #define DEB_EN BIT22 128 #define CERR_EN BIT28 129 #define BADA_EN BIT29 130 131 #define MMCHS_ISE (MMCHS1BASE + 0x138) 132 #define CC_SIGEN BIT0 133 #define TC_SIGEN BIT1 134 #define BWR_SIGEN BIT4 135 #define BRR_SIGEN BIT5 136 #define CTO_SIGEN BIT16 137 #define CCRC_SIGEN BIT17 138 #define CEB_SIGEN BIT18 139 #define CIE_SIGEN BIT19 140 #define DTO_SIGEN BIT20 141 #define DCRC_SIGEN BIT21 142 #define DEB_SIGEN BIT22 143 #define CERR_SIGEN BIT28 144 #define BADA_SIGEN BIT29 145 146 #define MMCHS_AC12 (MMCHS1BASE + 0x13C) 147 148 #define MMCHS_CAPA (MMCHS1BASE + 0x140) 149 #define VS30 BIT25 150 #define VS18 BIT26 151 152 #define MMCHS_CUR_CAPA (MMCHS1BASE + 0x148) 153 #define MMCHS_REV (MMCHS1BASE + 0x1FC) 154 155 #define CMD0 INDX(0) 156 #define CMD0_INT_EN (CC_EN | CEB_EN) 157 158 #define CMD1 (INDX(1) | RSP_TYPE_48BITS) 159 #define CMD1_INT_EN (CC_EN | CEB_EN | CTO_EN) 160 161 #define CMD2 (INDX(2) | CCCE_ENABLE | RSP_TYPE_136BITS) 162 #define CMD2_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN) 163 164 #define CMD3 (INDX(3) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS) 165 #define CMD3_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN) 166 167 #define CMD5 (INDX(5) | RSP_TYPE_48BITS) 168 #define CMD5_INT_EN (CC_EN | CEB_EN | CTO_EN) 169 170 #define CMD7 (INDX(7) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS) 171 #define CMD7_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN) 172 173 #define CMD8 (INDX(8) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS) 174 #define CMD8_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN) 175 //Reserved(0)[12:31], Supply voltage(1)[11:8], check pattern(0xCE)[7:0] = 0x1CE 176 #define CMD8_ARG (0x0UL << 12 | BIT8 | 0xCEUL << 0) 177 178 #define CMD9 (INDX(9) | CCCE_ENABLE | RSP_TYPE_136BITS) 179 #define CMD9_INT_EN (CCRC_EN | CC_EN | CEB_EN | CTO_EN) 180 181 #define CMD16 (INDX(16) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS) 182 #define CMD16_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN) 183 184 #define CMD17 (INDX(17) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | DDIR_READ) 185 #define CMD17_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BRR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN) 186 187 #define CMD18 (INDX(18) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | MSBS_MULTBLK | DDIR_READ | BCE_ENABLE | DE_ENABLE) 188 #define CMD18_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BRR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN) 189 190 #define CMD23 (INDX(23) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS) 191 #define CMD23_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN) 192 193 #define CMD24 (INDX(24) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | DDIR_WRITE) 194 #define CMD24_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BWR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN) 195 196 #define CMD25 (INDX(25) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | MSBS_MULTBLK | DDIR_READ | BCE_ENABLE | DE_ENABLE) 197 #define CMD25_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BRR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN) 198 199 #define CMD55 (INDX(55) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS) 200 #define CMD55_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN) 201 202 #define ACMD41 (INDX(41) | RSP_TYPE_48BITS) 203 #define ACMD41_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN) 204 205 #define ACMD6 (INDX(6) | RSP_TYPE_48BITS) 206 #define ACMD6_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN) 207 208 #endif //__OMAP3530SDIO_H__ 209