1 /*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2011 Carl-Daniel Hailfinger
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 /* Datasheet: http://download.intel.com/design/network/datashts/82559_Fast_Ethernet_Multifunction_PCI_Cardbus_Controller_Datasheet.pdf */
17
18 #include <stdlib.h>
19 #include "flash.h"
20 #include "programmer.h"
21 #include "hwaccess.h"
22
23 static uint8_t *nicintel_bar;
24 static uint8_t *nicintel_control_bar;
25
26 const struct dev_entry nics_intel[] = {
27 {PCI_VENDOR_ID_INTEL, 0x1209, NT, "Intel", "8255xER/82551IT Fast Ethernet Controller"},
28 {PCI_VENDOR_ID_INTEL, 0x1229, OK, "Intel", "82557/8/9/0/1 Ethernet Pro 100"},
29
30 {0},
31 };
32
33 /* Arbitrary limit, taken from the datasheet I just had lying around.
34 * 128 kByte on the 82559 device. Or not. Depends on whom you ask.
35 */
36 #define NICINTEL_MEMMAP_SIZE (128 * 1024)
37 #define NICINTEL_MEMMAP_MASK (NICINTEL_MEMMAP_SIZE - 1)
38
39 #define NICINTEL_CONTROL_MEMMAP_SIZE 0x10
40
41 #define CSR_FCR 0x0c
42
43 static void nicintel_chip_writeb(const struct flashctx *flash, uint8_t val,
44 chipaddr addr);
45 static uint8_t nicintel_chip_readb(const struct flashctx *flash,
46 const chipaddr addr);
47 static const struct par_master par_master_nicintel = {
48 .chip_readb = nicintel_chip_readb,
49 .chip_readw = fallback_chip_readw,
50 .chip_readl = fallback_chip_readl,
51 .chip_readn = fallback_chip_readn,
52 .chip_writeb = nicintel_chip_writeb,
53 .chip_writew = fallback_chip_writew,
54 .chip_writel = fallback_chip_writel,
55 .chip_writen = fallback_chip_writen,
56 };
57
nicintel_init(void)58 int nicintel_init(void)
59 {
60 struct pci_dev *dev = NULL;
61 uintptr_t addr;
62
63 /* Needed only for PCI accesses on some platforms.
64 * FIXME: Refactor that into get_mem_perms/rget_io_perms/get_pci_perms?
65 */
66 if (rget_io_perms())
67 return 1;
68
69 /* FIXME: BAR2 is not available if the device uses the CardBus function. */
70 dev = pcidev_init(nics_intel, PCI_BASE_ADDRESS_2);
71 if (!dev)
72 return 1;
73
74 addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_2);
75 if (!addr)
76 return 1;
77
78 nicintel_bar = rphysmap("Intel NIC flash", addr, NICINTEL_MEMMAP_SIZE);
79 if (nicintel_bar == ERROR_PTR)
80 return 1;
81
82 addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
83 if (!addr)
84 return 1;
85
86 nicintel_control_bar = rphysmap("Intel NIC control/status reg", addr, NICINTEL_CONTROL_MEMMAP_SIZE);
87 if (nicintel_control_bar == ERROR_PTR)
88 return 1;
89
90 /* FIXME: This register is pretty undocumented in all publicly available
91 * documentation from Intel. Let me quote the complete info we have:
92 * "Flash Control Register: The Flash Control register allows the CPU to
93 * enable writes to an external Flash. The Flash Control Register is a
94 * 32-bit field that allows access to an external Flash device."
95 * Ah yes, we also know where it is, but we have absolutely _no_ idea
96 * what we should do with it. Write 0x0001 because we have nothing
97 * better to do with our time.
98 */
99 pci_rmmio_writew(0x0001, nicintel_control_bar + CSR_FCR);
100
101 max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE;
102 register_par_master(&par_master_nicintel, BUS_PARALLEL);
103
104 return 0;
105 }
106
nicintel_chip_writeb(const struct flashctx * flash,uint8_t val,chipaddr addr)107 static void nicintel_chip_writeb(const struct flashctx *flash, uint8_t val,
108 chipaddr addr)
109 {
110 pci_mmio_writeb(val, nicintel_bar + (addr & NICINTEL_MEMMAP_MASK));
111 }
112
nicintel_chip_readb(const struct flashctx * flash,const chipaddr addr)113 static uint8_t nicintel_chip_readb(const struct flashctx *flash,
114 const chipaddr addr)
115 {
116 return pci_mmio_readb(nicintel_bar + (addr & NICINTEL_MEMMAP_MASK));
117 }
118