1 /*
2 Copyright (c) 2009-2019, Intel Corporation
3 All rights reserved.
4
5 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
6
7 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
8 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
9 * Neither the name of Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
10
11 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
12 */
13 // written by Roman Dementiev,
14 // Patrick Konsor
15 //
16
17 #include <iostream>
18 #include "bw.h"
19 #include "pci.h"
20 #include "utils.h"
21
22 namespace pcm {
23
24 constexpr auto PCM_CLIENT_IMC_BAR_OFFSET = 0x0048;
25 constexpr auto PCM_TGL_IMC_STEP = 0x10000;
26 unsigned int PCM_TGL_IMC_DRAM_DATA_READS[2] = { 0x5058, 0xd858 };
27 unsigned int PCM_TGL_IMC_DRAM_DATA_WRITES[2] = { 0x50A0, 0xd8A0 };
28 unsigned int PCM_TGL_IMC_MMAP_SIZE[2] = { 0x5000 + 0x1000, 0xd000 + 0x1000 };
29 unsigned int PCM_TGL_IMC_EVENT_BASE[2] = { 0x5000, 0xd000 };
30
getClientIMCStartAddr()31 uint64 getClientIMCStartAddr()
32 {
33 PciHandleType imcHandle(0, 0, 0, 0); // memory controller device coordinates: domain 0, bus 0, device 0, function 0
34 uint64 imcbar = 0;
35 imcHandle.read64(PCM_CLIENT_IMC_BAR_OFFSET, &imcbar);
36 // std::cout << "DEBUG: imcbar=" << std::hex << imcbar << "\n" << std::flush;
37 if (!imcbar)
38 {
39 std::cerr << "ERROR: imcbar is zero.\n";
40 throw std::exception();
41 }
42 return imcbar & (~(4096ULL - 1ULL)); // round down to 4K
43 }
44
TGLClientBW()45 TGLClientBW::TGLClientBW()
46 {
47 PCM_CPUID_INFO cpuinfo;
48 pcm_cpuid(1, cpuinfo); // need to retrieve original cpu id (undo cpu model merging)
49 model = ((cpuinfo.array[0]) & 0x10) >> 4;
50 const auto startAddr = getClientIMCStartAddr();
51 for (size_t i = 0; i < mmioRange.size(); ++i)
52 {
53 mmioRange[i] = std::make_shared<MMIORange>(startAddr + i * PCM_TGL_IMC_STEP + PCM_TGL_IMC_EVENT_BASE[model], PCM_TGL_IMC_MMAP_SIZE[model] - PCM_TGL_IMC_EVENT_BASE[model]);
54 }
55 }
56
getImcReads()57 uint64 TGLClientBW::getImcReads()
58 {
59 uint64 result = 0;
60 for (auto r : mmioRange)
61 {
62 result += r->read64(PCM_TGL_IMC_DRAM_DATA_READS[model] - PCM_TGL_IMC_EVENT_BASE[model]);
63 }
64 return result;
65 }
66
getImcWrites()67 uint64 TGLClientBW::getImcWrites()
68 {
69 uint64 result = 0;
70 for (auto r : mmioRange)
71 {
72 result += r->read64(PCM_TGL_IMC_DRAM_DATA_WRITES[model] - PCM_TGL_IMC_EVENT_BASE[model]);
73 }
74 return result;
75 }
76
77 #define PCM_CLIENT_IMC_DRAM_IO_REQESTS (0x5048)
78 #define PCM_CLIENT_IMC_DRAM_DATA_READS (0x5050)
79 #define PCM_CLIENT_IMC_DRAM_DATA_WRITES (0x5054)
80 #define PCM_CLIENT_IMC_MMAP_SIZE (0x6000)
81 #define PCM_CLIENT_IMC_EVENT_BASE (0x5000)
82
ClientBW()83 ClientBW::ClientBW()
84 {
85 mmioRange = std::make_shared<MMIORange>(getClientIMCStartAddr() + PCM_CLIENT_IMC_EVENT_BASE, PCM_CLIENT_IMC_MMAP_SIZE - PCM_CLIENT_IMC_EVENT_BASE);
86 }
87
getImcReads()88 uint64 ClientBW::getImcReads()
89 {
90 return mmioRange->read32(PCM_CLIENT_IMC_DRAM_DATA_READS - PCM_CLIENT_IMC_EVENT_BASE);
91 }
92
getImcWrites()93 uint64 ClientBW::getImcWrites()
94 {
95 return mmioRange->read32(PCM_CLIENT_IMC_DRAM_DATA_WRITES - PCM_CLIENT_IMC_EVENT_BASE);
96 }
97
getIoRequests()98 uint64 ClientBW::getIoRequests()
99 {
100 return mmioRange->read32(PCM_CLIENT_IMC_DRAM_IO_REQESTS - PCM_CLIENT_IMC_EVENT_BASE);
101 }
102
103 #define PCM_SERVER_IMC_DRAM_DATA_READS (0x2290)
104 #define PCM_SERVER_IMC_DRAM_DATA_WRITES (0x2298)
105 #define PCM_SERVER_IMC_PMM_DATA_READS (0x22a0)
106 #define PCM_SERVER_IMC_PMM_DATA_WRITES (0x22a8)
107 #define PCM_SERVER_IMC_MMAP_SIZE (0x4000)
108
getServerMemBars(const uint32 numIMC,const uint32 root_segment_ubox0,const uint32 root_bus_ubox0)109 std::vector<size_t> getServerMemBars(const uint32 numIMC, const uint32 root_segment_ubox0, const uint32 root_bus_ubox0)
110 {
111 std::vector<size_t> result;
112 PciHandleType ubox0Handle(root_segment_ubox0, root_bus_ubox0, SERVER_UBOX0_REGISTER_DEV_ADDR, SERVER_UBOX0_REGISTER_FUNC_ADDR);
113 uint32 mmioBase = 0;
114 ubox0Handle.read32(0xd0, &mmioBase);
115 for (uint32 i = 0; i < numIMC; ++i)
116 {
117 uint32 memOffset = 0;
118 ubox0Handle.read32(0xd8 + i * 4, &memOffset);
119 size_t memBar = ((mmioBase & ((1ULL << 29ULL) - 1ULL)) << 23ULL) |
120 ((memOffset & ((1ULL << 11ULL) - 1ULL)) << 12ULL);
121 if (memBar == 0)
122 {
123 std::cerr << "ERROR: memBar " << i << " is zero." << std::endl;
124 throw std::exception();
125 }
126 result.push_back(memBar);
127 }
128 return result;
129 }
130
ServerBW(const uint32 numIMC,const uint32 root_segment_ubox0,const uint32 root_bus_ubox0)131 ServerBW::ServerBW(const uint32 numIMC, const uint32 root_segment_ubox0, const uint32 root_bus_ubox0)
132 {
133 auto memBars = getServerMemBars(numIMC, root_segment_ubox0, root_bus_ubox0);
134 for (auto & memBar: memBars)
135 {
136 mmioRanges.push_back(std::make_shared<MMIORange>(memBar, PCM_SERVER_IMC_MMAP_SIZE));
137 }
138 }
139
getImcReads()140 uint64 ServerBW::getImcReads()
141 {
142 uint64 result = 0;
143 for (auto & mmio: mmioRanges)
144 {
145 result += mmio->read64(PCM_SERVER_IMC_DRAM_DATA_READS);
146 }
147 return result;
148 }
149
getImcWrites()150 uint64 ServerBW::getImcWrites()
151 {
152 uint64 result = 0;
153 for (auto & mmio : mmioRanges)
154 {
155 result += mmio->read64(PCM_SERVER_IMC_DRAM_DATA_WRITES);
156 }
157 return result;
158 }
159
getPMMReads()160 uint64 ServerBW::getPMMReads()
161 {
162 uint64 result = 0;
163 for (auto & mmio : mmioRanges)
164 {
165 result += mmio->read64(PCM_SERVER_IMC_PMM_DATA_READS);
166 }
167 return result;
168 }
169
getPMMWrites()170 uint64 ServerBW::getPMMWrites()
171 {
172 uint64 result = 0;
173 for (auto & mmio : mmioRanges)
174 {
175 result += mmio->read64(PCM_SERVER_IMC_PMM_DATA_WRITES);
176 }
177 return result;
178 }
179
180 } // namespace pcm