1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Chip-specific header file for the SAMA7G5 SoC 4 * 5 * Copyright (C) 2020 Microchip Technology, Inc. and its subsidiaries 6 * Eugen Hristev <eugen.hristev@microchip.com> 7 */ 8 9 #ifndef __SAMA7G5_H__ 10 #define __SAMA7G5_H__ 11 12 /* 13 * Peripheral identifiers/interrupts. 14 */ 15 #define ATMEL_ID_FLEXCOM0 38 16 #define ATMEL_ID_FLEXCOM1 39 17 #define ATMEL_ID_FLEXCOM2 40 18 #define ATMEL_ID_FLEXCOM3 41 19 20 #define ATMEL_ID_SDMMC0 80 21 #define ATMEL_ID_SDMMC1 81 22 23 #define ATMEL_ID_PIT64B0 70 24 #define ATMEL_ID_PIT64B ATMEL_ID_PIT64B0 25 26 #define ATMEL_CHIPID_CIDR 0xe0020000 27 #define ATMEL_CHIPID_EXID 0xe0020004 28 /* 29 * User Peripherals physical base addresses. 30 */ 31 #define ATMEL_BASE_PIOA 0xe0014000 32 #define ATMEL_BASE_PIOB (ATMEL_BASE_PIOA + 0x40) 33 #define ATMEL_BASE_PIOC (ATMEL_BASE_PIOB + 0x40) 34 #define ATMEL_BASE_PIOD (ATMEL_BASE_PIOC + 0x40) 35 #define ATMEL_BASE_PIOE (ATMEL_BASE_PIOD + 0x40) 36 37 #define ATMEL_PIO_PORTS 5 38 39 #define CPU_HAS_PCR 40 41 #define ATMEL_BASE_PMC 0xe0018000 42 43 #define ATMEL_BASE_WDT 0xe001c000 44 #define ATMEL_BASE_RSTC 0xe001d000 45 #define ATMEL_BASE_WDTS 0xe001d180 46 #define ATMEL_BASE_SCKCR 0xe001d050 47 48 #define ATMEL_BASE_SDMMC0 0xe1204000 49 #define ATMEL_BASE_SDMMC1 0xe1208000 50 51 #define ATMEL_BASE_PIT64B0 0xe1800000 52 53 #define ATMEL_BASE_FLEXCOM0 0xe1818000 54 #define ATMEL_BASE_FLEXCOM1 0xe181c000 55 #define ATMEL_BASE_FLEXCOM2 0xe1820000 56 #define ATMEL_BASE_FLEXCOM3 0xe1824000 57 #define ATMEL_BASE_FLEXCOM4 0xe2018000 58 59 #define ATMEL_BASE_TZC400 0xe3000000 60 61 #define ATMEL_BASE_UMCTL2 0xe3800000 62 #define ATMEL_BASE_UMCTL2_MP 0xe38003f8 63 #define ATMEL_BASE_PUBL 0xe3804000 64 65 #define ATMEL_NUM_FLEXCOM 12 66 #define ATMEL_PIO_PORTS 5 67 68 #define ATMEL_BASE_PIT64BC ATMEL_BASE_PIT64B0 69 70 #ifndef __ASSEMBLY__ 71 char *get_cpu_name(void); 72 #endif 73 74 #endif /* #ifndef __SAMA7G5_H__ */ 75