1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (c) 2011 The Chromium OS Authors.
4  */
5 
6 #ifndef __MIPS_CACHE_H__
7 #define __MIPS_CACHE_H__
8 
9 #define L1_CACHE_SHIFT		CONFIG_MIPS_L1_CACHE_SHIFT
10 #define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
11 
12 #define ARCH_DMA_MINALIGN	(L1_CACHE_BYTES)
13 
14 /*
15  * CONFIG_SYS_CACHELINE_SIZE is still used in various drivers primarily for
16  * DMA buffer alignment. Satisfy those drivers by providing it as a synonym
17  * of ARCH_DMA_MINALIGN for now.
18  */
19 #define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN
20 
21 #ifndef __ASSEMBLY__
22 /**
23  * mips_cache_probe() - Probe the properties of the caches
24  *
25  * Call this to probe the properties such as line sizes of the caches
26  * present in the system, if any. This must be done before cache maintenance
27  * functions such as flush_cache may be called.
28  */
29 void mips_cache_probe(void);
30 #endif
31 
32 #endif /* __MIPS_CACHE_H__ */
33