1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/aspeed-clock.h> 3#include <dt-bindings/reset/ast2500-reset.h> 4 5#include "ast2500.dtsi" 6 7/ { 8 scu: clock-controller@1e6e2000 { 9 compatible = "aspeed,ast2500-scu"; 10 reg = <0x1e6e2000 0x1000>; 11 u-boot,dm-pre-reloc; 12 #clock-cells = <1>; 13 #reset-cells = <1>; 14 }; 15 16 rst: reset-controller { 17 u-boot,dm-pre-reloc; 18 compatible = "aspeed,ast2500-reset"; 19 #reset-cells = <1>; 20 }; 21 22 sdrammc: sdrammc@1e6e0000 { 23 u-boot,dm-pre-reloc; 24 compatible = "aspeed,ast2500-sdrammc"; 25 reg = <0x1e6e0000 0x174 26 0x1e6e0200 0x1d4 >; 27 #reset-cells = <1>; 28 clocks = <&scu ASPEED_CLK_MPLL>; 29 resets = <&rst ASPEED_RESET_SDRAM>; 30 }; 31 32 ahb { 33 u-boot,dm-pre-reloc; 34 35 apb { 36 u-boot,dm-pre-reloc; 37 38 sdhci0: sdhci@1e740100 { 39 compatible = "aspeed,ast2500-sdhci"; 40 reg = <0x1e740100>; 41 #reset-cells = <1>; 42 clocks = <&scu ASPEED_CLK_SDIO>; 43 resets = <&rst ASPEED_RESET_SDIO>; 44 }; 45 46 sdhci1: sdhci@1e740200 { 47 compatible = "aspeed,ast2500-sdhci"; 48 reg = <0x1e740200>; 49 #reset-cells = <1>; 50 clocks = <&scu ASPEED_CLK_SDIO>; 51 resets = <&rst ASPEED_RESET_SDIO>; 52 }; 53 }; 54 55 }; 56}; 57 58&uart1 { 59 clocks = <&scu ASPEED_CLK_GATE_UART1CLK>; 60}; 61 62&uart2 { 63 clocks = <&scu ASPEED_CLK_GATE_UART2CLK>; 64}; 65 66&uart3 { 67 clocks = <&scu ASPEED_CLK_GATE_UART3CLK>; 68}; 69 70&uart4 { 71 clocks = <&scu ASPEED_CLK_GATE_UART4CLK>; 72}; 73 74&uart5 { 75 clocks = <&scu ASPEED_CLK_GATE_UART5CLK>; 76}; 77 78&timer { 79 u-boot,dm-pre-reloc; 80}; 81 82&mac0 { 83 clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>; 84}; 85 86&mac1 { 87 clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>; 88}; 89