1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2018 NXP 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include "fsl-imx8-ca53.dtsi" 8#include <dt-bindings/clock/imx8qm-clock.h> 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/soc/imx_rsrc.h> 11#include <dt-bindings/soc/imx8_pd.h> 12#include <dt-bindings/pinctrl/pads-imx8qm.h> 13#include <dt-bindings/gpio/gpio.h> 14 15/ { 16 compatible = "fsl,imx8qm"; 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 ethernet0 = &fec1; 23 ethernet1 = &fec2; 24 gpio0 = &gpio0; 25 gpio1 = &gpio1; 26 gpio2 = &gpio2; 27 gpio3 = &gpio3; 28 gpio4 = &gpio4; 29 gpio5 = &gpio5; 30 gpio6 = &gpio6; 31 gpio7 = &gpio7; 32 serial0 = &lpuart0; 33 serial1 = &lpuart1; 34 serial2 = &lpuart2; 35 serial3 = &lpuart3; 36 serial4 = &lpuart4; 37 mmc0 = &usdhc1; 38 mmc1 = &usdhc2; 39 mmc2 = &usdhc3; 40 i2c0 = &i2c0; 41 i2c1 = &i2c1; 42 i2c2 = &i2c2; 43 i2c3 = &i2c3; 44 i2c4 = &i2c4; 45 }; 46 47 memory@80000000 { 48 device_type = "memory"; 49 reg = <0x00000000 0x80000000 0 0x40000000>; 50 /* DRAM space - 1, size : 1 GB DRAM */ 51 }; 52 53 gic: interrupt-controller@51a00000 { 54 compatible = "arm,gic-v3"; 55 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ 56 <0x0 0x51b00000 0 0xC0000>, /* GICR */ 57 <0x0 0x52000000 0 0x2000>, /* GICC */ 58 <0x0 0x52010000 0 0x1000>, /* GICH */ 59 <0x0 0x52020000 0 0x20000>; /* GICV */ 60 #interrupt-cells = <3>; 61 interrupt-controller; 62 interrupts = <GIC_PPI 9 63 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 64 interrupt-parent = <&gic>; 65 }; 66 67 mu: mu@5d1c0000 { 68 compatible = "fsl,imx8-mu"; 69 reg = <0x0 0x5d1c0000 0x0 0x10000>; 70 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 71 interrupt-parent = <&gic>; 72 fsl,scu_ap_mu_id = <0>; 73 status = "okay"; 74 75 clk: clk { 76 compatible = "fsl,imx8qm-clk"; 77 #clock-cells = <1>; 78 }; 79 80 iomuxc: iomuxc { 81 compatible = "fsl,imx8qm-iomuxc"; 82 }; 83 }; 84 85 imx8qm-pm { 86 compatible = "simple-bus"; 87 #address-cells = <1>; 88 #size-cells = <0>; 89 90 pd_lsio: PD_LSIO { 91 compatible = "nxp,imx8-pd"; 92 reg = <SC_R_NONE>; 93 #power-domain-cells = <0>; 94 #address-cells = <1>; 95 #size-cells = <0>; 96 97 pd_lsio_gpio0: PD_LSIO_GPIO_0 { 98 reg = <SC_R_GPIO_0>; 99 #power-domain-cells = <0>; 100 power-domains = <&pd_lsio>; 101 }; 102 pd_lsio_gpio1: PD_LSIO_GPIO_1 { 103 reg = <SC_R_GPIO_1>; 104 #power-domain-cells = <0>; 105 power-domains = <&pd_lsio>; 106 }; 107 pd_lsio_gpio2: PD_LSIO_GPIO_2 { 108 reg = <SC_R_GPIO_2>; 109 #power-domain-cells = <0>; 110 power-domains = <&pd_lsio>; 111 }; 112 pd_lsio_gpio3: PD_LSIO_GPIO_3 { 113 reg = <SC_R_GPIO_3>; 114 #power-domain-cells = <0>; 115 power-domains = <&pd_lsio>; 116 }; 117 pd_lsio_gpio4: PD_LSIO_GPIO_4 { 118 reg = <SC_R_GPIO_4>; 119 #power-domain-cells = <0>; 120 power-domains = <&pd_lsio>; 121 }; 122 pd_lsio_gpio5: PD_LSIO_GPIO_5{ 123 reg = <SC_R_GPIO_5>; 124 #power-domain-cells = <0>; 125 power-domains = <&pd_lsio>; 126 }; 127 pd_lsio_gpio6:PD_LSIO_GPIO_6 { 128 reg = <SC_R_GPIO_6>; 129 #power-domain-cells = <0>; 130 power-domains = <&pd_lsio>; 131 }; 132 pd_lsio_gpio7: PD_LSIO_GPIO_7 { 133 reg = <SC_R_GPIO_7>; 134 #power-domain-cells = <0>; 135 power-domains = <&pd_lsio>; 136 }; 137 }; 138 139 pd_conn: PD_CONN { 140 compatible = "nxp,imx8-pd"; 141 reg = <SC_R_NONE>; 142 #power-domain-cells = <0>; 143 #address-cells = <1>; 144 #size-cells = <0>; 145 146 pd_conn_sdch0: PD_CONN_SDHC_0 { 147 reg = <SC_R_SDHC_0>; 148 #power-domain-cells = <0>; 149 power-domains = <&pd_conn>; 150 }; 151 pd_conn_sdch1: PD_CONN_SDHC_1 { 152 reg = <SC_R_SDHC_1>; 153 #power-domain-cells = <0>; 154 power-domains = <&pd_conn>; 155 }; 156 pd_conn_sdch2: PD_CONN_SDHC_2 { 157 reg = <SC_R_SDHC_2>; 158 #power-domain-cells = <0>; 159 power-domains = <&pd_conn>; 160 }; 161 pd_conn_enet0: PD_CONN_ENET_0 { 162 reg = <SC_R_ENET_0>; 163 #power-domain-cells = <0>; 164 power-domains = <&pd_conn>; 165 wakeup-irq = <258>; 166 }; 167 pd_conn_enet1: PD_CONN_ENET_1 { 168 reg = <SC_R_ENET_1>; 169 #power-domain-cells = <0>; 170 power-domains = <&pd_conn>; 171 fsl,wakeup_irq = <262>; 172 }; 173 }; 174 175 pd_dma: PD_DMA { 176 compatible = "nxp,imx8-pd"; 177 reg = <SC_R_NONE>; 178 #power-domain-cells = <0>; 179 #address-cells = <1>; 180 #size-cells = <0>; 181 182 pd_dma_lpi2c0: PD_DMA_I2C_0 { 183 reg = <SC_R_I2C_0>; 184 #power-domain-cells = <0>; 185 power-domains = <&pd_dma>; 186 }; 187 pd_dma_lpi2c1: PD_DMA_I2C_1 { 188 reg = <SC_R_I2C_1>; 189 #power-domain-cells = <0>; 190 power-domains = <&pd_dma>; 191 }; 192 pd_dma_lpi2c2:PD_DMA_I2C_2 { 193 reg = <SC_R_I2C_2>; 194 #power-domain-cells = <0>; 195 power-domains = <&pd_dma>; 196 }; 197 pd_dma_lpi2c3: PD_DMA_I2C_3 { 198 reg = <SC_R_I2C_3>; 199 #power-domain-cells = <0>; 200 power-domains = <&pd_dma>; 201 }; 202 pd_dma_lpi2c4: PD_DMA_I2C_4 { 203 reg = <SC_R_I2C_4>; 204 #power-domain-cells = <0>; 205 power-domains = <&pd_dma>; 206 }; 207 pd_dma_lpuart0: PD_DMA_UART0 { 208 reg = <SC_R_UART_0>; 209 #power-domain-cells = <0>; 210 power-domains = <&pd_dma>; 211 wakeup-irq = <345>; 212 }; 213 pd_dma_lpuart1: PD_DMA_UART1 { 214 reg = <SC_R_UART_1>; 215 #power-domain-cells = <0>; 216 power-domains = <&pd_dma>; 217 wakeup-irq = <346>; 218 }; 219 pd_dma_lpuart2: PD_DMA_UART2 { 220 reg = <SC_R_UART_2>; 221 #power-domain-cells = <0>; 222 power-domains = <&pd_dma>; 223 wakeup-irq = <347>; 224 }; 225 pd_dma_lpuart3: PD_DMA_UART3 { 226 reg = <SC_R_UART_3>; 227 #power-domain-cells = <0>; 228 power-domains = <&pd_dma>; 229 wakeup-irq = <348>; 230 }; 231 pd_dma_lpuart4: PD_DMA_UART4 { 232 reg = <SC_R_UART_4>; 233 #power-domain-cells = <0>; 234 power-domains = <&pd_dma>; 235 wakeup-irq = <349>; 236 }; 237 }; 238 }; 239 240 i2c0: i2c@5a800000 { 241 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 242 reg = <0x0 0x5a800000 0x0 0x4000>; 243 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 244 interrupt-parent = <&gic>; 245 clocks = <&clk IMX8QM_I2C0_CLK>, 246 <&clk IMX8QM_I2C0_IPG_CLK>; 247 clock-names = "per", "ipg"; 248 assigned-clocks = <&clk IMX8QM_I2C0_CLK>; 249 assigned-clock-rates = <24000000>; 250 power-domains = <&pd_dma_lpi2c0>; 251 status = "disabled"; 252 }; 253 254 i2c1: i2c@5a810000 { 255 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 256 reg = <0x0 0x5a810000 0x0 0x4000>; 257 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 258 interrupt-parent = <&gic>; 259 clocks = <&clk IMX8QM_I2C1_CLK>, 260 <&clk IMX8QM_I2C1_IPG_CLK>; 261 clock-names = "per", "ipg"; 262 assigned-clocks = <&clk IMX8QM_I2C1_CLK>; 263 assigned-clock-rates = <24000000>; 264 power-domains = <&pd_dma_lpi2c1>; 265 status = "disabled"; 266 }; 267 268 i2c2: i2c@5a820000 { 269 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 270 reg = <0x0 0x5a820000 0x0 0x4000>; 271 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 272 interrupt-parent = <&gic>; 273 clocks = <&clk IMX8QM_I2C2_CLK>, 274 <&clk IMX8QM_I2C2_IPG_CLK>; 275 clock-names = "per", "ipg"; 276 assigned-clocks = <&clk IMX8QM_I2C2_CLK>; 277 assigned-clock-rates = <24000000>; 278 power-domains = <&pd_dma_lpi2c2>; 279 status = "disabled"; 280 }; 281 282 i2c3: i2c@5a830000 { 283 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 284 reg = <0x0 0x5a830000 0x0 0x4000>; 285 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 286 interrupt-parent = <&gic>; 287 clocks = <&clk IMX8QM_I2C3_CLK>, 288 <&clk IMX8QM_I2C3_IPG_CLK>; 289 clock-names = "per", "ipg"; 290 assigned-clocks = <&clk IMX8QM_I2C3_CLK>; 291 assigned-clock-rates = <24000000>; 292 power-domains = <&pd_dma_lpi2c3>; 293 status = "disabled"; 294 }; 295 296 i2c4: i2c@5a840000 { 297 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 298 reg = <0x0 0x5a840000 0x0 0x4000>; 299 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 300 interrupt-parent = <&gic>; 301 clocks = <&clk IMX8QM_I2C4_CLK>, 302 <&clk IMX8QM_I2C4_IPG_CLK>; 303 clock-names = "per", "ipg"; 304 assigned-clocks = <&clk IMX8QM_I2C4_CLK>; 305 assigned-clock-rates = <24000000>; 306 power-domains = <&pd_dma_lpi2c4>; 307 status = "disabled"; 308 }; 309 310 gpio0: gpio@5d080000 { 311 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 312 reg = <0x0 0x5d080000 0x0 0x10000>; 313 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 314 gpio-controller; 315 #gpio-cells = <2>; 316 power-domains = <&pd_lsio_gpio0>; 317 interrupt-controller; 318 #interrupt-cells = <2>; 319 }; 320 321 gpio1: gpio@5d090000 { 322 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 323 reg = <0x0 0x5d090000 0x0 0x10000>; 324 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 325 gpio-controller; 326 #gpio-cells = <2>; 327 power-domains = <&pd_lsio_gpio1>; 328 interrupt-controller; 329 #interrupt-cells = <2>; 330 }; 331 332 gpio2: gpio@5d0a0000 { 333 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 334 reg = <0x0 0x5d0a0000 0x0 0x10000>; 335 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 336 gpio-controller; 337 #gpio-cells = <2>; 338 power-domains = <&pd_lsio_gpio2>; 339 interrupt-controller; 340 #interrupt-cells = <2>; 341 }; 342 343 gpio3: gpio@5d0b0000 { 344 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 345 reg = <0x0 0x5d0b0000 0x0 0x10000>; 346 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 347 gpio-controller; 348 #gpio-cells = <2>; 349 power-domains = <&pd_lsio_gpio3>; 350 interrupt-controller; 351 #interrupt-cells = <2>; 352 }; 353 354 gpio4: gpio@5d0c0000 { 355 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 356 reg = <0x0 0x5d0c0000 0x0 0x10000>; 357 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 358 gpio-controller; 359 #gpio-cells = <2>; 360 power-domains = <&pd_lsio_gpio4>; 361 interrupt-controller; 362 #interrupt-cells = <2>; 363 }; 364 365 gpio5: gpio@5d0d0000 { 366 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 367 reg = <0x0 0x5d0d0000 0x0 0x10000>; 368 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 369 gpio-controller; 370 #gpio-cells = <2>; 371 power-domains = <&pd_lsio_gpio5>; 372 interrupt-controller; 373 #interrupt-cells = <2>; 374 }; 375 376 gpio6: gpio@5d0e0000 { 377 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 378 reg = <0x0 0x5d0e0000 0x0 0x10000>; 379 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 380 gpio-controller; 381 #gpio-cells = <2>; 382 power-domains = <&pd_lsio_gpio6>; 383 interrupt-controller; 384 #interrupt-cells = <2>; 385 }; 386 387 gpio7: gpio@5d0f0000 { 388 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 389 reg = <0x0 0x5d0f0000 0x0 0x10000>; 390 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 391 gpio-controller; 392 #gpio-cells = <2>; 393 power-domains = <&pd_lsio_gpio7>; 394 interrupt-controller; 395 #interrupt-cells = <2>; 396 }; 397 398 lpuart0: serial@5a060000 { 399 compatible = "fsl,imx8qm-lpuart"; 400 reg = <0x0 0x5a060000 0x0 0x1000>; 401 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 402 clocks = <&clk IMX8QM_UART0_CLK>, 403 <&clk IMX8QM_UART0_IPG_CLK>; 404 clock-names = "per", "ipg"; 405 assigned-clocks = <&clk IMX8QM_UART0_CLK>; 406 assigned-clock-rates = <80000000>; 407 power-domains = <&pd_dma_lpuart0>; 408 status = "disabled"; 409 }; 410 411 lpuart1: serial@5a070000 { 412 compatible = "fsl,imx8qm-lpuart"; 413 reg = <0x0 0x5a070000 0x0 0x1000>; 414 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; 415 clocks = <&clk IMX8QM_UART1_CLK>, 416 <&clk IMX8QM_UART1_IPG_CLK>; 417 clock-names = "per", "ipg"; 418 assigned-clocks = <&clk IMX8QM_UART1_CLK>; 419 assigned-clock-rates = <80000000>; 420 power-domains = <&pd_dma_lpuart1>; 421 status = "disabled"; 422 }; 423 424 lpuart2: serial@5a080000 { 425 compatible = "fsl,imx8qm-lpuart"; 426 reg = <0x0 0x5a080000 0x0 0x1000>; 427 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; 428 clocks = <&clk IMX8QM_UART2_CLK>, 429 <&clk IMX8QM_UART2_IPG_CLK>; 430 clock-names = "per", "ipg"; 431 assigned-clocks = <&clk IMX8QM_UART2_CLK>; 432 assigned-clock-rates = <80000000>; 433 power-domains = <&pd_dma_lpuart2>; 434 status = "disabled"; 435 }; 436 437 lpuart3: serial@5a090000 { 438 compatible = "fsl,imx8qm-lpuart"; 439 reg = <0x0 0x5a090000 0x0 0x1000>; 440 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>; 441 clocks = <&clk IMX8QM_UART3_CLK>, 442 <&clk IMX8QM_UART3_IPG_CLK>; 443 clock-names = "per", "ipg"; 444 assigned-clocks = <&clk IMX8QM_UART3_CLK>; 445 assigned-clock-rates = <80000000>; 446 power-domains = <&pd_dma_lpuart3>; 447 status = "disabled"; 448 }; 449 450 lpuart4: serial@5a0a0000 { 451 compatible = "fsl,imx8qm-lpuart"; 452 reg = <0x0 0x5a0a0000 0x0 0x1000>; 453 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 454 clocks = <&clk IMX8QM_UART4_CLK>, 455 <&clk IMX8QM_UART4_IPG_CLK>; 456 clock-names = "per", "ipg"; 457 assigned-clocks = <&clk IMX8QM_UART4_CLK>; 458 assigned-clock-rates = <80000000>; 459 power-domains = <&pd_dma_lpuart4>; 460 status = "disabled"; 461 }; 462 463 usdhc1: usdhc@5b010000 { 464 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; 465 interrupt-parent = <&gic>; 466 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 467 reg = <0x0 0x5b010000 0x0 0x10000>; 468 clocks = <&clk IMX8QM_SDHC0_IPG_CLK>, 469 <&clk IMX8QM_SDHC0_CLK>, 470 <&clk IMX8QM_CLK_DUMMY>; 471 clock-names = "ipg", "per", "ahb"; 472 assigned-clocks = <&clk IMX8QM_SDHC0_DIV>; 473 assigned-clock-rates = <400000000>; 474 power-domains = <&pd_conn_sdch0>; 475 fsl,tuning-start-tap = <20>; 476 fsl,tuning-step= <2>; 477 status = "disabled"; 478 }; 479 480 usdhc2: usdhc@5b020000 { 481 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; 482 interrupt-parent = <&gic>; 483 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 484 reg = <0x0 0x5b020000 0x0 0x10000>; 485 clocks = <&clk IMX8QM_SDHC1_IPG_CLK>, 486 <&clk IMX8QM_SDHC1_CLK>, 487 <&clk IMX8QM_CLK_DUMMY>; 488 clock-names = "ipg", "per", "ahb"; 489 assigned-clocks = <&clk IMX8QM_SDHC1_DIV>; 490 assigned-clock-rates = <200000000>; 491 power-domains = <&pd_conn_sdch1>; 492 fsl,tuning-start-tap = <20>; 493 fsl,tuning-step= <2>; 494 status = "disabled"; 495 }; 496 497 usdhc3: usdhc@5b030000 { 498 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; 499 interrupt-parent = <&gic>; 500 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 501 reg = <0x0 0x5b030000 0x0 0x10000>; 502 clocks = <&clk IMX8QM_SDHC2_IPG_CLK>, 503 <&clk IMX8QM_SDHC2_CLK>, 504 <&clk IMX8QM_CLK_DUMMY>; 505 clock-names = "ipg", "per", "ahb"; 506 assigned-clocks = <&clk IMX8QM_SDHC2_DIV>; 507 assigned-clock-rates = <200000000>; 508 power-domains = <&pd_conn_sdch2>; 509 status = "disabled"; 510 }; 511 512 fec1: ethernet@5b040000 { 513 compatible = "fsl,imx8qm-fec", "fsl,imx7d-fec"; 514 reg = <0x0 0x5b040000 0x0 0x10000>; 515 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 519 clocks = <&clk IMX8QM_ENET0_IPG_CLK>, 520 <&clk IMX8QM_ENET0_AHB_CLK>, 521 <&clk IMX8QM_ENET0_RGMII_TX_CLK>, 522 <&clk IMX8QM_ENET0_PTP_CLK>, 523 <&clk IMX8QM_ENET0_TX_CLK>; 524 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", 525 "enet_2x_txclk"; 526 assigned-clocks = <&clk IMX8QM_ENET0_ROOT_DIV>, 527 <&clk IMX8QM_ENET0_REF_DIV>; 528 assigned-clock-rates = <250000000>, <125000000>; 529 fsl,num-tx-queues=<3>; 530 fsl,num-rx-queues=<3>; 531 fsl,wakeup_irq = <0>; 532 power-domains = <&pd_conn_enet0>; 533 status = "disabled"; 534 }; 535 536 fec2: ethernet@5b050000 { 537 compatible = "fsl,imx8qm-fec", "fsl,imx7d-fec"; 538 reg = <0x0 0x5b050000 0x0 0x10000>; 539 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&clk IMX8QM_ENET1_IPG_CLK>, 544 <&clk IMX8QM_ENET1_AHB_CLK>, 545 <&clk IMX8QM_ENET1_RGMII_TX_CLK>, 546 <&clk IMX8QM_ENET1_PTP_CLK>, 547 <&clk IMX8QM_ENET1_TX_CLK>; 548 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", 549 "enet_2x_txclk"; 550 assigned-clocks = <&clk IMX8QM_ENET1_ROOT_DIV>, 551 <&clk IMX8QM_ENET1_REF_DIV>; 552 assigned-clock-rates = <250000000>, <125000000>; 553 fsl,num-tx-queues=<3>; 554 fsl,num-rx-queues=<3>; 555 fsl,wakeup_irq = <0>; 556 power-domains = <&pd_conn_enet1>; 557 status = "disabled"; 558 }; 559}; 560 561&A53_0 { 562 clocks = <&clk IMX8QM_A53_DIV>; 563}; 564