1// SPDX-License-Identifier: GPL-2.0+ OR X11 2/* 3 * NXP LS1028A-QDS device tree fragment for RCW 9999 4 * 5 * Copyright 2019-2021 NXP Semiconductors 6 */ 7 8/* 9 * This setup is using SCH-24801 cards with VSC8234 quad SGMII PHY. 10 * LS1028A QDS boards with lane B rework require two cards for the 4 switch 11 * ports, QDS boards without the lane B rework only require one card. 12 * 13 * Switch ports are routed as follows: 14 * Port 0 goes to 1st port of VSC8234 quad card in slot 1, 15 * Port 1: 16 * - if the QDS has had lane B rework, it is 1st port in slot 2, 17 * - otherwise it is 2nd port in slot 1. 18 * Port 2: 19 * - if DIP SW5[1] = 0 it is 3rd port in slot 1, 20 * - otherwise it is 1st port in slot 3. 21 * Port 3: 22 * - if DIP SW5[2-3] = 00b it is 4th port in slot 1, 23 * - if DIP SW5[2-3] = 01b it is 2nd port in slot 3, 24 * - if DIP SW5[2-3] = 11b it is 1st port in slot 4. 25 * 26 * The following DTS assumes QDS lane B rework and DIP SW5[1-3] = 000b. Two 27 * SCH-24801 cards are required in slots 1 and 2. 28 */ 29&slot1 { 30 #include "fsl-sch-24801.dtsi" 31}; 32 33&slot2 { 34 #include "fsl-sch-24801.dtsi" 35}; 36 37&mscc_felix { 38 status = "okay"; 39}; 40 41&mscc_felix_port0 { 42 status = "okay"; 43 phy-mode = "sgmii"; 44 phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>; 45}; 46 47&mscc_felix_port1 { 48 status = "okay"; 49 phy-mode = "sgmii"; 50 phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@1c}>; 51}; 52 53&mscc_felix_port2 { 54 status = "okay"; 55 phy-mode = "sgmii"; 56 phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>; 57}; 58 59&mscc_felix_port3 { 60 status = "okay"; 61 phy-mode = "sgmii"; 62 phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>; 63}; 64