1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2//
3// Copyright 2021 Ronetix GmbH
4
5/dts-v1/;
6
7#include "imx7d.dtsi"
8
9/ {
10	model = "Ronetix iMX7-CM Board";
11	compatible = "ronetix,imx7-cm", "fsl,imx7d";
12
13	chosen {
14		stdout-path = &uart1;
15	};
16
17	/* DRAM size runtime extracted from the DDRC registers */
18	memory@80000000 {
19		device_type = "memory";
20		reg = <0x80000000 0>;
21	};
22
23	leds {
24		compatible = "gpio-leds";
25		pinctrl-names = "default";
26		pinctrl-0 = <&pinctrl_gpio_leds>;
27
28		led {
29			label = "gpio-led";
30			gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
31		};
32	};
33
34	reg_sd1_vmmc: regulator-sd1-vmmc {
35		compatible = "regulator-fixed";
36		regulator-name = "VDD_SD1";
37		regulator-min-microvolt = <3300000>;
38		regulator-max-microvolt = <3300000>;
39		gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
40		startup-delay-us = <200000>;
41		off-on-delay-us = <20000>;
42		enable-active-high;
43	};
44
45	reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
46		pinctrl-names = "default";
47		pinctrl-0 = <&pinctrl_usbotg1_pwr>;
48		compatible = "regulator-fixed";
49		regulator-name = "usb_otg1_vbus";
50		regulator-min-microvolt = <5000000>;
51		regulator-max-microvolt = <5000000>;
52		gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
53		enable-active-high;
54	};
55
56	reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
57		pinctrl-names = "default";
58		pinctrl-0 = <&pinctrl_usbotg2_pwr>;
59		compatible = "regulator-fixed";
60		regulator-name = "usb_otg2_vbus";
61		regulator-min-microvolt = <5000000>;
62		regulator-max-microvolt = <5000000>;
63		gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
64		enable-active-high;
65	};
66};
67
68&clks {
69	assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
70			  <&clks IMX7D_CLKO2_ROOT_DIV>;
71	assigned-clock-parents = <&clks IMX7D_CKIL>;
72	assigned-clock-rates = <0>, <32768>;
73};
74
75&fec1 {
76	pinctrl-names = "default";
77	pinctrl-0 = <&pinctrl_enet1>;
78	phy-mode = "rgmii-id";
79	phy-handle = <&ethphy0>;
80	fsl,magic-packet;
81	status = "okay";
82
83	mdio {
84		#address-cells = <1>;
85		#size-cells = <0>;
86
87		ethphy0: ethernet-phy@1 {
88			compatible = "ethernet-phy-ieee802.3-c22";
89			reg = <1>;
90			reset-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
91			reset-assert-us = <10000>;
92		};
93	};
94};
95
96&qspi1 {
97	pinctrl-names = "default";
98	pinctrl-0 = <&pinctrl_qspi1_1>;
99	status = "okay";
100	ddrsmp=<0>;
101
102	flash0: mx25l25645g@0 {
103		#address-cells = <1>;
104		#size-cells = <1>;
105		compatible = "jedec,spi-nor";
106		spi-max-frequency = <29000000>;
107		reg = <0>;
108	};
109};
110
111&i2c1 {
112	clock-frequency = <100000>;
113	pinctrl-names = "default";
114	pinctrl-0 = <&pinctrl_i2c1>;
115	status = "okay";
116
117	pmic@8 {
118		compatible = "fsl,pfuze3000";
119		reg = <0x08>;
120
121		regulators {
122			sw1a_reg: sw1a {
123				regulator-min-microvolt = <700000>;
124				regulator-max-microvolt = <3300000>;
125				regulator-boot-on;
126				regulator-always-on;
127				regulator-ramp-delay = <6250>;
128			};
129			/* use sw1c_reg to align with pfuze100/pfuze200 */
130			sw1c_reg: sw1b {
131				regulator-min-microvolt = <700000>;
132				regulator-max-microvolt = <1475000>;
133				regulator-boot-on;
134				regulator-always-on;
135				regulator-ramp-delay = <6250>;
136			};
137
138			sw2_reg: sw2 {
139				regulator-min-microvolt = <1800000>;
140				regulator-max-microvolt = <1850000>;
141				regulator-boot-on;
142				regulator-always-on;
143			};
144
145			sw3a_reg: sw3 {
146				regulator-min-microvolt = <900000>;
147				regulator-max-microvolt = <1650000>;
148				regulator-boot-on;
149				regulator-always-on;
150			};
151
152			swbst_reg: swbst {
153				regulator-min-microvolt = <5000000>;
154				regulator-max-microvolt = <5150000>;
155			};
156
157			snvs_reg: vsnvs {
158				regulator-min-microvolt = <1000000>;
159				regulator-max-microvolt = <3000000>;
160				regulator-boot-on;
161				regulator-always-on;
162			};
163
164			vref_reg: vrefddr {
165				regulator-boot-on;
166				regulator-always-on;
167			};
168
169			vgen1_reg: vldo1 {
170				regulator-min-microvolt = <1800000>;
171				regulator-max-microvolt = <3300000>;
172				regulator-always-on;
173			};
174
175			vgen2_reg: vldo2 {
176				regulator-min-microvolt = <800000>;
177				regulator-max-microvolt = <1550000>;
178			};
179
180			vgen3_reg: vccsd {
181				regulator-min-microvolt = <2850000>;
182				regulator-max-microvolt = <3300000>;
183				regulator-always-on;
184			};
185
186			vgen4_reg: v33 {
187				regulator-min-microvolt = <2850000>;
188				regulator-max-microvolt = <3300000>;
189				regulator-always-on;
190			};
191
192			vgen5_reg: vldo3 {
193				regulator-min-microvolt = <1800000>;
194				regulator-max-microvolt = <3300000>;
195				regulator-always-on;
196			};
197
198			vgen6_reg: vldo4 {
199				regulator-min-microvolt = <1800000>;
200				regulator-max-microvolt = <3300000>;
201				regulator-always-on;
202			};
203		};
204	};
205};
206
207&i2c2 {
208	pinctrl-names = "default";
209	pinctrl-0 = <&pinctrl_i2c2>;
210	status = "okay";
211};
212
213&uart1 { /* console */
214	pinctrl-names = "default";
215	pinctrl-0 = <&pinctrl_uart1>;
216	status = "okay";
217};
218
219&usbotg1 {
220	vbus-supply = <&reg_usb_otg1_vbus>;
221	status = "okay";
222};
223
224&usbotg2 {
225	vbus-supply = <&reg_usb_otg2_vbus>;
226	dr_mode = "host";
227	status = "okay";
228};
229
230/* SD card */
231&usdhc1 {
232	pinctrl-names = "default", "state_100mhz", "state_200mhz";
233	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
234	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
235	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
236	cd-gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
237	bus-width = <4>;
238	tuning-step = <2>;
239	vmmc-supply = <&reg_sd1_vmmc>;
240	wakeup-source;
241	no-1-8-v;
242	keep-power-in-suspend;
243	status = "okay";
244};
245
246/* eMMC */
247&usdhc3 {
248	pinctrl-names = "default", "state_100mhz", "state_200mhz";
249	pinctrl-0 = <&pinctrl_usdhc3>;
250	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
251	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
252	assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
253	assigned-clock-rates = <400000000>;
254	bus-width = <8>;
255	no-1-8-v;
256	fsl,tuning-step = <2>;
257	non-removable;
258	status = "okay";
259};
260
261&wdog1 {
262	pinctrl-names = "default";
263	pinctrl-0 = <&pinctrl_wdog>;
264	fsl,ext-reset-output;
265	status = "okay";
266};
267
268&iomuxc {
269	pinctrl_i2c1: i2c1grp {
270		fsl,pins = <
271			MX7D_PAD_I2C1_SCL__I2C1_SCL	0x4000007f
272			MX7D_PAD_I2C1_SDA__I2C1_SDA	0x4000007f
273		>;
274	};
275
276	pinctrl_i2c2: i2c2grp {
277		fsl,pins = <
278			MX7D_PAD_I2C2_SCL__I2C2_SCL	0x4000007f
279			MX7D_PAD_I2C2_SDA__I2C2_SDA	0x4000007f
280		>;
281	};
282
283	pinctrl_enet1: enet1grp {
284		fsl,pins = <
285			MX7D_PAD_GPIO1_IO10__ENET1_MDIO				0x3
286			MX7D_PAD_GPIO1_IO11__ENET1_MDC				0x3
287			MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC	0x1
288			MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0	0x1
289			MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1	0x1
290			MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2	0x1
291			MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3	0x1
292			MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL	0x1
293			MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC	0x1
294			MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0	0x1
295			MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1	0x1
296			MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2	0x1
297			MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3	0x1
298			MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL	0x1
299			MX7D_PAD_EPDC_DATA04__GPIO2_IO4	0x14	/* ETH_RESET */
300		>;
301	};
302
303	pinctrl_gpio_leds: gpioledsgrp {
304		fsl,pins = <
305			MX7D_PAD_EPDC_DATA07__GPIO2_IO7		0x14
306		>;
307	};
308
309	pinctrl_uart1: uart1grp {
310		fsl,pins = <
311			MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX	0x59
312			MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX	0x59
313		>;
314	};
315
316	pinctrl_usbotg1_pwr: usbotg_pwr {
317		fsl,pins = <
318			MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5	0x14
319		>;
320	};
321
322	pinctrl_usbotg2_pwr: usbotg_pwr {
323		fsl,pins = <
324			MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7	0x14
325		>;
326	};
327
328	pinctrl_usdhc1_gpio: usdhc1_gpiogrp {
329		fsl,pins = <
330			MX7D_PAD_SD1_CD_B__GPIO5_IO0		0x15 /* CD */
331			MX7D_PAD_SD1_RESET_B__GPIO5_IO2		0x59 /* Vmmc */
332			MX7D_PAD_GPIO1_IO08__SD1_VSELECT	0x59 /* VSELECT */
333		>;
334	};
335
336	pinctrl_usdhc1: usdhc1grp {
337		fsl,pins = <
338			MX7D_PAD_SD1_CMD__SD1_CMD			0x59
339			MX7D_PAD_SD1_CLK__SD1_CLK			0x19
340			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x59
341			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x59
342			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x59
343			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x59
344		>;
345	};
346
347	pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
348		fsl,pins = <
349			MX7D_PAD_SD1_CMD__SD1_CMD			0x5a
350			MX7D_PAD_SD1_CLK__SD1_CLK			0x1a
351			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5a
352			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5a
353			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5a
354			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5a
355		>;
356	};
357
358	pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
359		fsl,pins = <
360			MX7D_PAD_SD1_CMD__SD1_CMD			0x5b
361			MX7D_PAD_SD1_CLK__SD1_CLK			0x1b
362			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5b
363			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5b
364			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5b
365			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5b
366		>;
367	};
368
369	pinctrl_usdhc3: usdhc3grp {
370		fsl,pins = <
371			MX7D_PAD_SD3_CMD__SD3_CMD		0x59
372			MX7D_PAD_SD3_CLK__SD3_CLK		0x19
373			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x59
374			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x59
375			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x59
376			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x59
377			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x59
378			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x59
379			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x59
380			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x59
381		>;
382	};
383
384	pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
385		fsl,pins = <
386			MX7D_PAD_SD3_CMD__SD3_CMD		0x5a
387			MX7D_PAD_SD3_CLK__SD3_CLK		0x1a
388			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x5a
389			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x5a
390			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x5a
391			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x5a
392			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x5a
393			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x5a
394			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x5a
395			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x5a
396		>;
397	};
398
399	pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
400		fsl,pins = <
401			MX7D_PAD_SD3_CMD__SD3_CMD		0x5b
402			MX7D_PAD_SD3_CLK__SD3_CLK		0x1b
403			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x5b
404			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x5b
405			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x5b
406			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x5b
407			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x5b
408			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x5b
409			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x5b
410			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x5b
411		>;
412	};
413
414	pinctrl_qspi1_1: qspi1grp_1 {
415			fsl,pins = <
416				MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 	0x51
417				MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 	0x51
418				MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 	0x51
419				MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 	0x51
420				MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 	0x51
421				MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 	0x51
422			>;
423		};
424};
425
426&iomuxc_lpsr {
427	pinctrl_wdog: wdoggrp {
428		fsl,pins = <
429			MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B	0x74
430		>;
431	};
432};
433