1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6/dts-v1/; 7 8#include "k3-j721e.dtsi" 9 10/ { 11 memory@80000000 { 12 device_type = "memory"; 13 /* 4G RAM */ 14 reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 15 <0x00000008 0x80000000 0x00000000 0x80000000>; 16 }; 17 18 reserved_memory: reserved-memory { 19 #address-cells = <2>; 20 #size-cells = <2>; 21 ranges; 22 23 secure_ddr: optee@9e800000 { 24 reg = <0x00 0x9e800000 0x00 0x01800000>; 25 alignment = <0x1000>; 26 no-map; 27 }; 28 29 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 30 compatible = "shared-dma-pool"; 31 reg = <0x00 0xa0000000 0x00 0x100000>; 32 no-map; 33 }; 34 35 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { 36 compatible = "shared-dma-pool"; 37 reg = <0x00 0xa0100000 0x00 0xf00000>; 38 no-map; 39 }; 40 41 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 42 compatible = "shared-dma-pool"; 43 reg = <0x00 0xa1000000 0x00 0x100000>; 44 no-map; 45 }; 46 47 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { 48 compatible = "shared-dma-pool"; 49 reg = <0x00 0xa1100000 0x00 0xf00000>; 50 no-map; 51 }; 52 53 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { 54 compatible = "shared-dma-pool"; 55 reg = <0x00 0xa2000000 0x00 0x100000>; 56 no-map; 57 }; 58 59 main_r5fss0_core0_memory_region: r5f-memory@a2100000 { 60 compatible = "shared-dma-pool"; 61 reg = <0x00 0xa2100000 0x00 0xf00000>; 62 no-map; 63 }; 64 65 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { 66 compatible = "shared-dma-pool"; 67 reg = <0x00 0xa3000000 0x00 0x100000>; 68 no-map; 69 }; 70 71 main_r5fss0_core1_memory_region: r5f-memory@a3100000 { 72 compatible = "shared-dma-pool"; 73 reg = <0x00 0xa3100000 0x00 0xf00000>; 74 no-map; 75 }; 76 77 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { 78 compatible = "shared-dma-pool"; 79 reg = <0x00 0xa4000000 0x00 0x100000>; 80 no-map; 81 }; 82 83 main_r5fss1_core0_memory_region: r5f-memory@a4100000 { 84 compatible = "shared-dma-pool"; 85 reg = <0x00 0xa4100000 0x00 0xf00000>; 86 no-map; 87 }; 88 89 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { 90 compatible = "shared-dma-pool"; 91 reg = <0x00 0xa5000000 0x00 0x100000>; 92 no-map; 93 }; 94 95 main_r5fss1_core1_memory_region: r5f-memory@a5100000 { 96 compatible = "shared-dma-pool"; 97 reg = <0x00 0xa5100000 0x00 0xf00000>; 98 no-map; 99 }; 100 101 c66_1_dma_memory_region: c66-dma-memory@a6000000 { 102 compatible = "shared-dma-pool"; 103 reg = <0x00 0xa6000000 0x00 0x100000>; 104 no-map; 105 }; 106 107 c66_0_memory_region: c66-memory@a6100000 { 108 compatible = "shared-dma-pool"; 109 reg = <0x00 0xa6100000 0x00 0xf00000>; 110 no-map; 111 }; 112 113 c66_0_dma_memory_region: c66-dma-memory@a7000000 { 114 compatible = "shared-dma-pool"; 115 reg = <0x00 0xa7000000 0x00 0x100000>; 116 no-map; 117 }; 118 119 c66_1_memory_region: c66-memory@a7100000 { 120 compatible = "shared-dma-pool"; 121 reg = <0x00 0xa7100000 0x00 0xf00000>; 122 no-map; 123 }; 124 125 c71_0_dma_memory_region: c71-dma-memory@a8000000 { 126 compatible = "shared-dma-pool"; 127 reg = <0x00 0xa8000000 0x00 0x100000>; 128 no-map; 129 }; 130 131 c71_0_memory_region: c71-memory@a8100000 { 132 compatible = "shared-dma-pool"; 133 reg = <0x00 0xa8100000 0x00 0xf00000>; 134 no-map; 135 }; 136 137 rtos_ipc_memory_region: ipc-memories@aa000000 { 138 reg = <0x00 0xaa000000 0x00 0x01c00000>; 139 alignment = <0x1000>; 140 no-map; 141 }; 142 }; 143}; 144 145&wkup_pmx0 { 146 wkup_i2c0_pins_default: wkup-i2c0-pins-default { 147 pinctrl-single,pins = < 148 J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ 149 J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ 150 >; 151 }; 152 153 mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default { 154 pinctrl-single,pins = < 155 J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */ 156 J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */ 157 J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */ 158 J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */ 159 J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */ 160 J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */ 161 J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */ 162 J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */ 163 J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */ 164 J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */ 165 J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */ 166 J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */ 167 J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */ 168 J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */ 169 >; 170 }; 171 172 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { 173 pinctrl-single,pins = < 174 J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ 175 J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */ 176 J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */ 177 J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */ 178 J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */ 179 J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */ 180 J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */ 181 J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */ 182 J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */ 183 J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */ 184 J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ 185 >; 186 }; 187}; 188 189&hbmc { 190 status = "disabled"; 191 pinctrl-names = "default"; 192 pinctrl-0 = <&mcu_fss0_hpb0_pins_default>; 193 ranges = <0x0 0x0 0x5 0x0 0x4000000>, /* 64MB Flash on CS0 */ 194 <0x1 0x0 0x5 0x4000000 0x800000>; /* 8MB RAM on CS1 */ 195 196 flash@0,0 { 197 compatible = "cypress,hyperflash", "cfi-flash"; 198 reg = <0x0 0x0 0x4000000>; 199 }; 200}; 201 202&ospi0 { 203 pinctrl-names = "default"; 204 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; 205 206 flash@0{ 207 compatible = "jedec,spi-nor"; 208 reg = <0x0>; 209 spi-tx-bus-width = <1>; 210 spi-rx-bus-width = <8>; 211 spi-max-frequency = <40000000>; 212 cdns,tshsl-ns = <60>; 213 cdns,tsd2d-ns = <60>; 214 cdns,tchsh-ns = <60>; 215 cdns,tslch-ns = <60>; 216 cdns,read-delay = <0>; 217 #address-cells = <1>; 218 #size-cells = <1>; 219 }; 220}; 221 222&mailbox0_cluster0 { 223 interrupts = <436>; 224 225 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 226 ti,mbox-rx = <0 0 0>; 227 ti,mbox-tx = <1 0 0>; 228 }; 229 230 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 231 ti,mbox-rx = <2 0 0>; 232 ti,mbox-tx = <3 0 0>; 233 }; 234}; 235 236&mailbox0_cluster1 { 237 interrupts = <432>; 238 239 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 240 ti,mbox-rx = <0 0 0>; 241 ti,mbox-tx = <1 0 0>; 242 }; 243 244 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 245 ti,mbox-rx = <2 0 0>; 246 ti,mbox-tx = <3 0 0>; 247 }; 248}; 249 250&mailbox0_cluster2 { 251 interrupts = <428>; 252 253 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 254 ti,mbox-rx = <0 0 0>; 255 ti,mbox-tx = <1 0 0>; 256 }; 257 258 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 259 ti,mbox-rx = <2 0 0>; 260 ti,mbox-tx = <3 0 0>; 261 }; 262}; 263 264&mailbox0_cluster3 { 265 interrupts = <424>; 266 267 mbox_c66_0: mbox-c66-0 { 268 ti,mbox-rx = <0 0 0>; 269 ti,mbox-tx = <1 0 0>; 270 }; 271 272 mbox_c66_1: mbox-c66-1 { 273 ti,mbox-rx = <2 0 0>; 274 ti,mbox-tx = <3 0 0>; 275 }; 276}; 277 278&mailbox0_cluster4 { 279 interrupts = <420>; 280 281 mbox_c71_0: mbox-c71-0 { 282 ti,mbox-rx = <0 0 0>; 283 ti,mbox-tx = <1 0 0>; 284 }; 285}; 286 287&mailbox0_cluster5 { 288 status = "disabled"; 289}; 290 291&mailbox0_cluster6 { 292 status = "disabled"; 293}; 294 295&mailbox0_cluster7 { 296 status = "disabled"; 297}; 298 299&mailbox0_cluster8 { 300 status = "disabled"; 301}; 302 303&mailbox0_cluster9 { 304 status = "disabled"; 305}; 306 307&mailbox0_cluster10 { 308 status = "disabled"; 309}; 310 311&mailbox0_cluster11 { 312 status = "disabled"; 313}; 314 315&mcu_r5fss0_core0 { 316 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; 317 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 318 <&mcu_r5fss0_core0_memory_region>; 319}; 320 321&mcu_r5fss0_core1 { 322 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; 323 memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 324 <&mcu_r5fss0_core1_memory_region>; 325}; 326 327&main_r5fss0_core0 { 328 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; 329 memory-region = <&main_r5fss0_core0_dma_memory_region>, 330 <&main_r5fss0_core0_memory_region>; 331}; 332 333&main_r5fss0_core1 { 334 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; 335 memory-region = <&main_r5fss0_core1_dma_memory_region>, 336 <&main_r5fss0_core1_memory_region>; 337}; 338 339&main_r5fss1_core0 { 340 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; 341 memory-region = <&main_r5fss1_core0_dma_memory_region>, 342 <&main_r5fss1_core0_memory_region>; 343}; 344 345&main_r5fss1_core1 { 346 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; 347 memory-region = <&main_r5fss1_core1_dma_memory_region>, 348 <&main_r5fss1_core1_memory_region>; 349}; 350 351&c66_0 { 352 mboxes = <&mailbox0_cluster3 &mbox_c66_0>; 353 memory-region = <&c66_0_dma_memory_region>, 354 <&c66_0_memory_region>; 355}; 356 357&c66_1 { 358 mboxes = <&mailbox0_cluster3 &mbox_c66_1>; 359 memory-region = <&c66_1_dma_memory_region>, 360 <&c66_1_memory_region>; 361}; 362 363&c71_0 { 364 mboxes = <&mailbox0_cluster4 &mbox_c71_0>; 365 memory-region = <&c71_0_dma_memory_region>, 366 <&c71_0_memory_region>; 367}; 368