1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
4 */
5
6#include "rk3368-u-boot.dtsi"
7
8/ {
9	chosen {
10		u-boot,spl-boot-order = &emmc;
11	};
12};
13
14&dmc {
15	u-boot,dm-pre-reloc;
16
17	/*
18	 * PX5-evb(2GB) need to use CBRD mode, or else the dram is not correct
19	 * See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for
20	 * details on the 'rockchip,memory-schedule' property and how it
21	 * affects the physical-address to device-address mapping.
22	 */
23	rockchip,memory-schedule = <DMC_MSCH_CBRD>;
24	rockchip,ddr-frequency = <800000000>;
25	rockchip,ddr-speed-bin = <DDR3_1600K>;
26
27	status = "okay";
28};
29
30&pinctrl {
31	u-boot,dm-pre-reloc;
32};
33
34&service_msch {
35	u-boot,dm-pre-reloc;
36};
37
38&dmc {
39	u-boot,dm-pre-reloc;
40	status = "okay";
41};
42
43&pmugrf {
44	u-boot,dm-pre-reloc;
45};
46
47&sgrf {
48	u-boot,dm-pre-reloc;
49};
50
51&cru {
52	u-boot,dm-pre-reloc;
53};
54
55&grf {
56	u-boot,dm-pre-reloc;
57};
58
59&uart4 {
60	u-boot,dm-pre-reloc;
61};
62
63&emmc {
64	/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
65	u-boot,spl-fifo-mode;
66	u-boot,dm-pre-reloc;
67};
68
69&timer0 {
70	u-boot,dm-pre-reloc;
71	clock-frequency = <24000000>;
72	status = "okay";
73};
74