1menu "RISC-V architecture" 2 depends on RISCV 3 4config SYS_ARCH 5 default "riscv" 6 7choice 8 prompt "Target select" 9 optional 10 11config TARGET_AX25_AE350 12 bool "Support ax25-ae350" 13 14config TARGET_MICROCHIP_ICICLE 15 bool "Support Microchip PolarFire-SoC Icicle Board" 16 17config TARGET_QEMU_VIRT 18 bool "Support QEMU Virt Board" 19 20config TARGET_SIFIVE_UNLEASHED 21 bool "Support SiFive Unleashed Board" 22 23config TARGET_SIFIVE_UNMATCHED 24 bool "Support SiFive Unmatched Board" 25 26config TARGET_SIPEED_MAIX 27 bool "Support Sipeed Maix Board" 28 29endchoice 30 31config SYS_ICACHE_OFF 32 bool "Do not enable icache" 33 default n 34 help 35 Do not enable instruction cache in U-Boot. 36 37config SPL_SYS_ICACHE_OFF 38 bool "Do not enable icache in SPL" 39 depends on SPL 40 default SYS_ICACHE_OFF 41 help 42 Do not enable instruction cache in SPL. 43 44config SYS_DCACHE_OFF 45 bool "Do not enable dcache" 46 default n 47 help 48 Do not enable data cache in U-Boot. 49 50config SPL_SYS_DCACHE_OFF 51 bool "Do not enable dcache in SPL" 52 depends on SPL 53 default SYS_DCACHE_OFF 54 help 55 Do not enable data cache in SPL. 56 57# board-specific options below 58source "board/AndesTech/ax25-ae350/Kconfig" 59source "board/emulation/qemu-riscv/Kconfig" 60source "board/microchip/mpfs_icicle/Kconfig" 61source "board/sifive/unleashed/Kconfig" 62source "board/sifive/unmatched/Kconfig" 63source "board/sipeed/maix/Kconfig" 64 65# platform-specific options below 66source "arch/riscv/cpu/ax25/Kconfig" 67source "arch/riscv/cpu/fu540/Kconfig" 68source "arch/riscv/cpu/fu740/Kconfig" 69source "arch/riscv/cpu/generic/Kconfig" 70 71# architecture-specific options below 72 73choice 74 prompt "Base ISA" 75 default ARCH_RV32I 76 77config ARCH_RV32I 78 bool "RV32I" 79 select 32BIT 80 help 81 Choose this option to target the RV32I base integer instruction set. 82 83config ARCH_RV64I 84 bool "RV64I" 85 select 64BIT 86 select PHYS_64BIT 87 help 88 Choose this option to target the RV64I base integer instruction set. 89 90endchoice 91 92choice 93 prompt "Code Model" 94 default CMODEL_MEDLOW 95 96config CMODEL_MEDLOW 97 bool "medium low code model" 98 help 99 U-Boot and its statically defined symbols must lie within a single 2 GiB 100 address range and must lie between absolute addresses -2 GiB and +2 GiB. 101 102config CMODEL_MEDANY 103 bool "medium any code model" 104 help 105 U-Boot and its statically defined symbols must be within any single 2 GiB 106 address range. 107 108endchoice 109 110choice 111 prompt "Run Mode" 112 default RISCV_MMODE 113 114config RISCV_MMODE 115 bool "Machine" 116 help 117 Choose this option to build U-Boot for RISC-V M-Mode. 118 119config RISCV_SMODE 120 bool "Supervisor" 121 help 122 Choose this option to build U-Boot for RISC-V S-Mode. 123 124endchoice 125 126choice 127 prompt "SPL Run Mode" 128 default SPL_RISCV_MMODE 129 depends on SPL 130 131config SPL_RISCV_MMODE 132 bool "Machine" 133 help 134 Choose this option to build U-Boot SPL for RISC-V M-Mode. 135 136config SPL_RISCV_SMODE 137 bool "Supervisor" 138 help 139 Choose this option to build U-Boot SPL for RISC-V S-Mode. 140 141endchoice 142 143config RISCV_ISA_C 144 bool "Emit compressed instructions" 145 default y 146 help 147 Adds "C" to the ISA subsets that the toolchain is allowed to emit 148 when building U-Boot, which results in compressed instructions in the 149 U-Boot binary. 150 151config RISCV_ISA_A 152 def_bool y 153 154config 32BIT 155 bool 156 157config 64BIT 158 bool 159 160config DMA_ADDR_T_64BIT 161 bool 162 default y if 64BIT 163 164config SIFIVE_CLINT 165 bool 166 depends on RISCV_MMODE 167 help 168 The SiFive CLINT block holds memory-mapped control and status registers 169 associated with software and timer interrupts. 170 171config SPL_SIFIVE_CLINT 172 bool 173 depends on SPL_RISCV_MMODE 174 help 175 The SiFive CLINT block holds memory-mapped control and status registers 176 associated with software and timer interrupts. 177 178config ANDES_PLIC 179 bool 180 depends on RISCV_MMODE || SPL_RISCV_MMODE 181 select REGMAP 182 select SYSCON 183 select SPL_REGMAP if SPL 184 select SPL_SYSCON if SPL 185 help 186 The Andes PLIC block holds memory-mapped claim and pending registers 187 associated with software interrupt. 188 189config SYS_MALLOC_F_LEN 190 default 0x1000 191 192config SMP 193 bool "Symmetric Multi-Processing" 194 depends on SBI_V01 || !RISCV_SMODE 195 help 196 This enables support for systems with more than one CPU. If 197 you say N here, U-Boot will run on single and multiprocessor 198 machines, but will use only one CPU of a multiprocessor 199 machine. If you say Y here, U-Boot will run on many, but not 200 all, single processor machines. 201 202config SPL_SMP 203 bool "Symmetric Multi-Processing in SPL" 204 depends on SPL && SPL_RISCV_MMODE 205 default y 206 help 207 This enables support for systems with more than one CPU in SPL. 208 If you say N here, U-Boot SPL will run on single and multiprocessor 209 machines, but will use only one CPU of a multiprocessor 210 machine. If you say Y here, U-Boot SPL will run on many, but not 211 all, single processor machines. 212 213config NR_CPUS 214 int "Maximum number of CPUs (2-32)" 215 range 2 32 216 depends on SMP || SPL_SMP 217 default 8 218 help 219 On multiprocessor machines, U-Boot sets up a stack for each CPU. 220 Stack memory is pre-allocated. U-Boot must therefore know the 221 maximum number of CPUs that may be present. 222 223config SBI 224 bool 225 default y if RISCV_SMODE || SPL_RISCV_SMODE 226 227choice 228 prompt "SBI support" 229 default SBI_V02 230 231config SBI_V01 232 bool "SBI v0.1 support" 233 depends on SBI 234 help 235 This config allows kernel to use SBI v0.1 APIs. This will be 236 deprecated in future once legacy M-mode software are no longer in use. 237 238config SBI_V02 239 bool "SBI v0.2 support" 240 depends on SBI 241 help 242 This config allows kernel to use SBI v0.2 APIs. SBI v0.2 is more 243 scalable and extendable to handle future needs for RISC-V supervisor 244 interfaces. For example, with SBI v0.2 HSM extension, only a single 245 hart need to boot and enter operating system. The booting hart can 246 bring up secondary harts one by one afterwards. 247 248 Choose this option if OpenSBI v0.7 or above release is used together 249 with U-Boot. 250 251endchoice 252 253config SBI_IPI 254 bool 255 depends on SBI 256 default y if RISCV_SMODE || SPL_RISCV_SMODE 257 depends on SMP 258 259config XIP 260 bool "XIP mode" 261 help 262 XIP (eXecute In Place) is a method for executing code directly 263 from a NOR flash memory without copying the code to ram. 264 Say yes here if U-Boot boots from flash directly. 265 266config SHOW_REGS 267 bool "Show registers on unhandled exception" 268 269config RISCV_PRIV_1_9 270 bool "Use version 1.9 of the RISC-V priviledged specification" 271 help 272 Older versions of the RISC-V priviledged specification had 273 separate counter enable CSRs for each privilege mode. Writing 274 to the unified mcounteren CSR on a processor implementing the 275 old specification will result in an illegal instruction 276 exception. In addition to counter CSR changes, the way virtual 277 memory is configured was also changed. 278 279config STACK_SIZE_SHIFT 280 int 281 default 14 282 283config OF_BOARD_FIXUP 284 default y if OF_SEPARATE && RISCV_SMODE 285 286menu "Use assembly optimized implementation of memory routines" 287 288config USE_ARCH_MEMCPY 289 bool "Use an assembly optimized implementation of memcpy" 290 default y 291 help 292 Enable the generation of an optimized version of memcpy. 293 Such an implementation may be faster under some conditions 294 but may increase the binary size. 295 296config SPL_USE_ARCH_MEMCPY 297 bool "Use an assembly optimized implementation of memcpy for SPL" 298 default y if USE_ARCH_MEMCPY 299 depends on SPL 300 help 301 Enable the generation of an optimized version of memcpy. 302 Such an implementation may be faster under some conditions 303 but may increase the binary size. 304 305config TPL_USE_ARCH_MEMCPY 306 bool "Use an assembly optimized implementation of memcpy for TPL" 307 default y if USE_ARCH_MEMCPY 308 depends on TPL 309 help 310 Enable the generation of an optimized version of memcpy. 311 Such an implementation may be faster under some conditions 312 but may increase the binary size. 313 314config USE_ARCH_MEMMOVE 315 bool "Use an assembly optimized implementation of memmove" 316 default y 317 help 318 Enable the generation of an optimized version of memmove. 319 Such an implementation may be faster under some conditions 320 but may increase the binary size. 321 322config SPL_USE_ARCH_MEMMOVE 323 bool "Use an assembly optimized implementation of memmove for SPL" 324 default y if USE_ARCH_MEMCPY 325 depends on SPL 326 help 327 Enable the generation of an optimized version of memmove. 328 Such an implementation may be faster under some conditions 329 but may increase the binary size. 330 331config TPL_USE_ARCH_MEMMOVE 332 bool "Use an assembly optimized implementation of memmove for TPL" 333 default y if USE_ARCH_MEMCPY 334 depends on TPL 335 help 336 Enable the generation of an optimized version of memmove. 337 Such an implementation may be faster under some conditions 338 but may increase the binary size. 339 340config USE_ARCH_MEMSET 341 bool "Use an assembly optimized implementation of memset" 342 default y 343 help 344 Enable the generation of an optimized version of memset. 345 Such an implementation may be faster under some conditions 346 but may increase the binary size. 347 348config SPL_USE_ARCH_MEMSET 349 bool "Use an assembly optimized implementation of memset for SPL" 350 default y if USE_ARCH_MEMSET 351 depends on SPL 352 help 353 Enable the generation of an optimized version of memset. 354 Such an implementation may be faster under some conditions 355 but may increase the binary size. 356 357config TPL_USE_ARCH_MEMSET 358 bool "Use an assembly optimized implementation of memset for TPL" 359 default y if USE_ARCH_MEMSET 360 depends on TPL 361 help 362 Enable the generation of an optimized version of memset. 363 Such an implementation may be faster under some conditions 364 but may increase the binary size. 365 366endmenu 367 368endmenu 369