1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
4 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
5 */
6
7 #include <common.h>
8 #include <clk.h>
9 #include <cpu_func.h>
10 #include <dm.h>
11 #include <errno.h>
12 #include <generic-phy.h>
13 #include <log.h>
14 #include <malloc.h>
15 #include <memalign.h>
16 #include <phys2bus.h>
17 #include <usb.h>
18 #include <usbroothubdes.h>
19 #include <wait_bit.h>
20 #include <asm/cache.h>
21 #include <asm/io.h>
22 #include <dm/device_compat.h>
23 #include <linux/delay.h>
24 #include <linux/usb/otg.h>
25 #include <power/regulator.h>
26 #include <reset.h>
27
28 #include "dwc2.h"
29
30 /* Use only HC channel 0. */
31 #define DWC2_HC_CHANNEL 0
32
33 #define DWC2_STATUS_BUF_SIZE 64
34 #define DWC2_DATA_BUF_SIZE (CONFIG_USB_DWC2_BUFFER_SIZE * 1024)
35
36 #define MAX_DEVICE 16
37 #define MAX_ENDPOINT 16
38
39 struct dwc2_priv {
40 #if CONFIG_IS_ENABLED(DM_USB)
41 uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
42 uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
43 #ifdef CONFIG_DM_REGULATOR
44 struct udevice *vbus_supply;
45 #endif
46 struct phy phy;
47 struct clk_bulk clks;
48 #else
49 uint8_t *aligned_buffer;
50 uint8_t *status_buffer;
51 #endif
52 u8 in_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
53 u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
54 struct dwc2_core_regs *regs;
55 int root_hub_devnum;
56 bool ext_vbus;
57 /*
58 * The hnp/srp capability must be disabled if the platform
59 * does't support hnp/srp. Otherwise the force mode can't work.
60 */
61 bool hnp_srp_disable;
62 bool oc_disable;
63
64 struct reset_ctl_bulk resets;
65 };
66
67 #if !CONFIG_IS_ENABLED(DM_USB)
68 /* We need cacheline-aligned buffers for DMA transfers and dcache support */
69 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE,
70 ARCH_DMA_MINALIGN);
71 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE,
72 ARCH_DMA_MINALIGN);
73
74 static struct dwc2_priv local;
75 #endif
76
77 /*
78 * DWC2 IP interface
79 */
80
81 /*
82 * Initializes the FSLSPClkSel field of the HCFG register
83 * depending on the PHY type.
84 */
init_fslspclksel(struct dwc2_core_regs * regs)85 static void init_fslspclksel(struct dwc2_core_regs *regs)
86 {
87 uint32_t phyclk;
88
89 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
90 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
91 #else
92 /* High speed PHY running at full speed or high speed */
93 phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
94 #endif
95
96 #ifdef CONFIG_DWC2_ULPI_FS_LS
97 uint32_t hwcfg2 = readl(®s->ghwcfg2);
98 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
99 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
100 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
101 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
102
103 if (hval == 2 && fval == 1)
104 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
105 #endif
106
107 clrsetbits_le32(®s->host_regs.hcfg,
108 DWC2_HCFG_FSLSPCLKSEL_MASK,
109 phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
110 }
111
112 /*
113 * Flush a Tx FIFO.
114 *
115 * @param regs Programming view of DWC_otg controller.
116 * @param num Tx FIFO to flush.
117 */
dwc_otg_flush_tx_fifo(struct udevice * dev,struct dwc2_core_regs * regs,const int num)118 static void dwc_otg_flush_tx_fifo(struct udevice *dev,
119 struct dwc2_core_regs *regs, const int num)
120 {
121 int ret;
122
123 writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
124 ®s->grstctl);
125 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_TXFFLSH,
126 false, 1000, false);
127 if (ret)
128 dev_info(dev, "%s: Timeout!\n", __func__);
129
130 /* Wait for 3 PHY Clocks */
131 udelay(1);
132 }
133
134 /*
135 * Flush Rx FIFO.
136 *
137 * @param regs Programming view of DWC_otg controller.
138 */
dwc_otg_flush_rx_fifo(struct udevice * dev,struct dwc2_core_regs * regs)139 static void dwc_otg_flush_rx_fifo(struct udevice *dev,
140 struct dwc2_core_regs *regs)
141 {
142 int ret;
143
144 writel(DWC2_GRSTCTL_RXFFLSH, ®s->grstctl);
145 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_RXFFLSH,
146 false, 1000, false);
147 if (ret)
148 dev_info(dev, "%s: Timeout!\n", __func__);
149
150 /* Wait for 3 PHY Clocks */
151 udelay(1);
152 }
153
154 /*
155 * Do core a soft reset of the core. Be careful with this because it
156 * resets all the internal state machines of the core.
157 */
dwc_otg_core_reset(struct udevice * dev,struct dwc2_core_regs * regs)158 static void dwc_otg_core_reset(struct udevice *dev,
159 struct dwc2_core_regs *regs)
160 {
161 int ret;
162
163 /* Wait for AHB master IDLE state. */
164 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_AHBIDLE,
165 true, 1000, false);
166 if (ret)
167 dev_info(dev, "%s: Timeout!\n", __func__);
168
169 /* Core Soft Reset */
170 writel(DWC2_GRSTCTL_CSFTRST, ®s->grstctl);
171 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_CSFTRST,
172 false, 1000, false);
173 if (ret)
174 dev_info(dev, "%s: Timeout!\n", __func__);
175
176 /*
177 * Wait for core to come out of reset.
178 * NOTE: This long sleep is _very_ important, otherwise the core will
179 * not stay in host mode after a connector ID change!
180 */
181 mdelay(100);
182 }
183
184 #if CONFIG_IS_ENABLED(DM_USB) && defined(CONFIG_DM_REGULATOR)
dwc_vbus_supply_init(struct udevice * dev)185 static int dwc_vbus_supply_init(struct udevice *dev)
186 {
187 struct dwc2_priv *priv = dev_get_priv(dev);
188 int ret;
189
190 ret = device_get_supply_regulator(dev, "vbus-supply",
191 &priv->vbus_supply);
192 if (ret) {
193 debug("%s: No vbus supply\n", dev->name);
194 return 0;
195 }
196
197 ret = regulator_set_enable(priv->vbus_supply, true);
198 if (ret) {
199 dev_err(dev, "Error enabling vbus supply\n");
200 return ret;
201 }
202
203 return 0;
204 }
205
dwc_vbus_supply_exit(struct udevice * dev)206 static int dwc_vbus_supply_exit(struct udevice *dev)
207 {
208 struct dwc2_priv *priv = dev_get_priv(dev);
209 int ret;
210
211 if (priv->vbus_supply) {
212 ret = regulator_set_enable(priv->vbus_supply, false);
213 if (ret) {
214 dev_err(dev, "Error disabling vbus supply\n");
215 return ret;
216 }
217 }
218
219 return 0;
220 }
221 #else
dwc_vbus_supply_init(struct udevice * dev)222 static int dwc_vbus_supply_init(struct udevice *dev)
223 {
224 return 0;
225 }
226
227 #if CONFIG_IS_ENABLED(DM_USB)
dwc_vbus_supply_exit(struct udevice * dev)228 static int dwc_vbus_supply_exit(struct udevice *dev)
229 {
230 return 0;
231 }
232 #endif
233 #endif
234
235 /*
236 * This function initializes the DWC_otg controller registers for
237 * host mode.
238 *
239 * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
240 * request queues. Host channels are reset to ensure that they are ready for
241 * performing transfers.
242 *
243 * @param dev USB Device (NULL if driver model is not being used)
244 * @param regs Programming view of DWC_otg controller
245 *
246 */
dwc_otg_core_host_init(struct udevice * dev,struct dwc2_core_regs * regs)247 static void dwc_otg_core_host_init(struct udevice *dev,
248 struct dwc2_core_regs *regs)
249 {
250 uint32_t nptxfifosize = 0;
251 uint32_t ptxfifosize = 0;
252 uint32_t hprt0 = 0;
253 int i, ret, num_channels;
254
255 /* Restart the Phy Clock */
256 writel(0, ®s->pcgcctl);
257
258 /* Initialize Host Configuration Register */
259 init_fslspclksel(regs);
260 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL
261 setbits_le32(®s->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
262 #endif
263
264 /* Configure data FIFO sizes */
265 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
266 if (readl(®s->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
267 /* Rx FIFO */
268 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz);
269
270 /* Non-periodic Tx FIFO */
271 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
272 DWC2_FIFOSIZE_DEPTH_OFFSET;
273 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
274 DWC2_FIFOSIZE_STARTADDR_OFFSET;
275 writel(nptxfifosize, ®s->gnptxfsiz);
276
277 /* Periodic Tx FIFO */
278 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
279 DWC2_FIFOSIZE_DEPTH_OFFSET;
280 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
281 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
282 DWC2_FIFOSIZE_STARTADDR_OFFSET;
283 writel(ptxfifosize, ®s->hptxfsiz);
284 }
285 #endif
286
287 /* Clear Host Set HNP Enable in the OTG Control Register */
288 clrbits_le32(®s->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
289
290 /* Make sure the FIFOs are flushed. */
291 dwc_otg_flush_tx_fifo(dev, regs, 0x10); /* All Tx FIFOs */
292 dwc_otg_flush_rx_fifo(dev, regs);
293
294 /* Flush out any leftover queued requests. */
295 num_channels = readl(®s->ghwcfg2);
296 num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
297 num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
298 num_channels += 1;
299
300 for (i = 0; i < num_channels; i++)
301 clrsetbits_le32(®s->hc_regs[i].hcchar,
302 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
303 DWC2_HCCHAR_CHDIS);
304
305 /* Halt all channels to put them into a known state. */
306 for (i = 0; i < num_channels; i++) {
307 clrsetbits_le32(®s->hc_regs[i].hcchar,
308 DWC2_HCCHAR_EPDIR,
309 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
310 ret = wait_for_bit_le32(®s->hc_regs[i].hcchar,
311 DWC2_HCCHAR_CHEN, false, 1000, false);
312 if (ret)
313 dev_info(dev, "%s: Timeout!\n", __func__);
314 }
315
316 /* Turn on the vbus power. */
317 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
318 hprt0 = readl(®s->hprt0);
319 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
320 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
321 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
322 hprt0 |= DWC2_HPRT0_PRTPWR;
323 writel(hprt0, ®s->hprt0);
324 }
325 }
326
327 if (dev)
328 dwc_vbus_supply_init(dev);
329 }
330
331 /*
332 * This function initializes the DWC_otg controller registers and
333 * prepares the core for device mode or host mode operation.
334 *
335 * @param regs Programming view of the DWC_otg controller
336 */
dwc_otg_core_init(struct udevice * dev)337 static void dwc_otg_core_init(struct udevice *dev)
338 {
339 struct dwc2_priv *priv = dev_get_priv(dev);
340 struct dwc2_core_regs *regs = priv->regs;
341 uint32_t ahbcfg = 0;
342 uint32_t usbcfg = 0;
343 uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
344
345 /* Common Initialization */
346 usbcfg = readl(®s->gusbcfg);
347
348 /* Program the ULPI External VBUS bit if needed */
349 if (priv->ext_vbus) {
350 usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
351 if (!priv->oc_disable) {
352 usbcfg |= DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR |
353 DWC2_GUSBCFG_INDICATOR_PASSTHROUGH;
354 }
355 } else {
356 usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
357 }
358
359 /* Set external TS Dline pulsing */
360 #ifdef CONFIG_DWC2_TS_DLINE
361 usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
362 #else
363 usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
364 #endif
365 writel(usbcfg, ®s->gusbcfg);
366
367 /* Reset the Controller */
368 dwc_otg_core_reset(dev, regs);
369
370 /*
371 * This programming sequence needs to happen in FS mode before
372 * any other programming occurs
373 */
374 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
375 (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
376 /* If FS mode with FS PHY */
377 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_PHYSEL);
378
379 /* Reset after a PHY select */
380 dwc_otg_core_reset(dev, regs);
381
382 /*
383 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
384 * Also do this on HNP Dev/Host mode switches (done in dev_init
385 * and host_init).
386 */
387 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
388 init_fslspclksel(regs);
389
390 #ifdef CONFIG_DWC2_I2C_ENABLE
391 /* Program GUSBCFG.OtgUtmifsSel to I2C */
392 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
393
394 /* Program GI2CCTL.I2CEn */
395 clrsetbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN |
396 DWC2_GI2CCTL_I2CDEVADDR_MASK,
397 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
398 setbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN);
399 #endif
400
401 #else
402 /* High speed PHY. */
403
404 /*
405 * HS PHY parameters. These parameters are preserved during
406 * soft reset so only program the first time. Do a soft reset
407 * immediately after setting phyif.
408 */
409 usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
410 usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
411
412 if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */
413 #ifdef CONFIG_DWC2_PHY_ULPI_DDR
414 usbcfg |= DWC2_GUSBCFG_DDRSEL;
415 #else
416 usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
417 #endif
418 } else { /* UTMI+ interface */
419 #if (CONFIG_DWC2_UTMI_WIDTH == 16)
420 usbcfg |= DWC2_GUSBCFG_PHYIF;
421 #endif
422 }
423
424 writel(usbcfg, ®s->gusbcfg);
425
426 /* Reset after setting the PHY parameters */
427 dwc_otg_core_reset(dev, regs);
428 #endif
429
430 usbcfg = readl(®s->gusbcfg);
431 usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
432 #ifdef CONFIG_DWC2_ULPI_FS_LS
433 uint32_t hwcfg2 = readl(®s->ghwcfg2);
434 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
435 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
436 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
437 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
438 if (hval == 2 && fval == 1) {
439 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
440 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
441 }
442 #endif
443 if (priv->hnp_srp_disable)
444 usbcfg |= DWC2_GUSBCFG_FORCEHOSTMODE;
445
446 writel(usbcfg, ®s->gusbcfg);
447
448 /* Program the GAHBCFG Register. */
449 switch (readl(®s->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
450 case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
451 break;
452 case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
453 while (brst_sz > 1) {
454 ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
455 ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
456 brst_sz >>= 1;
457 }
458
459 #ifdef CONFIG_DWC2_DMA_ENABLE
460 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
461 #endif
462 break;
463
464 case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
465 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
466 #ifdef CONFIG_DWC2_DMA_ENABLE
467 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
468 #endif
469 break;
470 }
471
472 writel(ahbcfg, ®s->gahbcfg);
473
474 /* Program the capabilities in GUSBCFG Register */
475 usbcfg = 0;
476
477 if (!priv->hnp_srp_disable)
478 usbcfg |= DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP;
479 #ifdef CONFIG_DWC2_IC_USB_CAP
480 usbcfg |= DWC2_GUSBCFG_IC_USB_CAP;
481 #endif
482
483 setbits_le32(®s->gusbcfg, usbcfg);
484 }
485
486 /*
487 * Prepares a host channel for transferring packets to/from a specific
488 * endpoint. The HCCHARn register is set up with the characteristics specified
489 * in _hc. Host channel interrupts that may need to be serviced while this
490 * transfer is in progress are enabled.
491 *
492 * @param regs Programming view of DWC_otg controller
493 * @param hc Information needed to initialize the host channel
494 */
dwc_otg_hc_init(struct dwc2_core_regs * regs,uint8_t hc_num,struct usb_device * dev,uint8_t dev_addr,uint8_t ep_num,uint8_t ep_is_in,uint8_t ep_type,uint16_t max_packet)495 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
496 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num,
497 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet)
498 {
499 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[hc_num];
500 uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
501 (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
502 (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
503 (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
504 (max_packet << DWC2_HCCHAR_MPS_OFFSET);
505
506 if (dev->speed == USB_SPEED_LOW)
507 hcchar |= DWC2_HCCHAR_LSPDDEV;
508
509 /*
510 * Program the HCCHARn register with the endpoint characteristics
511 * for the current transfer.
512 */
513 writel(hcchar, &hc_regs->hcchar);
514
515 /* Program the HCSPLIT register, default to no SPLIT */
516 writel(0, &hc_regs->hcsplt);
517 }
518
dwc_otg_hc_init_split(struct dwc2_hc_regs * hc_regs,uint8_t hub_devnum,uint8_t hub_port)519 static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs,
520 uint8_t hub_devnum, uint8_t hub_port)
521 {
522 uint32_t hcsplt = 0;
523
524 hcsplt = DWC2_HCSPLT_SPLTENA;
525 hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET;
526 hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET;
527
528 /* Program the HCSPLIT register for SPLITs */
529 writel(hcsplt, &hc_regs->hcsplt);
530 }
531
532 /*
533 * DWC2 to USB API interface
534 */
535 /* Direction: In ; Request: Status */
dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs * regs,struct usb_device * dev,void * buffer,int txlen,struct devrequest * cmd)536 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs,
537 struct usb_device *dev, void *buffer,
538 int txlen, struct devrequest *cmd)
539 {
540 uint32_t hprt0 = 0;
541 uint32_t port_status = 0;
542 uint32_t port_change = 0;
543 int len = 0;
544 int stat = 0;
545
546 switch (cmd->requesttype & ~USB_DIR_IN) {
547 case 0:
548 *(uint16_t *)buffer = cpu_to_le16(1);
549 len = 2;
550 break;
551 case USB_RECIP_INTERFACE:
552 case USB_RECIP_ENDPOINT:
553 *(uint16_t *)buffer = cpu_to_le16(0);
554 len = 2;
555 break;
556 case USB_TYPE_CLASS:
557 *(uint32_t *)buffer = cpu_to_le32(0);
558 len = 4;
559 break;
560 case USB_RECIP_OTHER | USB_TYPE_CLASS:
561 hprt0 = readl(®s->hprt0);
562 if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
563 port_status |= USB_PORT_STAT_CONNECTION;
564 if (hprt0 & DWC2_HPRT0_PRTENA)
565 port_status |= USB_PORT_STAT_ENABLE;
566 if (hprt0 & DWC2_HPRT0_PRTSUSP)
567 port_status |= USB_PORT_STAT_SUSPEND;
568 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
569 port_status |= USB_PORT_STAT_OVERCURRENT;
570 if (hprt0 & DWC2_HPRT0_PRTRST)
571 port_status |= USB_PORT_STAT_RESET;
572 if (hprt0 & DWC2_HPRT0_PRTPWR)
573 port_status |= USB_PORT_STAT_POWER;
574
575 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW)
576 port_status |= USB_PORT_STAT_LOW_SPEED;
577 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
578 DWC2_HPRT0_PRTSPD_HIGH)
579 port_status |= USB_PORT_STAT_HIGH_SPEED;
580
581 if (hprt0 & DWC2_HPRT0_PRTENCHNG)
582 port_change |= USB_PORT_STAT_C_ENABLE;
583 if (hprt0 & DWC2_HPRT0_PRTCONNDET)
584 port_change |= USB_PORT_STAT_C_CONNECTION;
585 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
586 port_change |= USB_PORT_STAT_C_OVERCURRENT;
587
588 *(uint32_t *)buffer = cpu_to_le32(port_status |
589 (port_change << 16));
590 len = 4;
591 break;
592 default:
593 puts("unsupported root hub command\n");
594 stat = USB_ST_STALLED;
595 }
596
597 dev->act_len = min(len, txlen);
598 dev->status = stat;
599
600 return stat;
601 }
602
603 /* Direction: In ; Request: Descriptor */
dwc_otg_submit_rh_msg_in_descriptor(struct usb_device * dev,void * buffer,int txlen,struct devrequest * cmd)604 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
605 void *buffer, int txlen,
606 struct devrequest *cmd)
607 {
608 unsigned char data[32];
609 uint32_t dsc;
610 int len = 0;
611 int stat = 0;
612 uint16_t wValue = cpu_to_le16(cmd->value);
613 uint16_t wLength = cpu_to_le16(cmd->length);
614
615 switch (cmd->requesttype & ~USB_DIR_IN) {
616 case 0:
617 switch (wValue & 0xff00) {
618 case 0x0100: /* device descriptor */
619 len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
620 memcpy(buffer, root_hub_dev_des, len);
621 break;
622 case 0x0200: /* configuration descriptor */
623 len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
624 memcpy(buffer, root_hub_config_des, len);
625 break;
626 case 0x0300: /* string descriptors */
627 switch (wValue & 0xff) {
628 case 0x00:
629 len = min3(txlen, (int)sizeof(root_hub_str_index0),
630 (int)wLength);
631 memcpy(buffer, root_hub_str_index0, len);
632 break;
633 case 0x01:
634 len = min3(txlen, (int)sizeof(root_hub_str_index1),
635 (int)wLength);
636 memcpy(buffer, root_hub_str_index1, len);
637 break;
638 }
639 break;
640 default:
641 stat = USB_ST_STALLED;
642 }
643 break;
644
645 case USB_TYPE_CLASS:
646 /* Root port config, set 1 port and nothing else. */
647 dsc = 0x00000001;
648
649 data[0] = 9; /* min length; */
650 data[1] = 0x29;
651 data[2] = dsc & RH_A_NDP;
652 data[3] = 0;
653 if (dsc & RH_A_PSM)
654 data[3] |= 0x1;
655 if (dsc & RH_A_NOCP)
656 data[3] |= 0x10;
657 else if (dsc & RH_A_OCPM)
658 data[3] |= 0x8;
659
660 /* corresponds to data[4-7] */
661 data[5] = (dsc & RH_A_POTPGT) >> 24;
662 data[7] = dsc & RH_B_DR;
663 if (data[2] < 7) {
664 data[8] = 0xff;
665 } else {
666 data[0] += 2;
667 data[8] = (dsc & RH_B_DR) >> 8;
668 data[9] = 0xff;
669 data[10] = data[9];
670 }
671
672 len = min3(txlen, (int)data[0], (int)wLength);
673 memcpy(buffer, data, len);
674 break;
675 default:
676 puts("unsupported root hub command\n");
677 stat = USB_ST_STALLED;
678 }
679
680 dev->act_len = min(len, txlen);
681 dev->status = stat;
682
683 return stat;
684 }
685
686 /* Direction: In ; Request: Configuration */
dwc_otg_submit_rh_msg_in_configuration(struct usb_device * dev,void * buffer,int txlen,struct devrequest * cmd)687 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
688 void *buffer, int txlen,
689 struct devrequest *cmd)
690 {
691 int len = 0;
692 int stat = 0;
693
694 switch (cmd->requesttype & ~USB_DIR_IN) {
695 case 0:
696 *(uint8_t *)buffer = 0x01;
697 len = 1;
698 break;
699 default:
700 puts("unsupported root hub command\n");
701 stat = USB_ST_STALLED;
702 }
703
704 dev->act_len = min(len, txlen);
705 dev->status = stat;
706
707 return stat;
708 }
709
710 /* Direction: In */
dwc_otg_submit_rh_msg_in(struct dwc2_priv * priv,struct usb_device * dev,void * buffer,int txlen,struct devrequest * cmd)711 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv,
712 struct usb_device *dev, void *buffer,
713 int txlen, struct devrequest *cmd)
714 {
715 switch (cmd->request) {
716 case USB_REQ_GET_STATUS:
717 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer,
718 txlen, cmd);
719 case USB_REQ_GET_DESCRIPTOR:
720 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
721 txlen, cmd);
722 case USB_REQ_GET_CONFIGURATION:
723 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
724 txlen, cmd);
725 default:
726 puts("unsupported root hub command\n");
727 return USB_ST_STALLED;
728 }
729 }
730
731 /* Direction: Out */
dwc_otg_submit_rh_msg_out(struct dwc2_priv * priv,struct usb_device * dev,void * buffer,int txlen,struct devrequest * cmd)732 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv,
733 struct usb_device *dev,
734 void *buffer, int txlen,
735 struct devrequest *cmd)
736 {
737 struct dwc2_core_regs *regs = priv->regs;
738 int len = 0;
739 int stat = 0;
740 uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
741 uint16_t wValue = cpu_to_le16(cmd->value);
742
743 switch (bmrtype_breq & ~USB_DIR_IN) {
744 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
745 case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
746 break;
747
748 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
749 switch (wValue) {
750 case USB_PORT_FEAT_C_CONNECTION:
751 setbits_le32(®s->hprt0, DWC2_HPRT0_PRTCONNDET);
752 break;
753 }
754 break;
755
756 case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
757 switch (wValue) {
758 case USB_PORT_FEAT_SUSPEND:
759 break;
760
761 case USB_PORT_FEAT_RESET:
762 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
763 DWC2_HPRT0_PRTCONNDET |
764 DWC2_HPRT0_PRTENCHNG |
765 DWC2_HPRT0_PRTOVRCURRCHNG,
766 DWC2_HPRT0_PRTRST);
767 mdelay(50);
768 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTRST);
769 break;
770
771 case USB_PORT_FEAT_POWER:
772 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
773 DWC2_HPRT0_PRTCONNDET |
774 DWC2_HPRT0_PRTENCHNG |
775 DWC2_HPRT0_PRTOVRCURRCHNG,
776 DWC2_HPRT0_PRTRST);
777 break;
778
779 case USB_PORT_FEAT_ENABLE:
780 break;
781 }
782 break;
783 case (USB_REQ_SET_ADDRESS << 8):
784 priv->root_hub_devnum = wValue;
785 break;
786 case (USB_REQ_SET_CONFIGURATION << 8):
787 break;
788 default:
789 puts("unsupported root hub command\n");
790 stat = USB_ST_STALLED;
791 }
792
793 len = min(len, txlen);
794
795 dev->act_len = len;
796 dev->status = stat;
797
798 return stat;
799 }
800
dwc_otg_submit_rh_msg(struct dwc2_priv * priv,struct usb_device * dev,unsigned long pipe,void * buffer,int txlen,struct devrequest * cmd)801 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev,
802 unsigned long pipe, void *buffer, int txlen,
803 struct devrequest *cmd)
804 {
805 int stat = 0;
806
807 if (usb_pipeint(pipe)) {
808 puts("Root-Hub submit IRQ: NOT implemented\n");
809 return 0;
810 }
811
812 if (cmd->requesttype & USB_DIR_IN)
813 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd);
814 else
815 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd);
816
817 mdelay(1);
818
819 return stat;
820 }
821
wait_for_chhltd(struct dwc2_hc_regs * hc_regs,uint32_t * sub,u8 * toggle)822 int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle)
823 {
824 int ret;
825 uint32_t hcint, hctsiz;
826
827 ret = wait_for_bit_le32(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true,
828 2000, false);
829 if (ret)
830 return ret;
831
832 hcint = readl(&hc_regs->hcint);
833 hctsiz = readl(&hc_regs->hctsiz);
834 *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
835 DWC2_HCTSIZ_XFERSIZE_OFFSET;
836 *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
837
838 debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub,
839 *toggle);
840
841 if (hcint & DWC2_HCINT_XFERCOMP)
842 return 0;
843
844 if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
845 return -EAGAIN;
846
847 debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
848 return -EINVAL;
849 }
850
851 static int dwc2_eptype[] = {
852 DWC2_HCCHAR_EPTYPE_ISOC,
853 DWC2_HCCHAR_EPTYPE_INTR,
854 DWC2_HCCHAR_EPTYPE_CONTROL,
855 DWC2_HCCHAR_EPTYPE_BULK,
856 };
857
transfer_chunk(struct dwc2_hc_regs * hc_regs,void * aligned_buffer,u8 * pid,int in,void * buffer,int num_packets,int xfer_len,int * actual_len,int odd_frame)858 static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
859 u8 *pid, int in, void *buffer, int num_packets,
860 int xfer_len, int *actual_len, int odd_frame)
861 {
862 int ret = 0;
863 uint32_t sub;
864
865 debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
866 *pid, xfer_len, num_packets);
867
868 writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
869 (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
870 (*pid << DWC2_HCTSIZ_PID_OFFSET),
871 &hc_regs->hctsiz);
872
873 if (xfer_len) {
874 if (in) {
875 invalidate_dcache_range(
876 (uintptr_t)aligned_buffer,
877 (uintptr_t)aligned_buffer +
878 roundup(xfer_len, ARCH_DMA_MINALIGN));
879 } else {
880 memcpy(aligned_buffer, buffer, xfer_len);
881 flush_dcache_range(
882 (uintptr_t)aligned_buffer,
883 (uintptr_t)aligned_buffer +
884 roundup(xfer_len, ARCH_DMA_MINALIGN));
885 }
886 }
887
888 writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma);
889
890 /* Clear old interrupt conditions for this host channel. */
891 writel(0x3fff, &hc_regs->hcint);
892
893 /* Set host channel enable after all other setup is complete. */
894 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
895 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS |
896 DWC2_HCCHAR_ODDFRM,
897 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
898 (odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) |
899 DWC2_HCCHAR_CHEN);
900
901 ret = wait_for_chhltd(hc_regs, &sub, pid);
902 if (ret < 0)
903 return ret;
904
905 if (in) {
906 xfer_len -= sub;
907
908 invalidate_dcache_range((unsigned long)aligned_buffer,
909 (unsigned long)aligned_buffer +
910 roundup(xfer_len, ARCH_DMA_MINALIGN));
911
912 memcpy(buffer, aligned_buffer, xfer_len);
913 }
914 *actual_len = xfer_len;
915
916 return ret;
917 }
918
chunk_msg(struct dwc2_priv * priv,struct usb_device * dev,unsigned long pipe,u8 * pid,int in,void * buffer,int len)919 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
920 unsigned long pipe, u8 *pid, int in, void *buffer, int len)
921 {
922 struct dwc2_core_regs *regs = priv->regs;
923 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL];
924 struct dwc2_host_regs *host_regs = ®s->host_regs;
925 int devnum = usb_pipedevice(pipe);
926 int ep = usb_pipeendpoint(pipe);
927 int max = usb_maxpacket(dev, pipe);
928 int eptype = dwc2_eptype[usb_pipetype(pipe)];
929 int done = 0;
930 int ret = 0;
931 int do_split = 0;
932 int complete_split = 0;
933 uint32_t xfer_len;
934 uint32_t num_packets;
935 int stop_transfer = 0;
936 uint32_t max_xfer_len;
937 int ssplit_frame_num = 0;
938
939 debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
940 in, len);
941
942 max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max;
943 if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
944 max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE;
945 if (max_xfer_len > DWC2_DATA_BUF_SIZE)
946 max_xfer_len = DWC2_DATA_BUF_SIZE;
947
948 /* Make sure that max_xfer_len is a multiple of max packet size. */
949 num_packets = max_xfer_len / max;
950 max_xfer_len = num_packets * max;
951
952 /* Initialize channel */
953 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
954 eptype, max);
955
956 /* Check if the target is a FS/LS device behind a HS hub */
957 if (dev->speed != USB_SPEED_HIGH) {
958 uint8_t hub_addr;
959 uint8_t hub_port;
960 uint32_t hprt0 = readl(®s->hprt0);
961 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
962 DWC2_HPRT0_PRTSPD_HIGH) {
963 usb_find_usb2_hub_address_port(dev, &hub_addr,
964 &hub_port);
965 dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port);
966
967 do_split = 1;
968 num_packets = 1;
969 max_xfer_len = max;
970 }
971 }
972
973 do {
974 int actual_len = 0;
975 uint32_t hcint;
976 int odd_frame = 0;
977 xfer_len = len - done;
978
979 if (xfer_len > max_xfer_len)
980 xfer_len = max_xfer_len;
981 else if (xfer_len > max)
982 num_packets = (xfer_len + max - 1) / max;
983 else
984 num_packets = 1;
985
986 if (complete_split)
987 setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
988 else if (do_split)
989 clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
990
991 if (eptype == DWC2_HCCHAR_EPTYPE_INTR) {
992 int uframe_num = readl(&host_regs->hfnum);
993 if (!(uframe_num & 0x1))
994 odd_frame = 1;
995 }
996
997 ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid,
998 in, (char *)buffer + done, num_packets,
999 xfer_len, &actual_len, odd_frame);
1000
1001 hcint = readl(&hc_regs->hcint);
1002 if (complete_split) {
1003 stop_transfer = 0;
1004 if (hcint & DWC2_HCINT_NYET) {
1005 ret = 0;
1006 int frame_num = DWC2_HFNUM_MAX_FRNUM &
1007 readl(&host_regs->hfnum);
1008 if (((frame_num - ssplit_frame_num) &
1009 DWC2_HFNUM_MAX_FRNUM) > 4)
1010 ret = -EAGAIN;
1011 } else
1012 complete_split = 0;
1013 } else if (do_split) {
1014 if (hcint & DWC2_HCINT_ACK) {
1015 ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM &
1016 readl(&host_regs->hfnum);
1017 ret = 0;
1018 complete_split = 1;
1019 }
1020 }
1021
1022 if (ret)
1023 break;
1024
1025 if (actual_len < xfer_len)
1026 stop_transfer = 1;
1027
1028 done += actual_len;
1029
1030 /* Transactions are done when when either all data is transferred or
1031 * there is a short transfer. In case of a SPLIT make sure the CSPLIT
1032 * is executed.
1033 */
1034 } while (((done < len) && !stop_transfer) || complete_split);
1035
1036 writel(0, &hc_regs->hcintmsk);
1037 writel(0xFFFFFFFF, &hc_regs->hcint);
1038
1039 dev->status = 0;
1040 dev->act_len = done;
1041
1042 return ret;
1043 }
1044
1045 /* U-Boot USB transmission interface */
_submit_bulk_msg(struct dwc2_priv * priv,struct usb_device * dev,unsigned long pipe,void * buffer,int len)1046 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev,
1047 unsigned long pipe, void *buffer, int len)
1048 {
1049 int devnum = usb_pipedevice(pipe);
1050 int ep = usb_pipeendpoint(pipe);
1051 u8* pid;
1052
1053 if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) {
1054 dev->status = 0;
1055 return -EINVAL;
1056 }
1057
1058 if (usb_pipein(pipe))
1059 pid = &priv->in_data_toggle[devnum][ep];
1060 else
1061 pid = &priv->out_data_toggle[devnum][ep];
1062
1063 return chunk_msg(priv, dev, pipe, pid, usb_pipein(pipe), buffer, len);
1064 }
1065
_submit_control_msg(struct dwc2_priv * priv,struct usb_device * dev,unsigned long pipe,void * buffer,int len,struct devrequest * setup)1066 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
1067 unsigned long pipe, void *buffer, int len,
1068 struct devrequest *setup)
1069 {
1070 int devnum = usb_pipedevice(pipe);
1071 int ret, act_len;
1072 u8 pid;
1073 /* For CONTROL endpoint pid should start with DATA1 */
1074 int status_direction;
1075
1076 if (devnum == priv->root_hub_devnum) {
1077 dev->status = 0;
1078 dev->speed = USB_SPEED_HIGH;
1079 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len,
1080 setup);
1081 }
1082
1083 /* SETUP stage */
1084 pid = DWC2_HC_PID_SETUP;
1085 do {
1086 ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8);
1087 } while (ret == -EAGAIN);
1088 if (ret)
1089 return ret;
1090
1091 /* DATA stage */
1092 act_len = 0;
1093 if (buffer) {
1094 pid = DWC2_HC_PID_DATA1;
1095 do {
1096 ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe),
1097 buffer, len);
1098 act_len += dev->act_len;
1099 buffer += dev->act_len;
1100 len -= dev->act_len;
1101 } while (ret == -EAGAIN);
1102 if (ret)
1103 return ret;
1104 status_direction = usb_pipeout(pipe);
1105 } else {
1106 /* No-data CONTROL always ends with an IN transaction */
1107 status_direction = 1;
1108 }
1109
1110 /* STATUS stage */
1111 pid = DWC2_HC_PID_DATA1;
1112 do {
1113 ret = chunk_msg(priv, dev, pipe, &pid, status_direction,
1114 priv->status_buffer, 0);
1115 } while (ret == -EAGAIN);
1116 if (ret)
1117 return ret;
1118
1119 dev->act_len = act_len;
1120
1121 return 0;
1122 }
1123
_submit_int_msg(struct dwc2_priv * priv,struct usb_device * dev,unsigned long pipe,void * buffer,int len,int interval,bool nonblock)1124 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev,
1125 unsigned long pipe, void *buffer, int len, int interval,
1126 bool nonblock)
1127 {
1128 unsigned long timeout;
1129 int ret;
1130
1131 /* FIXME: what is interval? */
1132
1133 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1134 for (;;) {
1135 if (get_timer(0) > timeout) {
1136 #if CONFIG_IS_ENABLED(DM_USB)
1137 dev_err(dev->dev,
1138 "Timeout poll on interrupt endpoint\n");
1139 #else
1140 log_err("Timeout poll on interrupt endpoint\n");
1141 #endif
1142 return -ETIMEDOUT;
1143 }
1144 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len);
1145 if ((ret != -EAGAIN) || nonblock)
1146 return ret;
1147 }
1148 }
1149
dwc2_reset(struct udevice * dev)1150 static int dwc2_reset(struct udevice *dev)
1151 {
1152 int ret;
1153 struct dwc2_priv *priv = dev_get_priv(dev);
1154
1155 ret = reset_get_bulk(dev, &priv->resets);
1156 if (ret) {
1157 dev_warn(dev, "Can't get reset: %d\n", ret);
1158 /* Return 0 if error due to !CONFIG_DM_RESET and reset
1159 * DT property is not present.
1160 */
1161 if (ret == -ENOENT || ret == -ENOTSUPP)
1162 return 0;
1163 else
1164 return ret;
1165 }
1166
1167 /* force reset to clear all IP register */
1168 reset_assert_bulk(&priv->resets);
1169 ret = reset_deassert_bulk(&priv->resets);
1170 if (ret) {
1171 reset_release_bulk(&priv->resets);
1172 dev_err(dev, "Failed to reset: %d\n", ret);
1173 return ret;
1174 }
1175
1176 return 0;
1177 }
1178
dwc2_init_common(struct udevice * dev,struct dwc2_priv * priv)1179 static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv)
1180 {
1181 struct dwc2_core_regs *regs = priv->regs;
1182 uint32_t snpsid;
1183 int i, j;
1184 int ret;
1185
1186 ret = dwc2_reset(dev);
1187 if (ret)
1188 return ret;
1189
1190 snpsid = readl(®s->gsnpsid);
1191 dev_info(dev, "Core Release: %x.%03x\n",
1192 snpsid >> 12 & 0xf, snpsid & 0xfff);
1193
1194 if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
1195 (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
1196 dev_info(dev, "SNPSID invalid (not DWC2 OTG device): %08x\n",
1197 snpsid);
1198 return -ENODEV;
1199 }
1200
1201 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
1202 priv->ext_vbus = 1;
1203 #else
1204 priv->ext_vbus = 0;
1205 #endif
1206
1207 dwc_otg_core_init(dev);
1208
1209 if (usb_get_dr_mode(dev_ofnode(dev)) == USB_DR_MODE_PERIPHERAL) {
1210 dev_dbg(dev, "USB device %s dr_mode set to %d. Skipping host_init.\n",
1211 dev->name, usb_get_dr_mode(dev_ofnode(dev)));
1212 } else {
1213 dwc_otg_core_host_init(dev, regs);
1214 }
1215
1216 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
1217 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1218 DWC2_HPRT0_PRTOVRCURRCHNG,
1219 DWC2_HPRT0_PRTRST);
1220 mdelay(50);
1221 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
1222 DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
1223 DWC2_HPRT0_PRTRST);
1224
1225 for (i = 0; i < MAX_DEVICE; i++) {
1226 for (j = 0; j < MAX_ENDPOINT; j++) {
1227 priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1228 priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1229 }
1230 }
1231
1232 /*
1233 * Add a 1 second delay here. This gives the host controller
1234 * a bit time before the comminucation with the USB devices
1235 * is started (the bus is scanned) and fixes the USB detection
1236 * problems with some problematic USB keys.
1237 */
1238 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
1239 mdelay(1000);
1240
1241 printf("USB DWC2\n");
1242
1243 return 0;
1244 }
1245
dwc2_uninit_common(struct dwc2_core_regs * regs)1246 static void dwc2_uninit_common(struct dwc2_core_regs *regs)
1247 {
1248 /* Put everything in reset. */
1249 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
1250 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1251 DWC2_HPRT0_PRTOVRCURRCHNG,
1252 DWC2_HPRT0_PRTRST);
1253 }
1254
1255 #if !CONFIG_IS_ENABLED(DM_USB)
submit_control_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int len,struct devrequest * setup)1256 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1257 int len, struct devrequest *setup)
1258 {
1259 return _submit_control_msg(&local, dev, pipe, buffer, len, setup);
1260 }
1261
submit_bulk_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int len)1262 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1263 int len)
1264 {
1265 return _submit_bulk_msg(&local, dev, pipe, buffer, len);
1266 }
1267
submit_int_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int len,int interval,bool nonblock)1268 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1269 int len, int interval, bool nonblock)
1270 {
1271 return _submit_int_msg(&local, dev, pipe, buffer, len, interval,
1272 nonblock);
1273 }
1274
1275 /* U-Boot USB control interface */
usb_lowlevel_init(int index,enum usb_init_type init,void ** controller)1276 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1277 {
1278 struct dwc2_priv *priv = &local;
1279
1280 memset(priv, '\0', sizeof(*priv));
1281 priv->root_hub_devnum = 0;
1282 priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
1283 priv->aligned_buffer = aligned_buffer_addr;
1284 priv->status_buffer = status_buffer_addr;
1285
1286 /* board-dependant init */
1287 if (board_usb_init(index, USB_INIT_HOST))
1288 return -1;
1289
1290 return dwc2_init_common(NULL, priv);
1291 }
1292
usb_lowlevel_stop(int index)1293 int usb_lowlevel_stop(int index)
1294 {
1295 dwc2_uninit_common(local.regs);
1296
1297 return 0;
1298 }
1299 #endif
1300
1301 #if CONFIG_IS_ENABLED(DM_USB)
dwc2_submit_control_msg(struct udevice * dev,struct usb_device * udev,unsigned long pipe,void * buffer,int length,struct devrequest * setup)1302 static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1303 unsigned long pipe, void *buffer, int length,
1304 struct devrequest *setup)
1305 {
1306 struct dwc2_priv *priv = dev_get_priv(dev);
1307
1308 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1309 dev->name, udev, udev->dev->name, udev->portnr);
1310
1311 return _submit_control_msg(priv, udev, pipe, buffer, length, setup);
1312 }
1313
dwc2_submit_bulk_msg(struct udevice * dev,struct usb_device * udev,unsigned long pipe,void * buffer,int length)1314 static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1315 unsigned long pipe, void *buffer, int length)
1316 {
1317 struct dwc2_priv *priv = dev_get_priv(dev);
1318
1319 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1320
1321 return _submit_bulk_msg(priv, udev, pipe, buffer, length);
1322 }
1323
dwc2_submit_int_msg(struct udevice * dev,struct usb_device * udev,unsigned long pipe,void * buffer,int length,int interval,bool nonblock)1324 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1325 unsigned long pipe, void *buffer, int length,
1326 int interval, bool nonblock)
1327 {
1328 struct dwc2_priv *priv = dev_get_priv(dev);
1329
1330 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1331
1332 return _submit_int_msg(priv, udev, pipe, buffer, length, interval,
1333 nonblock);
1334 }
1335
dwc2_usb_of_to_plat(struct udevice * dev)1336 static int dwc2_usb_of_to_plat(struct udevice *dev)
1337 {
1338 struct dwc2_priv *priv = dev_get_priv(dev);
1339
1340 priv->regs = dev_read_addr_ptr(dev);
1341 if (!priv->regs)
1342 return -EINVAL;
1343
1344 priv->oc_disable = dev_read_bool(dev, "disable-over-current");
1345 priv->hnp_srp_disable = dev_read_bool(dev, "hnp-srp-disable");
1346
1347 return 0;
1348 }
1349
dwc2_setup_phy(struct udevice * dev)1350 static int dwc2_setup_phy(struct udevice *dev)
1351 {
1352 struct dwc2_priv *priv = dev_get_priv(dev);
1353 int ret;
1354
1355 ret = generic_phy_get_by_index(dev, 0, &priv->phy);
1356 if (ret) {
1357 if (ret == -ENOENT)
1358 return 0; /* no PHY, nothing to do */
1359 dev_err(dev, "Failed to get USB PHY: %d.\n", ret);
1360 return ret;
1361 }
1362
1363 ret = generic_phy_init(&priv->phy);
1364 if (ret) {
1365 dev_dbg(dev, "Failed to init USB PHY: %d.\n", ret);
1366 return ret;
1367 }
1368
1369 ret = generic_phy_power_on(&priv->phy);
1370 if (ret) {
1371 dev_dbg(dev, "Failed to power on USB PHY: %d.\n", ret);
1372 generic_phy_exit(&priv->phy);
1373 return ret;
1374 }
1375
1376 return 0;
1377 }
1378
dwc2_shutdown_phy(struct udevice * dev)1379 static int dwc2_shutdown_phy(struct udevice *dev)
1380 {
1381 struct dwc2_priv *priv = dev_get_priv(dev);
1382 int ret;
1383
1384 /* PHY is not valid when generic_phy_get_by_index() = -ENOENT */
1385 if (!generic_phy_valid(&priv->phy))
1386 return 0; /* no PHY, nothing to do */
1387
1388 ret = generic_phy_power_off(&priv->phy);
1389 if (ret) {
1390 dev_dbg(dev, "Failed to power off USB PHY: %d.\n", ret);
1391 return ret;
1392 }
1393
1394 ret = generic_phy_exit(&priv->phy);
1395 if (ret) {
1396 dev_dbg(dev, "Failed to power off USB PHY: %d.\n", ret);
1397 return ret;
1398 }
1399
1400 return 0;
1401 }
1402
dwc2_clk_init(struct udevice * dev)1403 static int dwc2_clk_init(struct udevice *dev)
1404 {
1405 struct dwc2_priv *priv = dev_get_priv(dev);
1406 int ret;
1407
1408 ret = clk_get_bulk(dev, &priv->clks);
1409 if (ret == -ENOSYS || ret == -ENOENT)
1410 return 0;
1411 if (ret)
1412 return ret;
1413
1414 ret = clk_enable_bulk(&priv->clks);
1415 if (ret) {
1416 clk_release_bulk(&priv->clks);
1417 return ret;
1418 }
1419
1420 return 0;
1421 }
1422
dwc2_usb_probe(struct udevice * dev)1423 static int dwc2_usb_probe(struct udevice *dev)
1424 {
1425 struct dwc2_priv *priv = dev_get_priv(dev);
1426 struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev);
1427 int ret;
1428
1429 bus_priv->desc_before_addr = true;
1430
1431 ret = dwc2_clk_init(dev);
1432 if (ret)
1433 return ret;
1434
1435 ret = dwc2_setup_phy(dev);
1436 if (ret)
1437 return ret;
1438
1439 return dwc2_init_common(dev, priv);
1440 }
1441
dwc2_usb_remove(struct udevice * dev)1442 static int dwc2_usb_remove(struct udevice *dev)
1443 {
1444 struct dwc2_priv *priv = dev_get_priv(dev);
1445 int ret;
1446
1447 ret = dwc_vbus_supply_exit(dev);
1448 if (ret)
1449 return ret;
1450
1451 ret = dwc2_shutdown_phy(dev);
1452 if (ret) {
1453 dev_dbg(dev, "Failed to shutdown USB PHY: %d.\n", ret);
1454 return ret;
1455 }
1456
1457 dwc2_uninit_common(priv->regs);
1458
1459 reset_release_bulk(&priv->resets);
1460 clk_disable_bulk(&priv->clks);
1461 clk_release_bulk(&priv->clks);
1462
1463 return 0;
1464 }
1465
1466 struct dm_usb_ops dwc2_usb_ops = {
1467 .control = dwc2_submit_control_msg,
1468 .bulk = dwc2_submit_bulk_msg,
1469 .interrupt = dwc2_submit_int_msg,
1470 };
1471
1472 static const struct udevice_id dwc2_usb_ids[] = {
1473 { .compatible = "brcm,bcm2835-usb" },
1474 { .compatible = "brcm,bcm2708-usb" },
1475 { .compatible = "snps,dwc2" },
1476 { }
1477 };
1478
1479 U_BOOT_DRIVER(usb_dwc2) = {
1480 .name = "dwc2_usb",
1481 .id = UCLASS_USB,
1482 .of_match = dwc2_usb_ids,
1483 .of_to_plat = dwc2_usb_of_to_plat,
1484 .probe = dwc2_usb_probe,
1485 .remove = dwc2_usb_remove,
1486 .ops = &dwc2_usb_ops,
1487 .priv_auto = sizeof(struct dwc2_priv),
1488 .flags = DM_FLAG_ALLOC_PRIV_DMA,
1489 };
1490 #endif
1491