1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * NAND driver for TI DaVinci based boards.
4 *
5 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6 *
7 * Based on Linux DaVinci NAND driver by TI. Original copyright follows:
8 */
9
10 /*
11 *
12 * linux/drivers/mtd/nand/raw/nand_davinci.c
13 *
14 * NAND Flash Driver
15 *
16 * Copyright (C) 2006 Texas Instruments.
17 *
18 * ----------------------------------------------------------------------------
19 *
20 * ----------------------------------------------------------------------------
21 *
22 * Overview:
23 * This is a device driver for the NAND flash device found on the
24 * DaVinci board which utilizes the Samsung k9k2g08 part.
25 *
26 Modifications:
27 ver. 1.0: Feb 2005, Vinod/Sudhakar
28 -
29 */
30
31 #include <common.h>
32 #include <log.h>
33 #include <asm/io.h>
34 #include <nand.h>
35 #include <dm/uclass.h>
36 #include <asm/ti-common/davinci_nand.h>
37
38 /* Definitions for 4-bit hardware ECC */
39 #define NAND_TIMEOUT 10240
40 #define NAND_ECC_BUSY 0xC
41 #define NAND_4BITECC_MASK 0x03FF03FF
42 #define EMIF_NANDFSR_ECC_STATE_MASK 0x00000F00
43 #define ECC_STATE_NO_ERR 0x0
44 #define ECC_STATE_TOO_MANY_ERRS 0x1
45 #define ECC_STATE_ERR_CORR_COMP_P 0x2
46 #define ECC_STATE_ERR_CORR_COMP_N 0x3
47
48 /*
49 * Exploit the little endianness of the ARM to do multi-byte transfers
50 * per device read. This can perform over twice as quickly as individual
51 * byte transfers when buffer alignment is conducive.
52 *
53 * NOTE: This only works if the NAND is not connected to the 2 LSBs of
54 * the address bus. On Davinci EVM platforms this has always been true.
55 */
nand_davinci_read_buf(struct mtd_info * mtd,uint8_t * buf,int len)56 static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
57 {
58 struct nand_chip *chip = mtd_to_nand(mtd);
59 const u32 *nand = chip->IO_ADDR_R;
60
61 /* Make sure that buf is 32 bit aligned */
62 if (((int)buf & 0x3) != 0) {
63 if (((int)buf & 0x1) != 0) {
64 if (len) {
65 *buf = readb(nand);
66 buf += 1;
67 len--;
68 }
69 }
70
71 if (((int)buf & 0x3) != 0) {
72 if (len >= 2) {
73 *(u16 *)buf = readw(nand);
74 buf += 2;
75 len -= 2;
76 }
77 }
78 }
79
80 /* copy aligned data */
81 while (len >= 4) {
82 *(u32 *)buf = __raw_readl(nand);
83 buf += 4;
84 len -= 4;
85 }
86
87 /* mop up any remaining bytes */
88 if (len) {
89 if (len >= 2) {
90 *(u16 *)buf = readw(nand);
91 buf += 2;
92 len -= 2;
93 }
94
95 if (len)
96 *buf = readb(nand);
97 }
98 }
99
nand_davinci_write_buf(struct mtd_info * mtd,const uint8_t * buf,int len)100 static void nand_davinci_write_buf(struct mtd_info *mtd, const uint8_t *buf,
101 int len)
102 {
103 struct nand_chip *chip = mtd_to_nand(mtd);
104 const u32 *nand = chip->IO_ADDR_W;
105
106 /* Make sure that buf is 32 bit aligned */
107 if (((int)buf & 0x3) != 0) {
108 if (((int)buf & 0x1) != 0) {
109 if (len) {
110 writeb(*buf, nand);
111 buf += 1;
112 len--;
113 }
114 }
115
116 if (((int)buf & 0x3) != 0) {
117 if (len >= 2) {
118 writew(*(u16 *)buf, nand);
119 buf += 2;
120 len -= 2;
121 }
122 }
123 }
124
125 /* copy aligned data */
126 while (len >= 4) {
127 __raw_writel(*(u32 *)buf, nand);
128 buf += 4;
129 len -= 4;
130 }
131
132 /* mop up any remaining bytes */
133 if (len) {
134 if (len >= 2) {
135 writew(*(u16 *)buf, nand);
136 buf += 2;
137 len -= 2;
138 }
139
140 if (len)
141 writeb(*buf, nand);
142 }
143 }
144
nand_davinci_hwcontrol(struct mtd_info * mtd,int cmd,unsigned int ctrl)145 static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
146 unsigned int ctrl)
147 {
148 struct nand_chip *this = mtd_to_nand(mtd);
149 u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
150
151 if (ctrl & NAND_CTRL_CHANGE) {
152 IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
153
154 if (ctrl & NAND_CLE)
155 IO_ADDR_W |= MASK_CLE;
156 if (ctrl & NAND_ALE)
157 IO_ADDR_W |= MASK_ALE;
158 this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
159 }
160
161 if (cmd != NAND_CMD_NONE)
162 writeb(cmd, IO_ADDR_W);
163 }
164
165 #ifdef CONFIG_SYS_NAND_HW_ECC
166
nand_davinci_readecc(struct mtd_info * mtd)167 static u_int32_t nand_davinci_readecc(struct mtd_info *mtd)
168 {
169 u_int32_t ecc = 0;
170
171 ecc = __raw_readl(&(davinci_emif_regs->nandfecc[
172 CONFIG_SYS_NAND_CS - 2]));
173
174 return ecc;
175 }
176
nand_davinci_enable_hwecc(struct mtd_info * mtd,int mode)177 static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
178 {
179 u_int32_t val;
180
181 /* reading the ECC result register resets the ECC calculation */
182 nand_davinci_readecc(mtd);
183
184 val = __raw_readl(&davinci_emif_regs->nandfcr);
185 val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
186 val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
187 __raw_writel(val, &davinci_emif_regs->nandfcr);
188 }
189
nand_davinci_calculate_ecc(struct mtd_info * mtd,const u_char * dat,u_char * ecc_code)190 static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
191 u_char *ecc_code)
192 {
193 u_int32_t tmp;
194
195 tmp = nand_davinci_readecc(mtd);
196
197 /* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
198 * and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
199 tmp = (tmp & 0x00000fff) | ((tmp & 0x0fff0000) >> 4);
200
201 /* Invert so that erased block ECC is correct */
202 tmp = ~tmp;
203
204 *ecc_code++ = tmp;
205 *ecc_code++ = tmp >> 8;
206 *ecc_code++ = tmp >> 16;
207
208 /* NOTE: the above code matches mainline Linux:
209 * .PQR.stu ==> ~PQRstu
210 *
211 * MontaVista/TI kernels encode those bytes differently, use
212 * complicated (and allegedly sometimes-wrong) correction code,
213 * and usually shipped with U-Boot that uses software ECC:
214 * .PQR.stu ==> PsQRtu
215 *
216 * If you need MV/TI compatible NAND I/O in U-Boot, it should
217 * be possible to (a) change the mangling above, (b) reverse
218 * that mangling in nand_davinci_correct_data() below.
219 */
220
221 return 0;
222 }
223
nand_davinci_correct_data(struct mtd_info * mtd,u_char * dat,u_char * read_ecc,u_char * calc_ecc)224 static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat,
225 u_char *read_ecc, u_char *calc_ecc)
226 {
227 struct nand_chip *this = mtd_to_nand(mtd);
228 u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) |
229 (read_ecc[2] << 16);
230 u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) |
231 (calc_ecc[2] << 16);
232 u_int32_t diff = ecc_calc ^ ecc_nand;
233
234 if (diff) {
235 if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
236 /* Correctable error */
237 if ((diff >> (12 + 3)) < this->ecc.size) {
238 uint8_t find_bit = 1 << ((diff >> 12) & 7);
239 uint32_t find_byte = diff >> (12 + 3);
240
241 dat[find_byte] ^= find_bit;
242 pr_debug("Correcting single "
243 "bit ECC error at offset: %d, bit: "
244 "%d\n", find_byte, find_bit);
245 return 1;
246 } else {
247 return -EBADMSG;
248 }
249 } else if (!(diff & (diff - 1))) {
250 /* Single bit ECC error in the ECC itself,
251 nothing to fix */
252 pr_debug("Single bit ECC error in " "ECC.\n");
253 return 1;
254 } else {
255 /* Uncorrectable error */
256 pr_debug("ECC UNCORRECTED_ERROR 1\n");
257 return -EBADMSG;
258 }
259 }
260 return 0;
261 }
262 #endif /* CONFIG_SYS_NAND_HW_ECC */
263
264 #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
265 static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = {
266 #if defined(CONFIG_SYS_NAND_PAGE_2K)
267 .eccbytes = 40,
268 #ifdef CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
269 .eccpos = {
270 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
271 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
272 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
273 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
274 },
275 .oobfree = {
276 {2, 4}, {16, 6}, {32, 6}, {48, 6},
277 },
278 #else
279 .eccpos = {
280 24, 25, 26, 27, 28,
281 29, 30, 31, 32, 33, 34, 35, 36, 37, 38,
282 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
283 49, 50, 51, 52, 53, 54, 55, 56, 57, 58,
284 59, 60, 61, 62, 63,
285 },
286 .oobfree = {
287 {.offset = 2, .length = 22, },
288 },
289 #endif /* #ifdef CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC */
290 #elif defined(CONFIG_SYS_NAND_PAGE_4K)
291 .eccbytes = 80,
292 .eccpos = {
293 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
294 58, 59, 60, 61, 62, 63, 64, 65, 66, 67,
295 68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
296 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,
297 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,
298 98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
299 108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
300 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
301 },
302 .oobfree = {
303 {.offset = 2, .length = 46, },
304 },
305 #endif
306 };
307
308 #if defined CONFIG_KEYSTONE_RBL_NAND
309 static struct nand_ecclayout nand_keystone_rbl_4bit_layout_oobfirst = {
310 #if defined(CONFIG_SYS_NAND_PAGE_2K)
311 .eccbytes = 40,
312 .eccpos = {
313 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
314 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
315 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
316 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
317 },
318 .oobfree = {
319 {.offset = 2, .length = 4, },
320 {.offset = 16, .length = 6, },
321 {.offset = 32, .length = 6, },
322 {.offset = 48, .length = 6, },
323 },
324 #elif defined(CONFIG_SYS_NAND_PAGE_4K)
325 .eccbytes = 80,
326 .eccpos = {
327 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
328 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
329 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
330 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
331 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
332 86, 87, 88, 89, 90, 91, 92, 93, 94, 95,
333 102, 103, 104, 105, 106, 107, 108, 109, 110, 111,
334 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
335 },
336 .oobfree = {
337 {.offset = 2, .length = 4, },
338 {.offset = 16, .length = 6, },
339 {.offset = 32, .length = 6, },
340 {.offset = 48, .length = 6, },
341 {.offset = 64, .length = 6, },
342 {.offset = 80, .length = 6, },
343 {.offset = 96, .length = 6, },
344 {.offset = 112, .length = 6, },
345 },
346 #endif
347 };
348
349 #ifdef CONFIG_SYS_NAND_PAGE_2K
350 #define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 11
351 #elif defined(CONFIG_SYS_NAND_PAGE_4K)
352 #define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 12
353 #endif
354
355 /**
356 * nand_davinci_write_page - write one page
357 * @mtd: MTD device structure
358 * @chip: NAND chip descriptor
359 * @buf: the data to write
360 * @oob_required: must write chip->oob_poi to OOB
361 * @page: page number to write
362 * @raw: use _raw version of write_page
363 */
nand_davinci_write_page(struct mtd_info * mtd,struct nand_chip * chip,uint32_t offset,int data_len,const uint8_t * buf,int oob_required,int page,int raw)364 static int nand_davinci_write_page(struct mtd_info *mtd, struct nand_chip *chip,
365 uint32_t offset, int data_len,
366 const uint8_t *buf, int oob_required,
367 int page, int raw)
368 {
369 int status;
370 int ret = 0;
371 struct nand_ecclayout *saved_ecc_layout;
372
373 /* save current ECC layout and assign Keystone RBL ECC layout */
374 if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
375 saved_ecc_layout = chip->ecc.layout;
376 chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst;
377 mtd->oobavail = chip->ecc.layout->oobavail;
378 }
379
380 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
381
382 if (unlikely(raw)) {
383 status = chip->ecc.write_page_raw(mtd, chip, buf,
384 oob_required, page);
385 } else {
386 status = chip->ecc.write_page(mtd, chip, buf,
387 oob_required, page);
388 }
389
390 if (status < 0) {
391 ret = status;
392 goto err;
393 }
394
395 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
396 status = chip->waitfunc(mtd, chip);
397
398 if (status & NAND_STATUS_FAIL) {
399 ret = -EIO;
400 goto err;
401 }
402
403 err:
404 /* restore ECC layout */
405 if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
406 chip->ecc.layout = saved_ecc_layout;
407 mtd->oobavail = saved_ecc_layout->oobavail;
408 }
409
410 return ret;
411 }
412
413 /**
414 * nand_davinci_read_page_hwecc - hardware ECC based page read function
415 * @mtd: mtd info structure
416 * @chip: nand chip info structure
417 * @buf: buffer to store read data
418 * @oob_required: caller requires OOB data read to chip->oob_poi
419 * @page: page number to read
420 *
421 * Not for syndrome calculating ECC controllers which need a special oob layout.
422 */
nand_davinci_read_page_hwecc(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)423 static int nand_davinci_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
424 uint8_t *buf, int oob_required, int page)
425 {
426 int i, eccsize = chip->ecc.size;
427 int eccbytes = chip->ecc.bytes;
428 int eccsteps = chip->ecc.steps;
429 uint32_t *eccpos;
430 uint8_t *p = buf;
431 uint8_t *ecc_code = chip->buffers->ecccode;
432 uint8_t *ecc_calc = chip->buffers->ecccalc;
433 struct nand_ecclayout *saved_ecc_layout = chip->ecc.layout;
434
435 /* save current ECC layout and assign Keystone RBL ECC layout */
436 if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
437 chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst;
438 mtd->oobavail = chip->ecc.layout->oobavail;
439 }
440
441 eccpos = chip->ecc.layout->eccpos;
442
443 /* Read the OOB area first */
444 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
445 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
446 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
447
448 for (i = 0; i < chip->ecc.total; i++)
449 ecc_code[i] = chip->oob_poi[eccpos[i]];
450
451 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
452 int stat;
453
454 chip->ecc.hwctl(mtd, NAND_ECC_READ);
455 chip->read_buf(mtd, p, eccsize);
456 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
457
458 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
459 if (stat < 0)
460 mtd->ecc_stats.failed++;
461 else
462 mtd->ecc_stats.corrected += stat;
463 }
464
465 /* restore ECC layout */
466 if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
467 chip->ecc.layout = saved_ecc_layout;
468 mtd->oobavail = saved_ecc_layout->oobavail;
469 }
470
471 return 0;
472 }
473 #endif /* CONFIG_KEYSTONE_RBL_NAND */
474
nand_davinci_4bit_enable_hwecc(struct mtd_info * mtd,int mode)475 static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
476 {
477 u32 val;
478
479 switch (mode) {
480 case NAND_ECC_WRITE:
481 case NAND_ECC_READ:
482 /*
483 * Start a new ECC calculation for reading or writing 512 bytes
484 * of data.
485 */
486 val = __raw_readl(&davinci_emif_regs->nandfcr);
487 val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
488 val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
489 val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS);
490 val |= DAVINCI_NANDFCR_4BIT_ECC_START;
491 __raw_writel(val, &davinci_emif_regs->nandfcr);
492 break;
493 case NAND_ECC_READSYN:
494 val = __raw_readl(&davinci_emif_regs->nand4bitecc[0]);
495 break;
496 default:
497 break;
498 }
499 }
500
nand_davinci_4bit_readecc(struct mtd_info * mtd,unsigned int ecc[4])501 static u32 nand_davinci_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4])
502 {
503 int i;
504
505 for (i = 0; i < 4; i++) {
506 ecc[i] = __raw_readl(&davinci_emif_regs->nand4bitecc[i]) &
507 NAND_4BITECC_MASK;
508 }
509
510 return 0;
511 }
512
nand_davinci_4bit_calculate_ecc(struct mtd_info * mtd,const uint8_t * dat,uint8_t * ecc_code)513 static int nand_davinci_4bit_calculate_ecc(struct mtd_info *mtd,
514 const uint8_t *dat,
515 uint8_t *ecc_code)
516 {
517 unsigned int hw_4ecc[4];
518 unsigned int i;
519
520 nand_davinci_4bit_readecc(mtd, hw_4ecc);
521
522 /*Convert 10 bit ecc value to 8 bit */
523 for (i = 0; i < 2; i++) {
524 unsigned int hw_ecc_low = hw_4ecc[i * 2];
525 unsigned int hw_ecc_hi = hw_4ecc[(i * 2) + 1];
526
527 /* Take first 8 bits from val1 (count1=0) or val5 (count1=1) */
528 *ecc_code++ = hw_ecc_low & 0xFF;
529
530 /*
531 * Take 2 bits as LSB bits from val1 (count1=0) or val5
532 * (count1=1) and 6 bits from val2 (count1=0) or
533 * val5 (count1=1)
534 */
535 *ecc_code++ =
536 ((hw_ecc_low >> 8) & 0x3) | ((hw_ecc_low >> 14) & 0xFC);
537
538 /*
539 * Take 4 bits from val2 (count1=0) or val5 (count1=1) and
540 * 4 bits from val3 (count1=0) or val6 (count1=1)
541 */
542 *ecc_code++ =
543 ((hw_ecc_low >> 22) & 0xF) | ((hw_ecc_hi << 4) & 0xF0);
544
545 /*
546 * Take 6 bits from val3(count1=0) or val6 (count1=1) and
547 * 2 bits from val4 (count1=0) or val7 (count1=1)
548 */
549 *ecc_code++ =
550 ((hw_ecc_hi >> 4) & 0x3F) | ((hw_ecc_hi >> 10) & 0xC0);
551
552 /* Take 8 bits from val4 (count1=0) or val7 (count1=1) */
553 *ecc_code++ = (hw_ecc_hi >> 18) & 0xFF;
554 }
555
556 return 0;
557 }
558
nand_davinci_4bit_correct_data(struct mtd_info * mtd,uint8_t * dat,uint8_t * read_ecc,uint8_t * calc_ecc)559 static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
560 uint8_t *read_ecc, uint8_t *calc_ecc)
561 {
562 int i;
563 unsigned int hw_4ecc[4];
564 unsigned int iserror;
565 unsigned short *ecc16;
566 unsigned int numerrors, erroraddress, errorvalue;
567 u32 val;
568
569 /*
570 * Check for an ECC where all bytes are 0xFF. If this is the case, we
571 * will assume we are looking at an erased page and we should ignore
572 * the ECC.
573 */
574 for (i = 0; i < 10; i++) {
575 if (read_ecc[i] != 0xFF)
576 break;
577 }
578 if (i == 10)
579 return 0;
580
581 /* Convert 8 bit in to 10 bit */
582 ecc16 = (unsigned short *)&read_ecc[0];
583
584 /*
585 * Write the parity values in the NAND Flash 4-bit ECC Load register.
586 * Write each parity value one at a time starting from 4bit_ecc_val8
587 * to 4bit_ecc_val1.
588 */
589
590 /*Take 2 bits from 8th byte and 8 bits from 9th byte */
591 __raw_writel(((ecc16[4]) >> 6) & 0x3FF,
592 &davinci_emif_regs->nand4biteccload);
593
594 /* Take 4 bits from 7th byte and 6 bits from 8th byte */
595 __raw_writel((((ecc16[3]) >> 12) & 0xF) | ((((ecc16[4])) << 4) & 0x3F0),
596 &davinci_emif_regs->nand4biteccload);
597
598 /* Take 6 bits from 6th byte and 4 bits from 7th byte */
599 __raw_writel((ecc16[3] >> 2) & 0x3FF,
600 &davinci_emif_regs->nand4biteccload);
601
602 /* Take 8 bits from 5th byte and 2 bits from 6th byte */
603 __raw_writel(((ecc16[2]) >> 8) | ((((ecc16[3])) << 8) & 0x300),
604 &davinci_emif_regs->nand4biteccload);
605
606 /*Take 2 bits from 3rd byte and 8 bits from 4th byte */
607 __raw_writel((((ecc16[1]) >> 14) & 0x3) | ((((ecc16[2])) << 2) & 0x3FC),
608 &davinci_emif_regs->nand4biteccload);
609
610 /* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */
611 __raw_writel(((ecc16[1]) >> 4) & 0x3FF,
612 &davinci_emif_regs->nand4biteccload);
613
614 /* Take 6 bits from 1st byte and 4 bits from 2nd byte */
615 __raw_writel((((ecc16[0]) >> 10) & 0x3F) | (((ecc16[1]) << 6) & 0x3C0),
616 &davinci_emif_regs->nand4biteccload);
617
618 /* Take 10 bits from 0th and 1st bytes */
619 __raw_writel((ecc16[0]) & 0x3FF,
620 &davinci_emif_regs->nand4biteccload);
621
622 /*
623 * Perform a dummy read to the EMIF Revision Code and Status register.
624 * This is required to ensure time for syndrome calculation after
625 * writing the ECC values in previous step.
626 */
627
628 val = __raw_readl(&davinci_emif_regs->nandfsr);
629
630 /*
631 * Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers.
632 * A syndrome value of 0 means no bit errors. If the syndrome is
633 * non-zero then go further otherwise return.
634 */
635 nand_davinci_4bit_readecc(mtd, hw_4ecc);
636
637 if (!(hw_4ecc[0] | hw_4ecc[1] | hw_4ecc[2] | hw_4ecc[3]))
638 return 0;
639
640 /*
641 * Clear any previous address calculation by doing a dummy read of an
642 * error address register.
643 */
644 val = __raw_readl(&davinci_emif_regs->nanderradd1);
645
646 /*
647 * Set the addr_calc_st bit(bit no 13) in the NAND Flash Control
648 * register to 1.
649 */
650 __raw_writel(DAVINCI_NANDFCR_4BIT_CALC_START,
651 &davinci_emif_regs->nandfcr);
652
653 /*
654 * Wait for the corr_state field (bits 8 to 11) in the
655 * NAND Flash Status register to be not equal to 0x0, 0x1, 0x2, or 0x3.
656 * Otherwise ECC calculation has not even begun and the next loop might
657 * fail because of a false positive!
658 */
659 i = NAND_TIMEOUT;
660 do {
661 val = __raw_readl(&davinci_emif_regs->nandfsr);
662 val &= 0xc00;
663 i--;
664 } while ((i > 0) && !val);
665
666 /*
667 * Wait for the corr_state field (bits 8 to 11) in the
668 * NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3.
669 */
670 i = NAND_TIMEOUT;
671 do {
672 val = __raw_readl(&davinci_emif_regs->nandfsr);
673 val &= 0xc00;
674 i--;
675 } while ((i > 0) && val);
676
677 iserror = __raw_readl(&davinci_emif_regs->nandfsr);
678 iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
679 iserror = iserror >> 8;
680
681 /*
682 * ECC_STATE_TOO_MANY_ERRS (0x1) means errors cannot be
683 * corrected (five or more errors). The number of errors
684 * calculated (err_num field) differs from the number of errors
685 * searched. ECC_STATE_ERR_CORR_COMP_P (0x2) means error
686 * correction complete (errors on bit 8 or 9).
687 * ECC_STATE_ERR_CORR_COMP_N (0x3) means error correction
688 * complete (error exists).
689 */
690
691 if (iserror == ECC_STATE_NO_ERR) {
692 val = __raw_readl(&davinci_emif_regs->nanderrval1);
693 return 0;
694 } else if (iserror == ECC_STATE_TOO_MANY_ERRS) {
695 val = __raw_readl(&davinci_emif_regs->nanderrval1);
696 return -EBADMSG;
697 }
698
699 numerrors = ((__raw_readl(&davinci_emif_regs->nandfsr) >> 16)
700 & 0x3) + 1;
701
702 /* Read the error address, error value and correct */
703 for (i = 0; i < numerrors; i++) {
704 if (i > 1) {
705 erroraddress =
706 ((__raw_readl(&davinci_emif_regs->nanderradd2) >>
707 (16 * (i & 1))) & 0x3FF);
708 erroraddress = ((512 + 7) - erroraddress);
709 errorvalue =
710 ((__raw_readl(&davinci_emif_regs->nanderrval2) >>
711 (16 * (i & 1))) & 0xFF);
712 } else {
713 erroraddress =
714 ((__raw_readl(&davinci_emif_regs->nanderradd1) >>
715 (16 * (i & 1))) & 0x3FF);
716 erroraddress = ((512 + 7) - erroraddress);
717 errorvalue =
718 ((__raw_readl(&davinci_emif_regs->nanderrval1) >>
719 (16 * (i & 1))) & 0xFF);
720 }
721 /* xor the corrupt data with error value */
722 if (erroraddress < 512)
723 dat[erroraddress] ^= errorvalue;
724 }
725
726 return numerrors;
727 }
728 #endif /* CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST */
729
nand_davinci_dev_ready(struct mtd_info * mtd)730 static int nand_davinci_dev_ready(struct mtd_info *mtd)
731 {
732 return __raw_readl(&davinci_emif_regs->nandfsr) & 0x1;
733 }
734
davinci_nand_init(struct nand_chip * nand)735 static void davinci_nand_init(struct nand_chip *nand)
736 {
737 #if defined CONFIG_KEYSTONE_RBL_NAND
738 int i;
739 struct nand_ecclayout *layout;
740
741 layout = &nand_keystone_rbl_4bit_layout_oobfirst;
742 layout->oobavail = 0;
743 for (i = 0; i < ARRAY_SIZE(layout->oobfree) &&
744 layout->oobfree[i].length; i++)
745 layout->oobavail += layout->oobfree[i].length;
746
747 nand->write_page = nand_davinci_write_page;
748 nand->ecc.read_page = nand_davinci_read_page_hwecc;
749 #endif
750 nand->chip_delay = 0;
751 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
752 nand->bbt_options |= NAND_BBT_USE_FLASH;
753 #endif
754 #ifdef CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
755 nand->options |= NAND_NO_SUBPAGE_WRITE;
756 #endif
757 #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
758 nand->options |= NAND_BUSWIDTH_16;
759 #endif
760 #ifdef CONFIG_SYS_NAND_HW_ECC
761 nand->ecc.mode = NAND_ECC_HW;
762 nand->ecc.size = 512;
763 nand->ecc.bytes = 3;
764 nand->ecc.strength = 1;
765 nand->ecc.calculate = nand_davinci_calculate_ecc;
766 nand->ecc.correct = nand_davinci_correct_data;
767 nand->ecc.hwctl = nand_davinci_enable_hwecc;
768 #else
769 nand->ecc.mode = NAND_ECC_SOFT;
770 #endif /* CONFIG_SYS_NAND_HW_ECC */
771 #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
772 nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;
773 nand->ecc.size = 512;
774 nand->ecc.bytes = 10;
775 nand->ecc.strength = 4;
776 nand->ecc.calculate = nand_davinci_4bit_calculate_ecc;
777 nand->ecc.correct = nand_davinci_4bit_correct_data;
778 nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc;
779 nand->ecc.layout = &nand_davinci_4bit_layout_oobfirst;
780 #endif
781 /* Set address of hardware control function */
782 nand->cmd_ctrl = nand_davinci_hwcontrol;
783
784 nand->read_buf = nand_davinci_read_buf;
785 nand->write_buf = nand_davinci_write_buf;
786
787 nand->dev_ready = nand_davinci_dev_ready;
788 }
789
790 #ifdef CONFIG_SYS_NAND_SELF_INIT
davinci_nand_probe(struct udevice * dev)791 static int davinci_nand_probe(struct udevice *dev)
792 {
793 struct nand_chip *nand = dev_get_priv(dev);
794 struct mtd_info *mtd = nand_to_mtd(nand);
795 int ret;
796
797 nand->IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
798 nand->IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
799
800 davinci_nand_init(nand);
801
802 ret = nand_scan(mtd, CONFIG_SYS_NAND_MAX_CHIPS);
803 if (ret)
804 return ret;
805
806 return nand_register(0, mtd);
807 }
808
809 static const struct udevice_id davinci_nand_ids[] = {
810 { .compatible = "ti,davinci-nand" },
811 { }
812 };
813
814 U_BOOT_DRIVER(davinci_nand) = {
815 .name = "davinci-nand",
816 .id = UCLASS_MTD,
817 .of_match = davinci_nand_ids,
818 .probe = davinci_nand_probe,
819 .priv_auto = sizeof(struct nand_chip),
820 };
821
board_nand_init(void)822 void board_nand_init(void)
823 {
824 struct udevice *dev;
825 int ret;
826
827 ret = uclass_get_device_by_driver(UCLASS_MTD,
828 DM_DRIVER_GET(davinci_nand), &dev);
829 if (ret && ret != -ENODEV)
830 pr_err("Failed to initialize %s: %d\n", dev->name, ret);
831 }
832 #else
833 int board_nand_init(struct nand_chip *chip) __attribute__((weak));
board_nand_init(struct nand_chip * chip)834 int board_nand_init(struct nand_chip *chip)
835 {
836 davinci_nand_init(chip);
837 return 0;
838 }
839 #endif /* CONFIG_SYS_NAND_SELF_INIT */
840