1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (C) 2020 Renesas Electronics Corp.
4  */
5 #ifndef __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__
6 #define __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__
7 
8 #include <dt-bindings/clock/renesas-cpg-mssr.h>
9 
10 /* r8a774c0 CPG Core Clocks */
11 #define R8A774C0_CLK_Z2			0
12 #define R8A774C0_CLK_ZG			1
13 #define R8A774C0_CLK_ZTR		2
14 #define R8A774C0_CLK_ZT			3
15 #define R8A774C0_CLK_ZX			4
16 #define R8A774C0_CLK_S0D1		5
17 #define R8A774C0_CLK_S0D3		6
18 #define R8A774C0_CLK_S0D6		7
19 #define R8A774C0_CLK_S0D12		8
20 #define R8A774C0_CLK_S0D24		9
21 #define R8A774C0_CLK_S1D1		10
22 #define R8A774C0_CLK_S1D2		11
23 #define R8A774C0_CLK_S1D4		12
24 #define R8A774C0_CLK_S2D1		13
25 #define R8A774C0_CLK_S2D2		14
26 #define R8A774C0_CLK_S2D4		15
27 #define R8A774C0_CLK_S3D1		16
28 #define R8A774C0_CLK_S3D2		17
29 #define R8A774C0_CLK_S3D4		18
30 #define R8A774C0_CLK_S0D6C		19
31 #define R8A774C0_CLK_S3D1C		20
32 #define R8A774C0_CLK_S3D2C		21
33 #define R8A774C0_CLK_S3D4C		22
34 #define R8A774C0_CLK_LB			23
35 #define R8A774C0_CLK_CL			24
36 #define R8A774C0_CLK_ZB3		25
37 #define R8A774C0_CLK_ZB3D2		26
38 #define R8A774C0_CLK_CR			27
39 #define R8A774C0_CLK_CRD2		28
40 #define R8A774C0_CLK_SD0H		29
41 #define R8A774C0_CLK_SD0		30
42 #define R8A774C0_CLK_SD1H		31
43 #define R8A774C0_CLK_SD1		32
44 #define R8A774C0_CLK_SD3H		33
45 #define R8A774C0_CLK_SD3		34
46 #define R8A774C0_CLK_RPC		35
47 #define R8A774C0_CLK_RPCD2		36
48 #define R8A774C0_CLK_ZA2		37
49 #define R8A774C0_CLK_ZA8		38
50 #define R8A774C0_CLK_Z2D		39
51 #define R8A774C0_CLK_MSO		40
52 #define R8A774C0_CLK_R			41
53 #define R8A774C0_CLK_OSC		42
54 #define R8A774C0_CLK_LV0		43
55 #define R8A774C0_CLK_LV1		44
56 #define R8A774C0_CLK_CSI0		45
57 #define R8A774C0_CLK_CP			46
58 #define R8A774C0_CLK_CPEX		47
59 #define R8A774C0_CLK_CANFD		48
60 
61 #endif /* __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__ */
62