1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Davinci MMC Controller Driver
4 *
5 * Copyright (C) 2010 Texas Instruments Incorporated
6 */
7
8 #include <config.h>
9 #include <common.h>
10 #include <dm.h>
11 #include <errno.h>
12 #include <mmc.h>
13 #include <command.h>
14 #include <part.h>
15 #include <malloc.h>
16 #include <asm/io.h>
17 #include <asm/arch/sdmmc_defs.h>
18 #include <asm-generic/gpio.h>
19 #include <linux/delay.h>
20
21 #define WATCHDOG_COUNT (100000)
22
23 #define get_val(addr) REG(addr)
24 #define set_val(addr, val) REG(addr) = (val)
25 #define set_bit(addr, val) set_val((addr), (get_val(addr) | (val)))
26 #define clear_bit(addr, val) set_val((addr), (get_val(addr) & ~(val)))
27
28 #ifdef CONFIG_DM_MMC
29 /* Davinci MMC board definitions */
30 struct davinci_mmc_priv {
31 struct davinci_mmc_regs *reg_base; /* Register base address */
32 uint input_clk; /* Input clock to MMC controller */
33 struct gpio_desc cd_gpio; /* Card Detect GPIO */
34 struct gpio_desc wp_gpio; /* Write Protect GPIO */
35 };
36 #endif
37
38 /* Set davinci clock prescalar value based on the required clock in HZ */
39 #if !CONFIG_IS_ENABLED(DM_MMC)
dmmc_set_clock(struct mmc * mmc,uint clock)40 static void dmmc_set_clock(struct mmc *mmc, uint clock)
41 {
42 struct davinci_mmc *host = mmc->priv;
43 #else
44
45 static void davinci_mmc_set_clock(struct udevice *dev, uint clock)
46 {
47 struct davinci_mmc_priv *host = dev_get_priv(dev);
48 struct mmc *mmc = mmc_get_mmc_dev(dev);
49 #endif
50 struct davinci_mmc_regs *regs = host->reg_base;
51 uint clkrt, sysclk2, act_clock;
52
53 if (clock < mmc->cfg->f_min)
54 clock = mmc->cfg->f_min;
55 if (clock > mmc->cfg->f_max)
56 clock = mmc->cfg->f_max;
57
58 set_val(®s->mmcclk, 0);
59 sysclk2 = host->input_clk;
60 clkrt = (sysclk2 / (2 * clock)) - 1;
61
62 /* Calculate the actual clock for the divider used */
63 act_clock = (sysclk2 / (2 * (clkrt + 1)));
64
65 /* Adjust divider if actual clock exceeds the required clock */
66 if (act_clock > clock)
67 clkrt++;
68
69 /* check clock divider boundary and correct it */
70 if (clkrt > 0xFF)
71 clkrt = 0xFF;
72
73 set_val(®s->mmcclk, (clkrt | MMCCLK_CLKEN));
74 }
75
76 /* Status bit wait loop for MMCST1 */
77 static int
78 dmmc_wait_fifo_status(volatile struct davinci_mmc_regs *regs, uint status)
79 {
80 uint wdog = WATCHDOG_COUNT;
81
82 while (--wdog && ((get_val(®s->mmcst1) & status) != status))
83 udelay(10);
84
85 if (!(get_val(®s->mmcctl) & MMCCTL_WIDTH_4_BIT))
86 udelay(100);
87
88 if (wdog == 0)
89 return -ECOMM;
90
91 return 0;
92 }
93
94 /* Busy bit wait loop for MMCST1 */
95 static int dmmc_busy_wait(volatile struct davinci_mmc_regs *regs)
96 {
97 uint wdog = WATCHDOG_COUNT;
98
99 while (--wdog && (get_val(®s->mmcst1) & MMCST1_BUSY))
100 udelay(10);
101
102 if (wdog == 0)
103 return -ECOMM;
104
105 return 0;
106 }
107
108 /* Status bit wait loop for MMCST0 - Checks for error bits as well */
109 static int dmmc_check_status(volatile struct davinci_mmc_regs *regs,
110 uint *cur_st, uint st_ready, uint st_error)
111 {
112 uint wdog = WATCHDOG_COUNT;
113 uint mmcstatus = *cur_st;
114
115 while (wdog--) {
116 if (mmcstatus & st_ready) {
117 *cur_st = mmcstatus;
118 mmcstatus = get_val(®s->mmcst1);
119 return 0;
120 } else if (mmcstatus & st_error) {
121 if (mmcstatus & MMCST0_TOUTRS)
122 return -ETIMEDOUT;
123 printf("[ ST0 ERROR %x]\n", mmcstatus);
124 /*
125 * Ignore CRC errors as some MMC cards fail to
126 * initialize on DM365-EVM on the SD1 slot
127 */
128 if (mmcstatus & MMCST0_CRCRS)
129 return 0;
130 return -ECOMM;
131 }
132 udelay(10);
133
134 mmcstatus = get_val(®s->mmcst0);
135 }
136
137 printf("Status %x Timeout ST0:%x ST1:%x\n", st_ready, mmcstatus,
138 get_val(®s->mmcst1));
139 return -ECOMM;
140 }
141
142 /*
143 * Sends a command out on the bus. Takes the device pointer,
144 * a command pointer, and an optional data pointer.
145 */
146 #if !CONFIG_IS_ENABLED(DM_MMC)
147 static int dmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
148 {
149 struct davinci_mmc *host = mmc->priv;
150 #else
151 static int
152 davinci_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, struct mmc_data *data)
153 {
154 struct davinci_mmc_priv *host = dev_get_priv(dev);
155 #endif
156 volatile struct davinci_mmc_regs *regs = host->reg_base;
157 uint mmcstatus, status_rdy, status_err;
158 uint i, cmddata, bytes_left = 0;
159 int fifo_words, fifo_bytes, err;
160 char *data_buf = NULL;
161
162 /* Clear status registers */
163 mmcstatus = get_val(®s->mmcst0);
164 fifo_words = 16;
165 fifo_bytes = fifo_words << 2;
166
167 /* Wait for any previous busy signal to be cleared */
168 dmmc_busy_wait(regs);
169
170 cmddata = cmd->cmdidx;
171 cmddata |= MMCCMD_PPLEN;
172
173 /* Send init clock for CMD0 */
174 if (cmd->cmdidx == MMC_CMD_GO_IDLE_STATE)
175 cmddata |= MMCCMD_INITCK;
176
177 switch (cmd->resp_type) {
178 case MMC_RSP_R1b:
179 cmddata |= MMCCMD_BSYEXP;
180 /* Fall-through */
181 case MMC_RSP_R1: /* R1, R1b, R5, R6, R7 */
182 cmddata |= MMCCMD_RSPFMT_R1567;
183 break;
184 case MMC_RSP_R2:
185 cmddata |= MMCCMD_RSPFMT_R2;
186 break;
187 case MMC_RSP_R3: /* R3, R4 */
188 cmddata |= MMCCMD_RSPFMT_R3;
189 break;
190 }
191
192 set_val(®s->mmcim, 0);
193
194 if (data) {
195 /* clear previous data transfer if any and set new one */
196 bytes_left = (data->blocksize * data->blocks);
197
198 /* Reset FIFO - Always use 32 byte fifo threshold */
199 set_val(®s->mmcfifoctl,
200 (MMCFIFOCTL_FIFOLEV | MMCFIFOCTL_FIFORST));
201
202 cmddata |= MMCCMD_DMATRIG;
203
204 cmddata |= MMCCMD_WDATX;
205 if (data->flags == MMC_DATA_READ) {
206 set_val(®s->mmcfifoctl, MMCFIFOCTL_FIFOLEV);
207 } else if (data->flags == MMC_DATA_WRITE) {
208 set_val(®s->mmcfifoctl,
209 (MMCFIFOCTL_FIFOLEV |
210 MMCFIFOCTL_FIFODIR));
211 cmddata |= MMCCMD_DTRW;
212 }
213
214 set_val(®s->mmctod, 0xFFFF);
215 set_val(®s->mmcnblk, (data->blocks & MMCNBLK_NBLK_MASK));
216 set_val(®s->mmcblen, (data->blocksize & MMCBLEN_BLEN_MASK));
217
218 if (data->flags == MMC_DATA_WRITE) {
219 uint val;
220 data_buf = (char *)data->src;
221 /* For write, fill FIFO with data before issue of CMD */
222 for (i = 0; (i < fifo_words) && bytes_left; i++) {
223 memcpy((char *)&val, data_buf, 4);
224 set_val(®s->mmcdxr, val);
225 data_buf += 4;
226 bytes_left -= 4;
227 }
228 }
229 } else {
230 set_val(®s->mmcblen, 0);
231 set_val(®s->mmcnblk, 0);
232 }
233
234 set_val(®s->mmctor, 0x1FFF);
235
236 /* Send the command */
237 set_val(®s->mmcarghl, cmd->cmdarg);
238 set_val(®s->mmccmd, cmddata);
239
240 status_rdy = MMCST0_RSPDNE;
241 status_err = (MMCST0_TOUTRS | MMCST0_TOUTRD |
242 MMCST0_CRCWR | MMCST0_CRCRD);
243 if (cmd->resp_type & MMC_RSP_CRC)
244 status_err |= MMCST0_CRCRS;
245
246 mmcstatus = get_val(®s->mmcst0);
247 err = dmmc_check_status(regs, &mmcstatus, status_rdy, status_err);
248 if (err)
249 return err;
250
251 /* For R1b wait for busy done */
252 if (cmd->resp_type == MMC_RSP_R1b)
253 dmmc_busy_wait(regs);
254
255 /* Collect response from controller for specific commands */
256 if (mmcstatus & MMCST0_RSPDNE) {
257 /* Copy the response to the response buffer */
258 if (cmd->resp_type & MMC_RSP_136) {
259 cmd->response[0] = get_val(®s->mmcrsp67);
260 cmd->response[1] = get_val(®s->mmcrsp45);
261 cmd->response[2] = get_val(®s->mmcrsp23);
262 cmd->response[3] = get_val(®s->mmcrsp01);
263 } else if (cmd->resp_type & MMC_RSP_PRESENT) {
264 cmd->response[0] = get_val(®s->mmcrsp67);
265 }
266 }
267
268 if (data == NULL)
269 return 0;
270
271 if (data->flags == MMC_DATA_READ) {
272 /* check for DATDNE along with DRRDY as the controller might
273 * set the DATDNE without DRRDY for smaller transfers with
274 * less than FIFO threshold bytes
275 */
276 status_rdy = MMCST0_DRRDY | MMCST0_DATDNE;
277 status_err = MMCST0_TOUTRD | MMCST0_CRCRD;
278 data_buf = data->dest;
279 } else {
280 status_rdy = MMCST0_DXRDY | MMCST0_DATDNE;
281 status_err = MMCST0_CRCWR;
282 }
283
284 /* Wait until all of the blocks are transferred */
285 while (bytes_left) {
286 err = dmmc_check_status(regs, &mmcstatus, status_rdy,
287 status_err);
288 if (err)
289 return err;
290
291 if (data->flags == MMC_DATA_READ) {
292 /*
293 * MMC controller sets the Data receive ready bit
294 * (DRRDY) in MMCST0 even before the entire FIFO is
295 * full. This results in erratic behavior if we start
296 * reading the FIFO soon after DRRDY. Wait for the
297 * FIFO full bit in MMCST1 for proper FIFO clearing.
298 */
299 if (bytes_left > fifo_bytes)
300 dmmc_wait_fifo_status(regs, 0x4a);
301 else if (bytes_left == fifo_bytes) {
302 dmmc_wait_fifo_status(regs, 0x40);
303 if (cmd->cmdidx == MMC_CMD_SEND_EXT_CSD)
304 udelay(600);
305 }
306
307 for (i = 0; bytes_left && (i < fifo_words); i++) {
308 cmddata = get_val(®s->mmcdrr);
309 memcpy(data_buf, (char *)&cmddata, 4);
310 data_buf += 4;
311 bytes_left -= 4;
312 }
313 } else {
314 /*
315 * MMC controller sets the Data transmit ready bit
316 * (DXRDY) in MMCST0 even before the entire FIFO is
317 * empty. This results in erratic behavior if we start
318 * writing the FIFO soon after DXRDY. Wait for the
319 * FIFO empty bit in MMCST1 for proper FIFO clearing.
320 */
321 dmmc_wait_fifo_status(regs, MMCST1_FIFOEMP);
322 for (i = 0; bytes_left && (i < fifo_words); i++) {
323 memcpy((char *)&cmddata, data_buf, 4);
324 set_val(®s->mmcdxr, cmddata);
325 data_buf += 4;
326 bytes_left -= 4;
327 }
328 dmmc_busy_wait(regs);
329 }
330 }
331
332 err = dmmc_check_status(regs, &mmcstatus, MMCST0_DATDNE, status_err);
333 if (err)
334 return err;
335
336 return 0;
337 }
338
339 /* Initialize Davinci MMC controller */
340 #if !CONFIG_IS_ENABLED(DM_MMC)
341 static int dmmc_init(struct mmc *mmc)
342 {
343 struct davinci_mmc *host = mmc->priv;
344 #else
345 static int davinci_dm_mmc_init(struct udevice *dev)
346 {
347 struct davinci_mmc_priv *host = dev_get_priv(dev);
348 #endif
349 struct davinci_mmc_regs *regs = host->reg_base;
350
351 /* Clear status registers explicitly - soft reset doesn't clear it
352 * If Uboot is invoked from UBL with SDMMC Support, the status
353 * registers can have uncleared bits
354 */
355 get_val(®s->mmcst0);
356 get_val(®s->mmcst1);
357
358 /* Hold software reset */
359 set_bit(®s->mmcctl, MMCCTL_DATRST);
360 set_bit(®s->mmcctl, MMCCTL_CMDRST);
361 udelay(10);
362
363 set_val(®s->mmcclk, 0x0);
364 set_val(®s->mmctor, 0x1FFF);
365 set_val(®s->mmctod, 0xFFFF);
366
367 /* Clear software reset */
368 clear_bit(®s->mmcctl, MMCCTL_DATRST);
369 clear_bit(®s->mmcctl, MMCCTL_CMDRST);
370
371 udelay(10);
372
373 /* Reset FIFO - Always use the maximum fifo threshold */
374 set_val(®s->mmcfifoctl, (MMCFIFOCTL_FIFOLEV | MMCFIFOCTL_FIFORST));
375 set_val(®s->mmcfifoctl, MMCFIFOCTL_FIFOLEV);
376
377 return 0;
378 }
379
380 /* Set buswidth or clock as indicated by the MMC framework */
381 #if !CONFIG_IS_ENABLED(DM_MMC)
382 static int dmmc_set_ios(struct mmc *mmc)
383 {
384 struct davinci_mmc *host = mmc->priv;
385 struct davinci_mmc_regs *regs = host->reg_base;
386 #else
387 static int davinci_mmc_set_ios(struct udevice *dev)
388 {
389 struct mmc *mmc = mmc_get_mmc_dev(dev);
390
391 struct davinci_mmc_priv *host = dev_get_priv(dev);
392 struct davinci_mmc_regs *regs = host->reg_base;
393 #endif
394 /* Set the bus width */
395 if (mmc->bus_width == 4)
396 set_bit(®s->mmcctl, MMCCTL_WIDTH_4_BIT);
397 else
398 clear_bit(®s->mmcctl, MMCCTL_WIDTH_4_BIT);
399
400 /* Set clock speed */
401 if (mmc->clock) {
402 #if !CONFIG_IS_ENABLED(DM_MMC)
403 dmmc_set_clock(mmc, mmc->clock);
404 #else
405 davinci_mmc_set_clock(dev, mmc->clock);
406 #endif
407 }
408 return 0;
409 }
410
411 #if !CONFIG_IS_ENABLED(DM_MMC)
412 static const struct mmc_ops dmmc_ops = {
413 .send_cmd = dmmc_send_cmd,
414 .set_ios = dmmc_set_ios,
415 .init = dmmc_init,
416 };
417 #else
418
419 static int davinci_mmc_getcd(struct udevice *dev)
420 {
421 int value = -1;
422 #if CONFIG_IS_ENABLED(DM_GPIO)
423 struct davinci_mmc_priv *priv = dev_get_priv(dev);
424 value = dm_gpio_get_value(&priv->cd_gpio);
425 #endif
426 /* if no CD return as 1 */
427 if (value < 0)
428 return 1;
429
430 return value;
431 }
432
433 static int davinci_mmc_getwp(struct udevice *dev)
434 {
435 int value = -1;
436 #if CONFIG_IS_ENABLED(DM_GPIO)
437 struct davinci_mmc_priv *priv = dev_get_priv(dev);
438
439 value = dm_gpio_get_value(&priv->wp_gpio);
440 #endif
441 /* if no WP return as 0 */
442 if (value < 0)
443 return 0;
444
445 return value;
446 }
447
448 static const struct dm_mmc_ops davinci_mmc_ops = {
449 .send_cmd = davinci_mmc_send_cmd,
450 .set_ios = davinci_mmc_set_ios,
451 .get_cd = davinci_mmc_getcd,
452 .get_wp = davinci_mmc_getwp,
453 };
454 #endif
455
456 #if !CONFIG_IS_ENABLED(DM_MMC)
457 /* Called from board_mmc_init during startup. Can be called multiple times
458 * depending on the number of slots available on board and controller
459 */
460 int davinci_mmc_init(struct bd_info *bis, struct davinci_mmc *host)
461 {
462 host->cfg.name = "davinci";
463 host->cfg.ops = &dmmc_ops;
464 host->cfg.f_min = 200000;
465 host->cfg.f_max = 25000000;
466 host->cfg.voltages = host->voltages;
467 host->cfg.host_caps = host->host_caps;
468
469 host->cfg.b_max = DAVINCI_MAX_BLOCKS;
470
471 mmc_create(&host->cfg, host);
472
473 return 0;
474 }
475 #else
476
477
478 static int davinci_mmc_probe(struct udevice *dev)
479 {
480 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
481 struct davinci_mmc_plat *plat = dev_get_plat(dev);
482 struct davinci_mmc_priv *priv = dev_get_priv(dev);
483
484 priv->reg_base = plat->reg_base;
485 priv->input_clk = clk_get(DAVINCI_MMCSD_CLKID);
486 #if CONFIG_IS_ENABLED(DM_GPIO)
487 /* These GPIOs are optional */
488 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
489 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
490 #endif
491 upriv->mmc = &plat->mmc;
492
493 return davinci_dm_mmc_init(dev);
494 }
495
496 static int davinci_mmc_bind(struct udevice *dev)
497 {
498 struct davinci_mmc_plat *plat = dev_get_plat(dev);
499
500 return mmc_bind(dev, &plat->mmc, &plat->cfg);
501 }
502
503 #if CONFIG_IS_ENABLED(OF_CONTROL)
504 static int davinci_mmc_of_to_plat(struct udevice *dev)
505 {
506 struct davinci_mmc_plat *plat = dev_get_plat(dev);
507 struct mmc_config *cfg = &plat->cfg;
508
509 plat->reg_base = (struct davinci_mmc_regs *)dev_read_addr(dev);
510 cfg->f_min = 200000;
511 cfg->f_max = 25000000;
512 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
513 cfg->host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */
514 cfg->b_max = DAVINCI_MAX_BLOCKS;
515 cfg->name = "da830-mmc";
516
517 return 0;
518 }
519
520 static const struct udevice_id davinci_mmc_ids[] = {
521 { .compatible = "ti,da830-mmc" },
522 {},
523 };
524 #endif
525 U_BOOT_DRIVER(ti_da830_mmc) = {
526 .name = "davinci_mmc",
527 .id = UCLASS_MMC,
528 #if CONFIG_IS_ENABLED(OF_CONTROL)
529 .of_match = davinci_mmc_ids,
530 .plat_auto = sizeof(struct davinci_mmc_plat),
531 .of_to_plat = davinci_mmc_of_to_plat,
532 #endif
533 #if CONFIG_BLK
534 .bind = davinci_mmc_bind,
535 #endif
536 .probe = davinci_mmc_probe,
537 .ops = &davinci_mmc_ops,
538 .priv_auto = sizeof(struct davinci_mmc_priv),
539 #if !CONFIG_IS_ENABLED(OF_CONTROL)
540 .flags = DM_FLAG_PRE_RELOC,
541 #endif
542 };
543 #endif
544