1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * NAND boot for Freescale Integrated Flash Controller, NAND FCM
4 *
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
7 */
8
9 #include <common.h>
10 #include <cpu_func.h>
11 #include <asm/io.h>
12 #include <fsl_ifc.h>
13 #include <part.h>
14 #include <linux/mtd/rawnand.h>
15 #ifdef CONFIG_CHAIN_OF_TRUST
16 #include <fsl_validate.h>
17 #endif
18
is_blank(uchar * addr,int page_size)19 static inline int is_blank(uchar *addr, int page_size)
20 {
21 int i;
22
23 for (i = 0; i < page_size; i++) {
24 if (__raw_readb(&addr[i]) != 0xff)
25 return 0;
26 }
27
28 /*
29 * For the SPL, don't worry about uncorrectable errors
30 * where the main area is all FFs but shouldn't be.
31 */
32 return 1;
33 }
34
35 /* returns nonzero if entire page is blank */
check_read_ecc(uchar * buf,u32 * eccstat,unsigned int bufnum,int page_size)36 static inline int check_read_ecc(uchar *buf, u32 *eccstat,
37 unsigned int bufnum, int page_size)
38 {
39 u32 reg = eccstat[bufnum / 4];
40 int errors = (reg >> ((3 - bufnum % 4) * 8)) & 0xf;
41
42 if (errors == 0xf) { /* uncorrectable */
43 /* Blank pages fail hw ECC checks */
44 if (is_blank(buf, page_size))
45 return 1;
46
47 puts("ecc error\n");
48 for (;;)
49 ;
50 }
51
52 return 0;
53 }
54
runtime_regs_address(void)55 static inline struct fsl_ifc_runtime *runtime_regs_address(void)
56 {
57 struct fsl_ifc regs = {(void *)CONFIG_SYS_IFC_ADDR, NULL};
58 int ver = 0;
59
60 ver = ifc_in32(®s.gregs->ifc_rev);
61 if (ver >= FSL_IFC_V2_0_0)
62 regs.rregs = (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET;
63 else
64 regs.rregs = (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET;
65
66 return regs.rregs;
67 }
68
nand_wait(uchar * buf,int bufnum,int page_size)69 static inline void nand_wait(uchar *buf, int bufnum, int page_size)
70 {
71 struct fsl_ifc_runtime *ifc = runtime_regs_address();
72 u32 status;
73 u32 eccstat[8];
74 int bufperpage = page_size / 512;
75 int bufnum_end, i;
76
77 bufnum *= bufperpage;
78 bufnum_end = bufnum + bufperpage - 1;
79
80 do {
81 status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
82 } while (!(status & IFC_NAND_EVTER_STAT_OPC));
83
84 if (status & IFC_NAND_EVTER_STAT_FTOER) {
85 puts("flash time out error\n");
86 for (;;)
87 ;
88 }
89
90 for (i = bufnum / 4; i <= bufnum_end / 4; i++)
91 eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]);
92
93 for (i = bufnum; i <= bufnum_end; i++) {
94 if (check_read_ecc(buf, eccstat, i, page_size))
95 break;
96 }
97
98 ifc_out32(&ifc->ifc_nand.nand_evter_stat, status);
99 }
100
bad_block(uchar * marker,int port_size)101 static inline int bad_block(uchar *marker, int port_size)
102 {
103 if (port_size == 8)
104 return __raw_readb(marker) != 0xff;
105 else
106 return __raw_readw((u16 *)marker) != 0xffff;
107 }
108
nand_spl_load_image(uint32_t offs,unsigned int uboot_size,void * vdst)109 int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
110 {
111 struct fsl_ifc_fcm *gregs = (void *)CONFIG_SYS_IFC_ADDR;
112 struct fsl_ifc_runtime *ifc = NULL;
113 uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
114 int page_size;
115 int port_size;
116 int pages_per_blk;
117 int blk_size;
118 int bad_marker = 0;
119 int bufnum_mask, bufnum, ver = 0;
120
121 int csor, cspr;
122 int pos = 0;
123 int j = 0;
124
125 int sram_addr;
126 int pg_no;
127 uchar *dst = vdst;
128
129 ifc = runtime_regs_address();
130
131 /* Get NAND Flash configuration */
132 csor = CONFIG_SYS_NAND_CSOR;
133 cspr = CONFIG_SYS_NAND_CSPR;
134
135 port_size = (cspr & CSPR_PORT_SIZE_16) ? 16 : 8;
136
137 if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_8K) {
138 page_size = 8192;
139 bufnum_mask = 0x0;
140 } else if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_4K) {
141 page_size = 4096;
142 bufnum_mask = 0x1;
143 } else if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_2K) {
144 page_size = 2048;
145 bufnum_mask = 0x3;
146 } else {
147 page_size = 512;
148 bufnum_mask = 0xf;
149
150 if (port_size == 8)
151 bad_marker = 5;
152 }
153
154 ver = ifc_in32(&gregs->ifc_rev);
155 if (ver >= FSL_IFC_V2_0_0)
156 bufnum_mask = (bufnum_mask * 2) + 1;
157
158 pages_per_blk =
159 32 << ((csor & CSOR_NAND_PB_MASK) >> CSOR_NAND_PB_SHIFT);
160
161 blk_size = pages_per_blk * page_size;
162
163 /* Open Full SRAM mapping for spare are access */
164 ifc_out32(&ifc->ifc_nand.ncfgr, 0x0);
165
166 /* Clear Boot events */
167 ifc_out32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff);
168
169 /* Program FIR/FCR for Large/Small page */
170 if (page_size > 512) {
171 ifc_out32(&ifc->ifc_nand.nand_fir0,
172 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
173 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
174 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
175 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
176 (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT));
177 ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
178
179 ifc_out32(&ifc->ifc_nand.nand_fcr0,
180 (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
181 (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
182 } else {
183 ifc_out32(&ifc->ifc_nand.nand_fir0,
184 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
185 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
186 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
187 (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT));
188 ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
189
190 ifc_out32(&ifc->ifc_nand.nand_fcr0,
191 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
192 }
193
194 /* Program FBCR = 0 for full page read */
195 ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
196
197 /* Read and copy u-boot on SDRAM from NAND device, In parallel
198 * check for Bad block if found skip it and read continue to
199 * next Block
200 */
201 while (pos < uboot_size) {
202 int i = 0;
203 do {
204 pg_no = offs / page_size;
205 bufnum = pg_no & bufnum_mask;
206 sram_addr = bufnum * page_size * 2;
207
208 ifc_out32(&ifc->ifc_nand.row0, pg_no);
209 ifc_out32(&ifc->ifc_nand.col0, 0);
210 /* start read */
211 ifc_out32(&ifc->ifc_nand.nandseq_strt,
212 IFC_NAND_SEQ_STRT_FIR_STRT);
213
214 /* wait for read to complete */
215 nand_wait(&buf[sram_addr], bufnum, page_size);
216
217 /*
218 * If either of the first two pages are marked bad,
219 * continue to the next block.
220 */
221 if (i++ < 2 &&
222 bad_block(&buf[sram_addr + page_size + bad_marker],
223 port_size)) {
224 puts("skipping\n");
225 offs = (offs + blk_size) & ~(blk_size - 1);
226 pos &= ~(blk_size - 1);
227 break;
228 }
229
230 for (j = 0; j < page_size; j++)
231 dst[pos + j] = __raw_readb(&buf[sram_addr + j]);
232
233 pos += page_size;
234 offs += page_size;
235 } while ((offs & (blk_size - 1)) && (pos < uboot_size));
236 }
237
238 return 0;
239 }
240
241 /*
242 * Main entrypoint for NAND Boot. It's necessary that SDRAM is already
243 * configured and available since this code loads the main U-Boot image
244 * from NAND into SDRAM and starts from there.
245 */
nand_boot(void)246 void nand_boot(void)
247 {
248 __attribute__((noreturn)) void (*uboot)(void);
249 /*
250 * Load U-Boot image from NAND into RAM
251 */
252 nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
253 CONFIG_SYS_NAND_U_BOOT_SIZE,
254 (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
255
256 #ifdef CONFIG_NAND_ENV_DST
257 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
258 (uchar *)CONFIG_NAND_ENV_DST);
259
260 #ifdef CONFIG_ENV_OFFSET_REDUND
261 nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
262 (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
263 #endif
264 #endif
265 /*
266 * Jump to U-Boot image
267 */
268 #ifdef CONFIG_SPL_FLUSH_IMAGE
269 /*
270 * Clean d-cache and invalidate i-cache, to
271 * make sure that no stale data is executed.
272 */
273 flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
274 #endif
275
276 #ifdef CONFIG_CHAIN_OF_TRUST
277 /*
278 * U-Boot header is appended at end of U-boot image, so
279 * calculate U-boot header address using U-boot header size.
280 */
281 #define CONFIG_U_BOOT_HDR_ADDR \
282 ((CONFIG_SYS_NAND_U_BOOT_START + \
283 CONFIG_SYS_NAND_U_BOOT_SIZE) - \
284 CONFIG_U_BOOT_HDR_SIZE)
285 spl_validate_uboot(CONFIG_U_BOOT_HDR_ADDR,
286 CONFIG_SYS_NAND_U_BOOT_START);
287 /*
288 * In case of failure in validation, spl_validate_uboot would
289 * not return back in case of Production environment with ITS=1.
290 * Thus U-Boot will not start.
291 * In Development environment (ITS=0 and SB_EN=1), the function
292 * may return back in case of non-fatal failures.
293 */
294 #endif
295
296 uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
297 uboot();
298 }
299
300 #ifndef CONFIG_SPL_NAND_INIT
nand_init(void)301 void nand_init(void)
302 {
303 }
304
nand_deselect(void)305 void nand_deselect(void)
306 {
307 }
308 #endif
309