1 /*
2 * Overview:
3 * This is the generic MTD driver for NAND flash devices. It should be
4 * capable of working with almost all NAND chips currently available.
5 *
6 * Additional technical information is available on
7 * http://www.linux-mtd.infradead.org/doc/nand.html
8 *
9 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
10 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
11 *
12 * Credits:
13 * David Woodhouse for adding multichip support
14 *
15 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
16 * rework for 2K page size chips
17 *
18 * TODO:
19 * Enable cached programming for 2k page size chips
20 * Check, if mtd->ecctype should be set to MTD_ECC_HW
21 * if we have HW ECC support.
22 * BBT table is not serialized, has to be fixed
23 *
24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License version 2 as
26 * published by the Free Software Foundation.
27 *
28 */
29
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <common.h>
32 #if CONFIG_IS_ENABLED(OF_CONTROL)
33 #include <fdtdec.h>
34 #endif
35 #include <log.h>
36 #include <malloc.h>
37 #include <watchdog.h>
38 #include <dm/devres.h>
39 #include <linux/bitops.h>
40 #include <linux/bug.h>
41 #include <linux/delay.h>
42 #include <linux/err.h>
43 #include <linux/compat.h>
44 #include <linux/mtd/mtd.h>
45 #include <linux/mtd/rawnand.h>
46 #include <linux/mtd/nand_ecc.h>
47 #include <linux/mtd/nand_bch.h>
48 #ifdef CONFIG_MTD_PARTITIONS
49 #include <linux/mtd/partitions.h>
50 #endif
51 #include <asm/io.h>
52 #include <linux/errno.h>
53
54 /* Define default oob placement schemes for large and small page devices */
55 #ifndef CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
56 static struct nand_ecclayout nand_oob_8 = {
57 .eccbytes = 3,
58 .eccpos = {0, 1, 2},
59 .oobfree = {
60 {.offset = 3,
61 .length = 2},
62 {.offset = 6,
63 .length = 2} }
64 };
65
66 static struct nand_ecclayout nand_oob_16 = {
67 .eccbytes = 6,
68 .eccpos = {0, 1, 2, 3, 6, 7},
69 .oobfree = {
70 {.offset = 8,
71 . length = 8} }
72 };
73
74 static struct nand_ecclayout nand_oob_64 = {
75 .eccbytes = 24,
76 .eccpos = {
77 40, 41, 42, 43, 44, 45, 46, 47,
78 48, 49, 50, 51, 52, 53, 54, 55,
79 56, 57, 58, 59, 60, 61, 62, 63},
80 .oobfree = {
81 {.offset = 2,
82 .length = 38} }
83 };
84
85 static struct nand_ecclayout nand_oob_128 = {
86 .eccbytes = 48,
87 .eccpos = {
88 80, 81, 82, 83, 84, 85, 86, 87,
89 88, 89, 90, 91, 92, 93, 94, 95,
90 96, 97, 98, 99, 100, 101, 102, 103,
91 104, 105, 106, 107, 108, 109, 110, 111,
92 112, 113, 114, 115, 116, 117, 118, 119,
93 120, 121, 122, 123, 124, 125, 126, 127},
94 .oobfree = {
95 {.offset = 2,
96 .length = 78} }
97 };
98 #endif
99
100 static int nand_get_device(struct mtd_info *mtd, int new_state);
101
102 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
103 struct mtd_oob_ops *ops);
104
105 /*
106 * For devices which display every fart in the system on a separate LED. Is
107 * compiled away when LED support is disabled.
108 */
109 DEFINE_LED_TRIGGER(nand_led_trigger);
110
check_offs_len(struct mtd_info * mtd,loff_t ofs,uint64_t len)111 static int check_offs_len(struct mtd_info *mtd,
112 loff_t ofs, uint64_t len)
113 {
114 struct nand_chip *chip = mtd_to_nand(mtd);
115 int ret = 0;
116
117 /* Start address must align on block boundary */
118 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
119 pr_debug("%s: unaligned address\n", __func__);
120 ret = -EINVAL;
121 }
122
123 /* Length must align on block boundary */
124 if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
125 pr_debug("%s: length not block aligned\n", __func__);
126 ret = -EINVAL;
127 }
128
129 return ret;
130 }
131
132 /**
133 * nand_release_device - [GENERIC] release chip
134 * @mtd: MTD device structure
135 *
136 * Release chip lock and wake up anyone waiting on the device.
137 */
nand_release_device(struct mtd_info * mtd)138 static void nand_release_device(struct mtd_info *mtd)
139 {
140 struct nand_chip *chip = mtd_to_nand(mtd);
141
142 /* De-select the NAND device */
143 chip->select_chip(mtd, -1);
144 }
145
146 /**
147 * nand_read_byte - [DEFAULT] read one byte from the chip
148 * @mtd: MTD device structure
149 *
150 * Default read function for 8bit buswidth
151 */
nand_read_byte(struct mtd_info * mtd)152 uint8_t nand_read_byte(struct mtd_info *mtd)
153 {
154 struct nand_chip *chip = mtd_to_nand(mtd);
155 return readb(chip->IO_ADDR_R);
156 }
157
158 /**
159 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
160 * @mtd: MTD device structure
161 *
162 * Default read function for 16bit buswidth with endianness conversion.
163 *
164 */
nand_read_byte16(struct mtd_info * mtd)165 static uint8_t nand_read_byte16(struct mtd_info *mtd)
166 {
167 struct nand_chip *chip = mtd_to_nand(mtd);
168 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
169 }
170
171 /**
172 * nand_read_word - [DEFAULT] read one word from the chip
173 * @mtd: MTD device structure
174 *
175 * Default read function for 16bit buswidth without endianness conversion.
176 */
nand_read_word(struct mtd_info * mtd)177 static u16 nand_read_word(struct mtd_info *mtd)
178 {
179 struct nand_chip *chip = mtd_to_nand(mtd);
180 return readw(chip->IO_ADDR_R);
181 }
182
183 /**
184 * nand_select_chip - [DEFAULT] control CE line
185 * @mtd: MTD device structure
186 * @chipnr: chipnumber to select, -1 for deselect
187 *
188 * Default select function for 1 chip devices.
189 */
nand_select_chip(struct mtd_info * mtd,int chipnr)190 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
191 {
192 struct nand_chip *chip = mtd_to_nand(mtd);
193
194 switch (chipnr) {
195 case -1:
196 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
197 break;
198 case 0:
199 break;
200
201 default:
202 BUG();
203 }
204 }
205
206 /**
207 * nand_write_byte - [DEFAULT] write single byte to chip
208 * @mtd: MTD device structure
209 * @byte: value to write
210 *
211 * Default function to write a byte to I/O[7:0]
212 */
nand_write_byte(struct mtd_info * mtd,uint8_t byte)213 static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
214 {
215 struct nand_chip *chip = mtd_to_nand(mtd);
216
217 chip->write_buf(mtd, &byte, 1);
218 }
219
220 /**
221 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
222 * @mtd: MTD device structure
223 * @byte: value to write
224 *
225 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
226 */
nand_write_byte16(struct mtd_info * mtd,uint8_t byte)227 static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
228 {
229 struct nand_chip *chip = mtd_to_nand(mtd);
230 uint16_t word = byte;
231
232 /*
233 * It's not entirely clear what should happen to I/O[15:8] when writing
234 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
235 *
236 * When the host supports a 16-bit bus width, only data is
237 * transferred at the 16-bit width. All address and command line
238 * transfers shall use only the lower 8-bits of the data bus. During
239 * command transfers, the host may place any value on the upper
240 * 8-bits of the data bus. During address transfers, the host shall
241 * set the upper 8-bits of the data bus to 00h.
242 *
243 * One user of the write_byte callback is nand_onfi_set_features. The
244 * four parameters are specified to be written to I/O[7:0], but this is
245 * neither an address nor a command transfer. Let's assume a 0 on the
246 * upper I/O lines is OK.
247 */
248 chip->write_buf(mtd, (uint8_t *)&word, 2);
249 }
250
iowrite8_rep(void * addr,const uint8_t * buf,int len)251 static void iowrite8_rep(void *addr, const uint8_t *buf, int len)
252 {
253 int i;
254
255 for (i = 0; i < len; i++)
256 writeb(buf[i], addr);
257 }
ioread8_rep(void * addr,uint8_t * buf,int len)258 static void ioread8_rep(void *addr, uint8_t *buf, int len)
259 {
260 int i;
261
262 for (i = 0; i < len; i++)
263 buf[i] = readb(addr);
264 }
265
ioread16_rep(void * addr,void * buf,int len)266 static void ioread16_rep(void *addr, void *buf, int len)
267 {
268 int i;
269 u16 *p = (u16 *) buf;
270
271 for (i = 0; i < len; i++)
272 p[i] = readw(addr);
273 }
274
iowrite16_rep(void * addr,void * buf,int len)275 static void iowrite16_rep(void *addr, void *buf, int len)
276 {
277 int i;
278 u16 *p = (u16 *) buf;
279
280 for (i = 0; i < len; i++)
281 writew(p[i], addr);
282 }
283
284 /**
285 * nand_write_buf - [DEFAULT] write buffer to chip
286 * @mtd: MTD device structure
287 * @buf: data buffer
288 * @len: number of bytes to write
289 *
290 * Default write function for 8bit buswidth.
291 */
nand_write_buf(struct mtd_info * mtd,const uint8_t * buf,int len)292 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
293 {
294 struct nand_chip *chip = mtd_to_nand(mtd);
295
296 iowrite8_rep(chip->IO_ADDR_W, buf, len);
297 }
298
299 /**
300 * nand_read_buf - [DEFAULT] read chip data into buffer
301 * @mtd: MTD device structure
302 * @buf: buffer to store date
303 * @len: number of bytes to read
304 *
305 * Default read function for 8bit buswidth.
306 */
nand_read_buf(struct mtd_info * mtd,uint8_t * buf,int len)307 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
308 {
309 struct nand_chip *chip = mtd_to_nand(mtd);
310
311 ioread8_rep(chip->IO_ADDR_R, buf, len);
312 }
313
314 /**
315 * nand_write_buf16 - [DEFAULT] write buffer to chip
316 * @mtd: MTD device structure
317 * @buf: data buffer
318 * @len: number of bytes to write
319 *
320 * Default write function for 16bit buswidth.
321 */
nand_write_buf16(struct mtd_info * mtd,const uint8_t * buf,int len)322 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
323 {
324 struct nand_chip *chip = mtd_to_nand(mtd);
325 u16 *p = (u16 *) buf;
326
327 iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
328 }
329
330 /**
331 * nand_read_buf16 - [DEFAULT] read chip data into buffer
332 * @mtd: MTD device structure
333 * @buf: buffer to store date
334 * @len: number of bytes to read
335 *
336 * Default read function for 16bit buswidth.
337 */
nand_read_buf16(struct mtd_info * mtd,uint8_t * buf,int len)338 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
339 {
340 struct nand_chip *chip = mtd_to_nand(mtd);
341 u16 *p = (u16 *) buf;
342
343 ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
344 }
345
346 /**
347 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
348 * @mtd: MTD device structure
349 * @ofs: offset from device start
350 *
351 * Check, if the block is bad.
352 */
nand_block_bad(struct mtd_info * mtd,loff_t ofs)353 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs)
354 {
355 int page, res = 0, i = 0;
356 struct nand_chip *chip = mtd_to_nand(mtd);
357 u16 bad;
358
359 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
360 ofs += mtd->erasesize - mtd->writesize;
361
362 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
363
364 do {
365 if (chip->options & NAND_BUSWIDTH_16) {
366 chip->cmdfunc(mtd, NAND_CMD_READOOB,
367 chip->badblockpos & 0xFE, page);
368 bad = cpu_to_le16(chip->read_word(mtd));
369 if (chip->badblockpos & 0x1)
370 bad >>= 8;
371 else
372 bad &= 0xFF;
373 } else {
374 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
375 page);
376 bad = chip->read_byte(mtd);
377 }
378
379 if (likely(chip->badblockbits == 8))
380 res = bad != 0xFF;
381 else
382 res = hweight8(bad) < chip->badblockbits;
383 ofs += mtd->writesize;
384 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
385 i++;
386 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
387
388 return res;
389 }
390
391 /**
392 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
393 * @mtd: MTD device structure
394 * @ofs: offset from device start
395 *
396 * This is the default implementation, which can be overridden by a hardware
397 * specific driver. It provides the details for writing a bad block marker to a
398 * block.
399 */
nand_default_block_markbad(struct mtd_info * mtd,loff_t ofs)400 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
401 {
402 struct nand_chip *chip = mtd_to_nand(mtd);
403 struct mtd_oob_ops ops;
404 uint8_t buf[2] = { 0, 0 };
405 int ret = 0, res, i = 0;
406
407 memset(&ops, 0, sizeof(ops));
408 ops.oobbuf = buf;
409 ops.ooboffs = chip->badblockpos;
410 if (chip->options & NAND_BUSWIDTH_16) {
411 ops.ooboffs &= ~0x01;
412 ops.len = ops.ooblen = 2;
413 } else {
414 ops.len = ops.ooblen = 1;
415 }
416 ops.mode = MTD_OPS_PLACE_OOB;
417
418 /* Write to first/last page(s) if necessary */
419 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
420 ofs += mtd->erasesize - mtd->writesize;
421 do {
422 res = nand_do_write_oob(mtd, ofs, &ops);
423 if (!ret)
424 ret = res;
425
426 i++;
427 ofs += mtd->writesize;
428 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
429
430 return ret;
431 }
432
433 /**
434 * nand_block_markbad_lowlevel - mark a block bad
435 * @mtd: MTD device structure
436 * @ofs: offset from device start
437 *
438 * This function performs the generic NAND bad block marking steps (i.e., bad
439 * block table(s) and/or marker(s)). We only allow the hardware driver to
440 * specify how to write bad block markers to OOB (chip->block_markbad).
441 *
442 * We try operations in the following order:
443 * (1) erase the affected block, to allow OOB marker to be written cleanly
444 * (2) write bad block marker to OOB area of affected block (unless flag
445 * NAND_BBT_NO_OOB_BBM is present)
446 * (3) update the BBT
447 * Note that we retain the first error encountered in (2) or (3), finish the
448 * procedures, and dump the error in the end.
449 */
nand_block_markbad_lowlevel(struct mtd_info * mtd,loff_t ofs)450 static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
451 {
452 struct nand_chip *chip = mtd_to_nand(mtd);
453 int res, ret = 0;
454
455 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
456 struct erase_info einfo;
457
458 /* Attempt erase before marking OOB */
459 memset(&einfo, 0, sizeof(einfo));
460 einfo.mtd = mtd;
461 einfo.addr = ofs;
462 einfo.len = 1ULL << chip->phys_erase_shift;
463 nand_erase_nand(mtd, &einfo, 0);
464
465 /* Write bad block marker to OOB */
466 nand_get_device(mtd, FL_WRITING);
467 ret = chip->block_markbad(mtd, ofs);
468 nand_release_device(mtd);
469 }
470
471 /* Mark block bad in BBT */
472 if (chip->bbt) {
473 res = nand_markbad_bbt(mtd, ofs);
474 if (!ret)
475 ret = res;
476 }
477
478 if (!ret)
479 mtd->ecc_stats.badblocks++;
480
481 return ret;
482 }
483
484 /**
485 * nand_check_wp - [GENERIC] check if the chip is write protected
486 * @mtd: MTD device structure
487 *
488 * Check, if the device is write protected. The function expects, that the
489 * device is already selected.
490 */
nand_check_wp(struct mtd_info * mtd)491 static int nand_check_wp(struct mtd_info *mtd)
492 {
493 struct nand_chip *chip = mtd_to_nand(mtd);
494 u8 status;
495 int ret;
496
497 /* Broken xD cards report WP despite being writable */
498 if (chip->options & NAND_BROKEN_XD)
499 return 0;
500
501 /* Check the WP bit */
502 ret = nand_status_op(chip, &status);
503 if (ret)
504 return ret;
505
506 return status & NAND_STATUS_WP ? 0 : 1;
507 }
508
509 /**
510 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
511 * @mtd: MTD device structure
512 * @ofs: offset from device start
513 *
514 * Check if the block is marked as reserved.
515 */
nand_block_isreserved(struct mtd_info * mtd,loff_t ofs)516 static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
517 {
518 struct nand_chip *chip = mtd_to_nand(mtd);
519
520 if (!chip->bbt)
521 return 0;
522 /* Return info from the table */
523 return nand_isreserved_bbt(mtd, ofs);
524 }
525
526 /**
527 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
528 * @mtd: MTD device structure
529 * @ofs: offset from device start
530 * @allowbbt: 1, if its allowed to access the bbt area
531 *
532 * Check, if the block is bad. Either by reading the bad block table or
533 * calling of the scan function.
534 */
nand_block_checkbad(struct mtd_info * mtd,loff_t ofs,int allowbbt)535 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt)
536 {
537 struct nand_chip *chip = mtd_to_nand(mtd);
538
539 if (!(chip->options & NAND_SKIP_BBTSCAN) &&
540 !(chip->options & NAND_BBT_SCANNED)) {
541 chip->options |= NAND_BBT_SCANNED;
542 chip->scan_bbt(mtd);
543 }
544
545 if (!chip->bbt)
546 return chip->block_bad(mtd, ofs);
547
548 /* Return info from the table */
549 return nand_isbad_bbt(mtd, ofs, allowbbt);
550 }
551
552 /**
553 * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
554 * @mtd: MTD device structure
555 *
556 * Wait for the ready pin after a command, and warn if a timeout occurs.
557 */
nand_wait_ready(struct mtd_info * mtd)558 void nand_wait_ready(struct mtd_info *mtd)
559 {
560 struct nand_chip *chip = mtd_to_nand(mtd);
561 u32 timeo = (CONFIG_SYS_HZ * 400) / 1000;
562 u32 time_start;
563
564 time_start = get_timer(0);
565 /* Wait until command is processed or timeout occurs */
566 while (get_timer(time_start) < timeo) {
567 if (chip->dev_ready)
568 if (chip->dev_ready(mtd))
569 break;
570 }
571
572 if (!chip->dev_ready(mtd))
573 pr_warn("timeout while waiting for chip to become ready\n");
574 }
575 EXPORT_SYMBOL_GPL(nand_wait_ready);
576
577 /**
578 * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
579 * @mtd: MTD device structure
580 * @timeo: Timeout in ms
581 *
582 * Wait for status ready (i.e. command done) or timeout.
583 */
nand_wait_status_ready(struct mtd_info * mtd,unsigned long timeo)584 static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo)
585 {
586 register struct nand_chip *chip = mtd_to_nand(mtd);
587 u32 time_start;
588 int ret;
589
590 timeo = (CONFIG_SYS_HZ * timeo) / 1000;
591 time_start = get_timer(0);
592 while (get_timer(time_start) < timeo) {
593 u8 status;
594
595 ret = nand_read_data_op(chip, &status, sizeof(status), true);
596 if (ret)
597 return;
598
599 if (status & NAND_STATUS_READY)
600 break;
601 WATCHDOG_RESET();
602 }
603 };
604
605 /**
606 * nand_command - [DEFAULT] Send command to NAND device
607 * @mtd: MTD device structure
608 * @command: the command to be sent
609 * @column: the column address for this command, -1 if none
610 * @page_addr: the page address for this command, -1 if none
611 *
612 * Send command to NAND device. This function is used for small page devices
613 * (512 Bytes per page).
614 */
nand_command(struct mtd_info * mtd,unsigned int command,int column,int page_addr)615 static void nand_command(struct mtd_info *mtd, unsigned int command,
616 int column, int page_addr)
617 {
618 register struct nand_chip *chip = mtd_to_nand(mtd);
619 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
620
621 /* Write out the command to the device */
622 if (command == NAND_CMD_SEQIN) {
623 int readcmd;
624
625 if (column >= mtd->writesize) {
626 /* OOB area */
627 column -= mtd->writesize;
628 readcmd = NAND_CMD_READOOB;
629 } else if (column < 256) {
630 /* First 256 bytes --> READ0 */
631 readcmd = NAND_CMD_READ0;
632 } else {
633 column -= 256;
634 readcmd = NAND_CMD_READ1;
635 }
636 chip->cmd_ctrl(mtd, readcmd, ctrl);
637 ctrl &= ~NAND_CTRL_CHANGE;
638 }
639 chip->cmd_ctrl(mtd, command, ctrl);
640
641 /* Address cycle, when necessary */
642 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
643 /* Serially input address */
644 if (column != -1) {
645 /* Adjust columns for 16 bit buswidth */
646 if (chip->options & NAND_BUSWIDTH_16 &&
647 !nand_opcode_8bits(command))
648 column >>= 1;
649 chip->cmd_ctrl(mtd, column, ctrl);
650 ctrl &= ~NAND_CTRL_CHANGE;
651 }
652 if (page_addr != -1) {
653 chip->cmd_ctrl(mtd, page_addr, ctrl);
654 ctrl &= ~NAND_CTRL_CHANGE;
655 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
656 if (chip->options & NAND_ROW_ADDR_3)
657 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
658 }
659 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
660
661 /*
662 * Program and erase have their own busy handlers status and sequential
663 * in needs no delay
664 */
665 switch (command) {
666
667 case NAND_CMD_PAGEPROG:
668 case NAND_CMD_ERASE1:
669 case NAND_CMD_ERASE2:
670 case NAND_CMD_SEQIN:
671 case NAND_CMD_STATUS:
672 case NAND_CMD_READID:
673 case NAND_CMD_SET_FEATURES:
674 return;
675
676 case NAND_CMD_RESET:
677 if (chip->dev_ready)
678 break;
679 udelay(chip->chip_delay);
680 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
681 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
682 chip->cmd_ctrl(mtd,
683 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
684 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
685 nand_wait_status_ready(mtd, 250);
686 return;
687
688 /* This applies to read commands */
689 default:
690 /*
691 * If we don't have access to the busy pin, we apply the given
692 * command delay
693 */
694 if (!chip->dev_ready) {
695 udelay(chip->chip_delay);
696 return;
697 }
698 }
699 /*
700 * Apply this short delay always to ensure that we do wait tWB in
701 * any case on any machine.
702 */
703 ndelay(100);
704
705 nand_wait_ready(mtd);
706 }
707
708 /**
709 * nand_command_lp - [DEFAULT] Send command to NAND large page device
710 * @mtd: MTD device structure
711 * @command: the command to be sent
712 * @column: the column address for this command, -1 if none
713 * @page_addr: the page address for this command, -1 if none
714 *
715 * Send command to NAND device. This is the version for the new large page
716 * devices. We don't have the separate regions as we have in the small page
717 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
718 */
nand_command_lp(struct mtd_info * mtd,unsigned int command,int column,int page_addr)719 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
720 int column, int page_addr)
721 {
722 register struct nand_chip *chip = mtd_to_nand(mtd);
723
724 /* Emulate NAND_CMD_READOOB */
725 if (command == NAND_CMD_READOOB) {
726 column += mtd->writesize;
727 command = NAND_CMD_READ0;
728 }
729
730 /* Command latch cycle */
731 chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
732
733 if (column != -1 || page_addr != -1) {
734 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
735
736 /* Serially input address */
737 if (column != -1) {
738 /* Adjust columns for 16 bit buswidth */
739 if (chip->options & NAND_BUSWIDTH_16 &&
740 !nand_opcode_8bits(command))
741 column >>= 1;
742 chip->cmd_ctrl(mtd, column, ctrl);
743 ctrl &= ~NAND_CTRL_CHANGE;
744 chip->cmd_ctrl(mtd, column >> 8, ctrl);
745 }
746 if (page_addr != -1) {
747 chip->cmd_ctrl(mtd, page_addr, ctrl);
748 chip->cmd_ctrl(mtd, page_addr >> 8,
749 NAND_NCE | NAND_ALE);
750 if (chip->options & NAND_ROW_ADDR_3)
751 chip->cmd_ctrl(mtd, page_addr >> 16,
752 NAND_NCE | NAND_ALE);
753 }
754 }
755 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
756
757 /*
758 * Program and erase have their own busy handlers status, sequential
759 * in and status need no delay.
760 */
761 switch (command) {
762
763 case NAND_CMD_CACHEDPROG:
764 case NAND_CMD_PAGEPROG:
765 case NAND_CMD_ERASE1:
766 case NAND_CMD_ERASE2:
767 case NAND_CMD_SEQIN:
768 case NAND_CMD_RNDIN:
769 case NAND_CMD_STATUS:
770 case NAND_CMD_READID:
771 case NAND_CMD_SET_FEATURES:
772 return;
773
774 case NAND_CMD_RESET:
775 if (chip->dev_ready)
776 break;
777 udelay(chip->chip_delay);
778 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
779 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
780 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
781 NAND_NCE | NAND_CTRL_CHANGE);
782 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
783 nand_wait_status_ready(mtd, 250);
784 return;
785
786 case NAND_CMD_RNDOUT:
787 /* No ready / busy check necessary */
788 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
789 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
790 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
791 NAND_NCE | NAND_CTRL_CHANGE);
792 return;
793
794 case NAND_CMD_READ0:
795 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
796 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
797 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
798 NAND_NCE | NAND_CTRL_CHANGE);
799
800 /* This applies to read commands */
801 default:
802 /*
803 * If we don't have access to the busy pin, we apply the given
804 * command delay.
805 */
806 if (!chip->dev_ready) {
807 udelay(chip->chip_delay);
808 return;
809 }
810 }
811
812 /*
813 * Apply this short delay always to ensure that we do wait tWB in
814 * any case on any machine.
815 */
816 ndelay(100);
817
818 nand_wait_ready(mtd);
819 }
820
821 /**
822 * panic_nand_get_device - [GENERIC] Get chip for selected access
823 * @chip: the nand chip descriptor
824 * @mtd: MTD device structure
825 * @new_state: the state which is requested
826 *
827 * Used when in panic, no locks are taken.
828 */
panic_nand_get_device(struct nand_chip * chip,struct mtd_info * mtd,int new_state)829 static void panic_nand_get_device(struct nand_chip *chip,
830 struct mtd_info *mtd, int new_state)
831 {
832 /* Hardware controller shared among independent devices */
833 chip->controller->active = chip;
834 chip->state = new_state;
835 }
836
837 /**
838 * nand_get_device - [GENERIC] Get chip for selected access
839 * @mtd: MTD device structure
840 * @new_state: the state which is requested
841 *
842 * Get the device and lock it for exclusive access
843 */
844 static int
nand_get_device(struct mtd_info * mtd,int new_state)845 nand_get_device(struct mtd_info *mtd, int new_state)
846 {
847 struct nand_chip *chip = mtd_to_nand(mtd);
848 chip->state = new_state;
849 return 0;
850 }
851
852 /**
853 * panic_nand_wait - [GENERIC] wait until the command is done
854 * @mtd: MTD device structure
855 * @chip: NAND chip structure
856 * @timeo: timeout
857 *
858 * Wait for command done. This is a helper function for nand_wait used when
859 * we are in interrupt context. May happen when in panic and trying to write
860 * an oops through mtdoops.
861 */
panic_nand_wait(struct mtd_info * mtd,struct nand_chip * chip,unsigned long timeo)862 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
863 unsigned long timeo)
864 {
865 int i;
866 for (i = 0; i < timeo; i++) {
867 if (chip->dev_ready) {
868 if (chip->dev_ready(mtd))
869 break;
870 } else {
871 int ret;
872 u8 status;
873
874 ret = nand_read_data_op(chip, &status, sizeof(status),
875 true);
876 if (ret)
877 return;
878
879 if (status & NAND_STATUS_READY)
880 break;
881 }
882 mdelay(1);
883 }
884 }
885
886 /**
887 * nand_wait - [DEFAULT] wait until the command is done
888 * @mtd: MTD device structure
889 * @chip: NAND chip structure
890 *
891 * Wait for command done. This applies to erase and program only.
892 */
nand_wait(struct mtd_info * mtd,struct nand_chip * chip)893 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
894 {
895 unsigned long timeo = 400;
896 u8 status;
897 int ret;
898
899 led_trigger_event(nand_led_trigger, LED_FULL);
900
901 /*
902 * Apply this short delay always to ensure that we do wait tWB in any
903 * case on any machine.
904 */
905 ndelay(100);
906
907 ret = nand_status_op(chip, NULL);
908 if (ret)
909 return ret;
910
911 u32 timer = (CONFIG_SYS_HZ * timeo) / 1000;
912 u32 time_start;
913
914 time_start = get_timer(0);
915 while (get_timer(time_start) < timer) {
916 if (chip->dev_ready) {
917 if (chip->dev_ready(mtd))
918 break;
919 } else {
920 ret = nand_read_data_op(chip, &status,
921 sizeof(status), true);
922 if (ret)
923 return ret;
924
925 if (status & NAND_STATUS_READY)
926 break;
927 }
928 }
929 led_trigger_event(nand_led_trigger, LED_OFF);
930
931 ret = nand_read_data_op(chip, &status, sizeof(status), true);
932 if (ret)
933 return ret;
934
935 /* This can happen if in case of timeout or buggy dev_ready */
936 WARN_ON(!(status & NAND_STATUS_READY));
937 return status;
938 }
939
940 /**
941 * nand_reset_data_interface - Reset data interface and timings
942 * @chip: The NAND chip
943 * @chipnr: Internal die id
944 *
945 * Reset the Data interface and timings to ONFI mode 0.
946 *
947 * Returns 0 for success or negative error code otherwise.
948 */
nand_reset_data_interface(struct nand_chip * chip,int chipnr)949 static int nand_reset_data_interface(struct nand_chip *chip, int chipnr)
950 {
951 struct mtd_info *mtd = nand_to_mtd(chip);
952 const struct nand_data_interface *conf;
953 int ret;
954
955 if (!chip->setup_data_interface)
956 return 0;
957
958 /*
959 * The ONFI specification says:
960 * "
961 * To transition from NV-DDR or NV-DDR2 to the SDR data
962 * interface, the host shall use the Reset (FFh) command
963 * using SDR timing mode 0. A device in any timing mode is
964 * required to recognize Reset (FFh) command issued in SDR
965 * timing mode 0.
966 * "
967 *
968 * Configure the data interface in SDR mode and set the
969 * timings to timing mode 0.
970 */
971
972 conf = nand_get_default_data_interface();
973 ret = chip->setup_data_interface(mtd, chipnr, conf);
974 if (ret)
975 pr_err("Failed to configure data interface to SDR timing mode 0\n");
976
977 return ret;
978 }
979
980 /**
981 * nand_setup_data_interface - Setup the best data interface and timings
982 * @chip: The NAND chip
983 * @chipnr: Internal die id
984 *
985 * Find and configure the best data interface and NAND timings supported by
986 * the chip and the driver.
987 * First tries to retrieve supported timing modes from ONFI information,
988 * and if the NAND chip does not support ONFI, relies on the
989 * ->onfi_timing_mode_default specified in the nand_ids table.
990 *
991 * Returns 0 for success or negative error code otherwise.
992 */
nand_setup_data_interface(struct nand_chip * chip,int chipnr)993 static int nand_setup_data_interface(struct nand_chip *chip, int chipnr)
994 {
995 struct mtd_info *mtd = nand_to_mtd(chip);
996 int ret;
997
998 if (!chip->setup_data_interface || !chip->data_interface)
999 return 0;
1000
1001 /*
1002 * Ensure the timing mode has been changed on the chip side
1003 * before changing timings on the controller side.
1004 */
1005 if (chip->onfi_version) {
1006 u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = {
1007 chip->onfi_timing_mode_default,
1008 };
1009
1010 ret = chip->onfi_set_features(mtd, chip,
1011 ONFI_FEATURE_ADDR_TIMING_MODE,
1012 tmode_param);
1013 if (ret)
1014 goto err;
1015 }
1016
1017 ret = chip->setup_data_interface(mtd, chipnr, chip->data_interface);
1018 err:
1019 return ret;
1020 }
1021
1022 /**
1023 * nand_init_data_interface - find the best data interface and timings
1024 * @chip: The NAND chip
1025 *
1026 * Find the best data interface and NAND timings supported by the chip
1027 * and the driver.
1028 * First tries to retrieve supported timing modes from ONFI information,
1029 * and if the NAND chip does not support ONFI, relies on the
1030 * ->onfi_timing_mode_default specified in the nand_ids table. After this
1031 * function nand_chip->data_interface is initialized with the best timing mode
1032 * available.
1033 *
1034 * Returns 0 for success or negative error code otherwise.
1035 */
nand_init_data_interface(struct nand_chip * chip)1036 static int nand_init_data_interface(struct nand_chip *chip)
1037 {
1038 struct mtd_info *mtd = nand_to_mtd(chip);
1039 int modes, mode, ret;
1040
1041 if (!chip->setup_data_interface)
1042 return 0;
1043
1044 /*
1045 * First try to identify the best timings from ONFI parameters and
1046 * if the NAND does not support ONFI, fallback to the default ONFI
1047 * timing mode.
1048 */
1049 modes = onfi_get_async_timing_mode(chip);
1050 if (modes == ONFI_TIMING_MODE_UNKNOWN) {
1051 if (!chip->onfi_timing_mode_default)
1052 return 0;
1053
1054 modes = GENMASK(chip->onfi_timing_mode_default, 0);
1055 }
1056
1057 chip->data_interface = kzalloc(sizeof(*chip->data_interface),
1058 GFP_KERNEL);
1059 if (!chip->data_interface)
1060 return -ENOMEM;
1061
1062 for (mode = fls(modes) - 1; mode >= 0; mode--) {
1063 ret = onfi_init_data_interface(chip, chip->data_interface,
1064 NAND_SDR_IFACE, mode);
1065 if (ret)
1066 continue;
1067
1068 /* Pass -1 to only */
1069 ret = chip->setup_data_interface(mtd,
1070 NAND_DATA_IFACE_CHECK_ONLY,
1071 chip->data_interface);
1072 if (!ret) {
1073 chip->onfi_timing_mode_default = mode;
1074 break;
1075 }
1076 }
1077
1078 return 0;
1079 }
1080
nand_release_data_interface(struct nand_chip * chip)1081 static void __maybe_unused nand_release_data_interface(struct nand_chip *chip)
1082 {
1083 kfree(chip->data_interface);
1084 }
1085
1086 /**
1087 * nand_read_page_op - Do a READ PAGE operation
1088 * @chip: The NAND chip
1089 * @page: page to read
1090 * @offset_in_page: offset within the page
1091 * @buf: buffer used to store the data
1092 * @len: length of the buffer
1093 *
1094 * This function issues a READ PAGE operation.
1095 * This function does not select/unselect the CS line.
1096 *
1097 * Returns 0 on success, a negative error code otherwise.
1098 */
nand_read_page_op(struct nand_chip * chip,unsigned int page,unsigned int offset_in_page,void * buf,unsigned int len)1099 int nand_read_page_op(struct nand_chip *chip, unsigned int page,
1100 unsigned int offset_in_page, void *buf, unsigned int len)
1101 {
1102 struct mtd_info *mtd = nand_to_mtd(chip);
1103
1104 if (len && !buf)
1105 return -EINVAL;
1106
1107 if (offset_in_page + len > mtd->writesize + mtd->oobsize)
1108 return -EINVAL;
1109
1110 chip->cmdfunc(mtd, NAND_CMD_READ0, offset_in_page, page);
1111 if (len)
1112 chip->read_buf(mtd, buf, len);
1113
1114 return 0;
1115 }
1116 EXPORT_SYMBOL_GPL(nand_read_page_op);
1117
1118 /**
1119 * nand_read_param_page_op - Do a READ PARAMETER PAGE operation
1120 * @chip: The NAND chip
1121 * @page: parameter page to read
1122 * @buf: buffer used to store the data
1123 * @len: length of the buffer
1124 *
1125 * This function issues a READ PARAMETER PAGE operation.
1126 * This function does not select/unselect the CS line.
1127 *
1128 * Returns 0 on success, a negative error code otherwise.
1129 */
nand_read_param_page_op(struct nand_chip * chip,u8 page,void * buf,unsigned int len)1130 static int nand_read_param_page_op(struct nand_chip *chip, u8 page, void *buf,
1131 unsigned int len)
1132 {
1133 struct mtd_info *mtd = nand_to_mtd(chip);
1134 unsigned int i;
1135 u8 *p = buf;
1136
1137 if (len && !buf)
1138 return -EINVAL;
1139
1140 chip->cmdfunc(mtd, NAND_CMD_PARAM, page, -1);
1141 for (i = 0; i < len; i++)
1142 p[i] = chip->read_byte(mtd);
1143
1144 return 0;
1145 }
1146
1147 /**
1148 * nand_change_read_column_op - Do a CHANGE READ COLUMN operation
1149 * @chip: The NAND chip
1150 * @offset_in_page: offset within the page
1151 * @buf: buffer used to store the data
1152 * @len: length of the buffer
1153 * @force_8bit: force 8-bit bus access
1154 *
1155 * This function issues a CHANGE READ COLUMN operation.
1156 * This function does not select/unselect the CS line.
1157 *
1158 * Returns 0 on success, a negative error code otherwise.
1159 */
nand_change_read_column_op(struct nand_chip * chip,unsigned int offset_in_page,void * buf,unsigned int len,bool force_8bit)1160 int nand_change_read_column_op(struct nand_chip *chip,
1161 unsigned int offset_in_page, void *buf,
1162 unsigned int len, bool force_8bit)
1163 {
1164 struct mtd_info *mtd = nand_to_mtd(chip);
1165
1166 if (len && !buf)
1167 return -EINVAL;
1168
1169 if (offset_in_page + len > mtd->writesize + mtd->oobsize)
1170 return -EINVAL;
1171
1172 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset_in_page, -1);
1173 if (len)
1174 chip->read_buf(mtd, buf, len);
1175
1176 return 0;
1177 }
1178 EXPORT_SYMBOL_GPL(nand_change_read_column_op);
1179
1180 /**
1181 * nand_read_oob_op - Do a READ OOB operation
1182 * @chip: The NAND chip
1183 * @page: page to read
1184 * @offset_in_oob: offset within the OOB area
1185 * @buf: buffer used to store the data
1186 * @len: length of the buffer
1187 *
1188 * This function issues a READ OOB operation.
1189 * This function does not select/unselect the CS line.
1190 *
1191 * Returns 0 on success, a negative error code otherwise.
1192 */
nand_read_oob_op(struct nand_chip * chip,unsigned int page,unsigned int offset_in_oob,void * buf,unsigned int len)1193 int nand_read_oob_op(struct nand_chip *chip, unsigned int page,
1194 unsigned int offset_in_oob, void *buf, unsigned int len)
1195 {
1196 struct mtd_info *mtd = nand_to_mtd(chip);
1197
1198 if (len && !buf)
1199 return -EINVAL;
1200
1201 if (offset_in_oob + len > mtd->oobsize)
1202 return -EINVAL;
1203
1204 chip->cmdfunc(mtd, NAND_CMD_READOOB, offset_in_oob, page);
1205 if (len)
1206 chip->read_buf(mtd, buf, len);
1207
1208 return 0;
1209 }
1210 EXPORT_SYMBOL_GPL(nand_read_oob_op);
1211
1212 /**
1213 * nand_prog_page_begin_op - starts a PROG PAGE operation
1214 * @chip: The NAND chip
1215 * @page: page to write
1216 * @offset_in_page: offset within the page
1217 * @buf: buffer containing the data to write to the page
1218 * @len: length of the buffer
1219 *
1220 * This function issues the first half of a PROG PAGE operation.
1221 * This function does not select/unselect the CS line.
1222 *
1223 * Returns 0 on success, a negative error code otherwise.
1224 */
nand_prog_page_begin_op(struct nand_chip * chip,unsigned int page,unsigned int offset_in_page,const void * buf,unsigned int len)1225 int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page,
1226 unsigned int offset_in_page, const void *buf,
1227 unsigned int len)
1228 {
1229 struct mtd_info *mtd = nand_to_mtd(chip);
1230
1231 if (len && !buf)
1232 return -EINVAL;
1233
1234 if (offset_in_page + len > mtd->writesize + mtd->oobsize)
1235 return -EINVAL;
1236
1237 chip->cmdfunc(mtd, NAND_CMD_SEQIN, offset_in_page, page);
1238
1239 if (buf)
1240 chip->write_buf(mtd, buf, len);
1241
1242 return 0;
1243 }
1244 EXPORT_SYMBOL_GPL(nand_prog_page_begin_op);
1245
1246 /**
1247 * nand_prog_page_end_op - ends a PROG PAGE operation
1248 * @chip: The NAND chip
1249 *
1250 * This function issues the second half of a PROG PAGE operation.
1251 * This function does not select/unselect the CS line.
1252 *
1253 * Returns 0 on success, a negative error code otherwise.
1254 */
nand_prog_page_end_op(struct nand_chip * chip)1255 int nand_prog_page_end_op(struct nand_chip *chip)
1256 {
1257 struct mtd_info *mtd = nand_to_mtd(chip);
1258 int status;
1259
1260 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1261
1262 status = chip->waitfunc(mtd, chip);
1263 if (status & NAND_STATUS_FAIL)
1264 return -EIO;
1265
1266 return 0;
1267 }
1268 EXPORT_SYMBOL_GPL(nand_prog_page_end_op);
1269
1270 /**
1271 * nand_prog_page_op - Do a full PROG PAGE operation
1272 * @chip: The NAND chip
1273 * @page: page to write
1274 * @offset_in_page: offset within the page
1275 * @buf: buffer containing the data to write to the page
1276 * @len: length of the buffer
1277 *
1278 * This function issues a full PROG PAGE operation.
1279 * This function does not select/unselect the CS line.
1280 *
1281 * Returns 0 on success, a negative error code otherwise.
1282 */
nand_prog_page_op(struct nand_chip * chip,unsigned int page,unsigned int offset_in_page,const void * buf,unsigned int len)1283 int nand_prog_page_op(struct nand_chip *chip, unsigned int page,
1284 unsigned int offset_in_page, const void *buf,
1285 unsigned int len)
1286 {
1287 struct mtd_info *mtd = nand_to_mtd(chip);
1288 int status;
1289
1290 if (!len || !buf)
1291 return -EINVAL;
1292
1293 if (offset_in_page + len > mtd->writesize + mtd->oobsize)
1294 return -EINVAL;
1295
1296 chip->cmdfunc(mtd, NAND_CMD_SEQIN, offset_in_page, page);
1297 chip->write_buf(mtd, buf, len);
1298 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1299
1300 status = chip->waitfunc(mtd, chip);
1301 if (status & NAND_STATUS_FAIL)
1302 return -EIO;
1303
1304 return 0;
1305 }
1306 EXPORT_SYMBOL_GPL(nand_prog_page_op);
1307
1308 /**
1309 * nand_change_write_column_op - Do a CHANGE WRITE COLUMN operation
1310 * @chip: The NAND chip
1311 * @offset_in_page: offset within the page
1312 * @buf: buffer containing the data to send to the NAND
1313 * @len: length of the buffer
1314 * @force_8bit: force 8-bit bus access
1315 *
1316 * This function issues a CHANGE WRITE COLUMN operation.
1317 * This function does not select/unselect the CS line.
1318 *
1319 * Returns 0 on success, a negative error code otherwise.
1320 */
nand_change_write_column_op(struct nand_chip * chip,unsigned int offset_in_page,const void * buf,unsigned int len,bool force_8bit)1321 int nand_change_write_column_op(struct nand_chip *chip,
1322 unsigned int offset_in_page,
1323 const void *buf, unsigned int len,
1324 bool force_8bit)
1325 {
1326 struct mtd_info *mtd = nand_to_mtd(chip);
1327
1328 if (len && !buf)
1329 return -EINVAL;
1330
1331 if (offset_in_page + len > mtd->writesize + mtd->oobsize)
1332 return -EINVAL;
1333
1334 chip->cmdfunc(mtd, NAND_CMD_RNDIN, offset_in_page, -1);
1335 if (len)
1336 chip->write_buf(mtd, buf, len);
1337
1338 return 0;
1339 }
1340 EXPORT_SYMBOL_GPL(nand_change_write_column_op);
1341
1342 /**
1343 * nand_readid_op - Do a READID operation
1344 * @chip: The NAND chip
1345 * @addr: address cycle to pass after the READID command
1346 * @buf: buffer used to store the ID
1347 * @len: length of the buffer
1348 *
1349 * This function sends a READID command and reads back the ID returned by the
1350 * NAND.
1351 * This function does not select/unselect the CS line.
1352 *
1353 * Returns 0 on success, a negative error code otherwise.
1354 */
nand_readid_op(struct nand_chip * chip,u8 addr,void * buf,unsigned int len)1355 int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf,
1356 unsigned int len)
1357 {
1358 struct mtd_info *mtd = nand_to_mtd(chip);
1359 unsigned int i;
1360 u8 *id = buf;
1361
1362 if (len && !buf)
1363 return -EINVAL;
1364
1365 chip->cmdfunc(mtd, NAND_CMD_READID, addr, -1);
1366
1367 for (i = 0; i < len; i++)
1368 id[i] = chip->read_byte(mtd);
1369
1370 return 0;
1371 }
1372 EXPORT_SYMBOL_GPL(nand_readid_op);
1373
1374 /**
1375 * nand_status_op - Do a STATUS operation
1376 * @chip: The NAND chip
1377 * @status: out variable to store the NAND status
1378 *
1379 * This function sends a STATUS command and reads back the status returned by
1380 * the NAND.
1381 * This function does not select/unselect the CS line.
1382 *
1383 * Returns 0 on success, a negative error code otherwise.
1384 */
nand_status_op(struct nand_chip * chip,u8 * status)1385 int nand_status_op(struct nand_chip *chip, u8 *status)
1386 {
1387 struct mtd_info *mtd = nand_to_mtd(chip);
1388
1389 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1390 if (status)
1391 *status = chip->read_byte(mtd);
1392
1393 return 0;
1394 }
1395 EXPORT_SYMBOL_GPL(nand_status_op);
1396
1397 /**
1398 * nand_exit_status_op - Exit a STATUS operation
1399 * @chip: The NAND chip
1400 *
1401 * This function sends a READ0 command to cancel the effect of the STATUS
1402 * command to avoid reading only the status until a new read command is sent.
1403 *
1404 * This function does not select/unselect the CS line.
1405 *
1406 * Returns 0 on success, a negative error code otherwise.
1407 */
nand_exit_status_op(struct nand_chip * chip)1408 int nand_exit_status_op(struct nand_chip *chip)
1409 {
1410 struct mtd_info *mtd = nand_to_mtd(chip);
1411
1412 chip->cmdfunc(mtd, NAND_CMD_READ0, -1, -1);
1413
1414 return 0;
1415 }
1416 EXPORT_SYMBOL_GPL(nand_exit_status_op);
1417
1418 /**
1419 * nand_erase_op - Do an erase operation
1420 * @chip: The NAND chip
1421 * @eraseblock: block to erase
1422 *
1423 * This function sends an ERASE command and waits for the NAND to be ready
1424 * before returning.
1425 * This function does not select/unselect the CS line.
1426 *
1427 * Returns 0 on success, a negative error code otherwise.
1428 */
nand_erase_op(struct nand_chip * chip,unsigned int eraseblock)1429 int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock)
1430 {
1431 struct mtd_info *mtd = nand_to_mtd(chip);
1432 unsigned int page = eraseblock <<
1433 (chip->phys_erase_shift - chip->page_shift);
1434 int status;
1435
1436 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
1437 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1438
1439 status = chip->waitfunc(mtd, chip);
1440 if (status < 0)
1441 return status;
1442
1443 if (status & NAND_STATUS_FAIL)
1444 return -EIO;
1445
1446 return 0;
1447 }
1448 EXPORT_SYMBOL_GPL(nand_erase_op);
1449
1450 /**
1451 * nand_set_features_op - Do a SET FEATURES operation
1452 * @chip: The NAND chip
1453 * @feature: feature id
1454 * @data: 4 bytes of data
1455 *
1456 * This function sends a SET FEATURES command and waits for the NAND to be
1457 * ready before returning.
1458 * This function does not select/unselect the CS line.
1459 *
1460 * Returns 0 on success, a negative error code otherwise.
1461 */
nand_set_features_op(struct nand_chip * chip,u8 feature,const void * data)1462 static int nand_set_features_op(struct nand_chip *chip, u8 feature,
1463 const void *data)
1464 {
1465 struct mtd_info *mtd = nand_to_mtd(chip);
1466 const u8 *params = data;
1467 int i, status;
1468
1469 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, feature, -1);
1470 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
1471 chip->write_byte(mtd, params[i]);
1472
1473 status = chip->waitfunc(mtd, chip);
1474 if (status & NAND_STATUS_FAIL)
1475 return -EIO;
1476
1477 return 0;
1478 }
1479
1480 /**
1481 * nand_get_features_op - Do a GET FEATURES operation
1482 * @chip: The NAND chip
1483 * @feature: feature id
1484 * @data: 4 bytes of data
1485 *
1486 * This function sends a GET FEATURES command and waits for the NAND to be
1487 * ready before returning.
1488 * This function does not select/unselect the CS line.
1489 *
1490 * Returns 0 on success, a negative error code otherwise.
1491 */
nand_get_features_op(struct nand_chip * chip,u8 feature,void * data)1492 static int nand_get_features_op(struct nand_chip *chip, u8 feature,
1493 void *data)
1494 {
1495 struct mtd_info *mtd = nand_to_mtd(chip);
1496 u8 *params = data;
1497 int i;
1498
1499 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, feature, -1);
1500 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
1501 params[i] = chip->read_byte(mtd);
1502
1503 return 0;
1504 }
1505
1506 /**
1507 * nand_reset_op - Do a reset operation
1508 * @chip: The NAND chip
1509 *
1510 * This function sends a RESET command and waits for the NAND to be ready
1511 * before returning.
1512 * This function does not select/unselect the CS line.
1513 *
1514 * Returns 0 on success, a negative error code otherwise.
1515 */
nand_reset_op(struct nand_chip * chip)1516 int nand_reset_op(struct nand_chip *chip)
1517 {
1518 struct mtd_info *mtd = nand_to_mtd(chip);
1519
1520 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1521
1522 return 0;
1523 }
1524 EXPORT_SYMBOL_GPL(nand_reset_op);
1525
1526 /**
1527 * nand_read_data_op - Read data from the NAND
1528 * @chip: The NAND chip
1529 * @buf: buffer used to store the data
1530 * @len: length of the buffer
1531 * @force_8bit: force 8-bit bus access
1532 *
1533 * This function does a raw data read on the bus. Usually used after launching
1534 * another NAND operation like nand_read_page_op().
1535 * This function does not select/unselect the CS line.
1536 *
1537 * Returns 0 on success, a negative error code otherwise.
1538 */
nand_read_data_op(struct nand_chip * chip,void * buf,unsigned int len,bool force_8bit)1539 int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len,
1540 bool force_8bit)
1541 {
1542 struct mtd_info *mtd = nand_to_mtd(chip);
1543
1544 if (!len || !buf)
1545 return -EINVAL;
1546
1547 if (force_8bit) {
1548 u8 *p = buf;
1549 unsigned int i;
1550
1551 for (i = 0; i < len; i++)
1552 p[i] = chip->read_byte(mtd);
1553 } else {
1554 chip->read_buf(mtd, buf, len);
1555 }
1556
1557 return 0;
1558 }
1559 EXPORT_SYMBOL_GPL(nand_read_data_op);
1560
1561 /**
1562 * nand_write_data_op - Write data from the NAND
1563 * @chip: The NAND chip
1564 * @buf: buffer containing the data to send on the bus
1565 * @len: length of the buffer
1566 * @force_8bit: force 8-bit bus access
1567 *
1568 * This function does a raw data write on the bus. Usually used after launching
1569 * another NAND operation like nand_write_page_begin_op().
1570 * This function does not select/unselect the CS line.
1571 *
1572 * Returns 0 on success, a negative error code otherwise.
1573 */
nand_write_data_op(struct nand_chip * chip,const void * buf,unsigned int len,bool force_8bit)1574 int nand_write_data_op(struct nand_chip *chip, const void *buf,
1575 unsigned int len, bool force_8bit)
1576 {
1577 struct mtd_info *mtd = nand_to_mtd(chip);
1578
1579 if (!len || !buf)
1580 return -EINVAL;
1581
1582 if (force_8bit) {
1583 const u8 *p = buf;
1584 unsigned int i;
1585
1586 for (i = 0; i < len; i++)
1587 chip->write_byte(mtd, p[i]);
1588 } else {
1589 chip->write_buf(mtd, buf, len);
1590 }
1591
1592 return 0;
1593 }
1594 EXPORT_SYMBOL_GPL(nand_write_data_op);
1595
1596 /**
1597 * nand_reset - Reset and initialize a NAND device
1598 * @chip: The NAND chip
1599 * @chipnr: Internal die id
1600 *
1601 * Returns 0 for success or negative error code otherwise
1602 */
nand_reset(struct nand_chip * chip,int chipnr)1603 int nand_reset(struct nand_chip *chip, int chipnr)
1604 {
1605 struct mtd_info *mtd = nand_to_mtd(chip);
1606 int ret;
1607
1608 ret = nand_reset_data_interface(chip, chipnr);
1609 if (ret)
1610 return ret;
1611
1612 /*
1613 * The CS line has to be released before we can apply the new NAND
1614 * interface settings, hence this weird ->select_chip() dance.
1615 */
1616 chip->select_chip(mtd, chipnr);
1617 ret = nand_reset_op(chip);
1618 chip->select_chip(mtd, -1);
1619 if (ret)
1620 return ret;
1621
1622 chip->select_chip(mtd, chipnr);
1623 ret = nand_setup_data_interface(chip, chipnr);
1624 chip->select_chip(mtd, -1);
1625 if (ret)
1626 return ret;
1627
1628 return 0;
1629 }
1630
1631 /**
1632 * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
1633 * @buf: buffer to test
1634 * @len: buffer length
1635 * @bitflips_threshold: maximum number of bitflips
1636 *
1637 * Check if a buffer contains only 0xff, which means the underlying region
1638 * has been erased and is ready to be programmed.
1639 * The bitflips_threshold specify the maximum number of bitflips before
1640 * considering the region is not erased.
1641 * Note: The logic of this function has been extracted from the memweight
1642 * implementation, except that nand_check_erased_buf function exit before
1643 * testing the whole buffer if the number of bitflips exceed the
1644 * bitflips_threshold value.
1645 *
1646 * Returns a positive number of bitflips less than or equal to
1647 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1648 * threshold.
1649 */
nand_check_erased_buf(void * buf,int len,int bitflips_threshold)1650 static int nand_check_erased_buf(void *buf, int len, int bitflips_threshold)
1651 {
1652 const unsigned char *bitmap = buf;
1653 int bitflips = 0;
1654 int weight;
1655
1656 for (; len && ((uintptr_t)bitmap) % sizeof(long);
1657 len--, bitmap++) {
1658 weight = hweight8(*bitmap);
1659 bitflips += BITS_PER_BYTE - weight;
1660 if (unlikely(bitflips > bitflips_threshold))
1661 return -EBADMSG;
1662 }
1663
1664 for (; len >= 4; len -= 4, bitmap += 4) {
1665 weight = hweight32(*((u32 *)bitmap));
1666 bitflips += 32 - weight;
1667 if (unlikely(bitflips > bitflips_threshold))
1668 return -EBADMSG;
1669 }
1670
1671 for (; len > 0; len--, bitmap++) {
1672 weight = hweight8(*bitmap);
1673 bitflips += BITS_PER_BYTE - weight;
1674 if (unlikely(bitflips > bitflips_threshold))
1675 return -EBADMSG;
1676 }
1677
1678 return bitflips;
1679 }
1680
1681 /**
1682 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
1683 * 0xff data
1684 * @data: data buffer to test
1685 * @datalen: data length
1686 * @ecc: ECC buffer
1687 * @ecclen: ECC length
1688 * @extraoob: extra OOB buffer
1689 * @extraooblen: extra OOB length
1690 * @bitflips_threshold: maximum number of bitflips
1691 *
1692 * Check if a data buffer and its associated ECC and OOB data contains only
1693 * 0xff pattern, which means the underlying region has been erased and is
1694 * ready to be programmed.
1695 * The bitflips_threshold specify the maximum number of bitflips before
1696 * considering the region as not erased.
1697 *
1698 * Note:
1699 * 1/ ECC algorithms are working on pre-defined block sizes which are usually
1700 * different from the NAND page size. When fixing bitflips, ECC engines will
1701 * report the number of errors per chunk, and the NAND core infrastructure
1702 * expect you to return the maximum number of bitflips for the whole page.
1703 * This is why you should always use this function on a single chunk and
1704 * not on the whole page. After checking each chunk you should update your
1705 * max_bitflips value accordingly.
1706 * 2/ When checking for bitflips in erased pages you should not only check
1707 * the payload data but also their associated ECC data, because a user might
1708 * have programmed almost all bits to 1 but a few. In this case, we
1709 * shouldn't consider the chunk as erased, and checking ECC bytes prevent
1710 * this case.
1711 * 3/ The extraoob argument is optional, and should be used if some of your OOB
1712 * data are protected by the ECC engine.
1713 * It could also be used if you support subpages and want to attach some
1714 * extra OOB data to an ECC chunk.
1715 *
1716 * Returns a positive number of bitflips less than or equal to
1717 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1718 * threshold. In case of success, the passed buffers are filled with 0xff.
1719 */
nand_check_erased_ecc_chunk(void * data,int datalen,void * ecc,int ecclen,void * extraoob,int extraooblen,int bitflips_threshold)1720 int nand_check_erased_ecc_chunk(void *data, int datalen,
1721 void *ecc, int ecclen,
1722 void *extraoob, int extraooblen,
1723 int bitflips_threshold)
1724 {
1725 int data_bitflips = 0, ecc_bitflips = 0, extraoob_bitflips = 0;
1726
1727 data_bitflips = nand_check_erased_buf(data, datalen,
1728 bitflips_threshold);
1729 if (data_bitflips < 0)
1730 return data_bitflips;
1731
1732 bitflips_threshold -= data_bitflips;
1733
1734 ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold);
1735 if (ecc_bitflips < 0)
1736 return ecc_bitflips;
1737
1738 bitflips_threshold -= ecc_bitflips;
1739
1740 extraoob_bitflips = nand_check_erased_buf(extraoob, extraooblen,
1741 bitflips_threshold);
1742 if (extraoob_bitflips < 0)
1743 return extraoob_bitflips;
1744
1745 if (data_bitflips)
1746 memset(data, 0xff, datalen);
1747
1748 if (ecc_bitflips)
1749 memset(ecc, 0xff, ecclen);
1750
1751 if (extraoob_bitflips)
1752 memset(extraoob, 0xff, extraooblen);
1753
1754 return data_bitflips + ecc_bitflips + extraoob_bitflips;
1755 }
1756 EXPORT_SYMBOL(nand_check_erased_ecc_chunk);
1757
1758 /**
1759 * nand_read_page_raw - [INTERN] read raw page data without ecc
1760 * @mtd: mtd info structure
1761 * @chip: nand chip info structure
1762 * @buf: buffer to store read data
1763 * @oob_required: caller requires OOB data read to chip->oob_poi
1764 * @page: page number to read
1765 *
1766 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1767 */
nand_read_page_raw(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)1768 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1769 uint8_t *buf, int oob_required, int page)
1770 {
1771 int ret;
1772
1773 ret = nand_read_data_op(chip, buf, mtd->writesize, false);
1774 if (ret)
1775 return ret;
1776
1777 if (oob_required) {
1778 ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize,
1779 false);
1780 if (ret)
1781 return ret;
1782 }
1783
1784 return 0;
1785 }
1786
1787 /**
1788 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1789 * @mtd: mtd info structure
1790 * @chip: nand chip info structure
1791 * @buf: buffer to store read data
1792 * @oob_required: caller requires OOB data read to chip->oob_poi
1793 * @page: page number to read
1794 *
1795 * We need a special oob layout and handling even when OOB isn't used.
1796 */
nand_read_page_raw_syndrome(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)1797 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1798 struct nand_chip *chip, uint8_t *buf,
1799 int oob_required, int page)
1800 {
1801 int eccsize = chip->ecc.size;
1802 int eccbytes = chip->ecc.bytes;
1803 uint8_t *oob = chip->oob_poi;
1804 int steps, size, ret;
1805
1806 for (steps = chip->ecc.steps; steps > 0; steps--) {
1807 ret = nand_read_data_op(chip, buf, eccsize, false);
1808 if (ret)
1809 return ret;
1810
1811 buf += eccsize;
1812
1813 if (chip->ecc.prepad) {
1814 ret = nand_read_data_op(chip, oob, chip->ecc.prepad,
1815 false);
1816 if (ret)
1817 return ret;
1818
1819 oob += chip->ecc.prepad;
1820 }
1821
1822 ret = nand_read_data_op(chip, oob, eccbytes, false);
1823 if (ret)
1824 return ret;
1825
1826 oob += eccbytes;
1827
1828 if (chip->ecc.postpad) {
1829 ret = nand_read_data_op(chip, oob, chip->ecc.postpad,
1830 false);
1831 if (ret)
1832 return ret;
1833
1834 oob += chip->ecc.postpad;
1835 }
1836 }
1837
1838 size = mtd->oobsize - (oob - chip->oob_poi);
1839 if (size) {
1840 ret = nand_read_data_op(chip, oob, size, false);
1841 if (ret)
1842 return ret;
1843 }
1844
1845 return 0;
1846 }
1847
1848 /**
1849 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1850 * @mtd: mtd info structure
1851 * @chip: nand chip info structure
1852 * @buf: buffer to store read data
1853 * @oob_required: caller requires OOB data read to chip->oob_poi
1854 * @page: page number to read
1855 */
nand_read_page_swecc(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)1856 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1857 uint8_t *buf, int oob_required, int page)
1858 {
1859 int i, eccsize = chip->ecc.size;
1860 int eccbytes = chip->ecc.bytes;
1861 int eccsteps = chip->ecc.steps;
1862 uint8_t *p = buf;
1863 uint8_t *ecc_calc = chip->buffers->ecccalc;
1864 uint8_t *ecc_code = chip->buffers->ecccode;
1865 uint32_t *eccpos = chip->ecc.layout->eccpos;
1866 unsigned int max_bitflips = 0;
1867
1868 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
1869
1870 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1871 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1872
1873 for (i = 0; i < chip->ecc.total; i++)
1874 ecc_code[i] = chip->oob_poi[eccpos[i]];
1875
1876 eccsteps = chip->ecc.steps;
1877 p = buf;
1878
1879 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1880 int stat;
1881
1882 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1883 if (stat < 0) {
1884 mtd->ecc_stats.failed++;
1885 } else {
1886 mtd->ecc_stats.corrected += stat;
1887 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1888 }
1889 }
1890 return max_bitflips;
1891 }
1892
1893 /**
1894 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1895 * @mtd: mtd info structure
1896 * @chip: nand chip info structure
1897 * @data_offs: offset of requested data within the page
1898 * @readlen: data length
1899 * @bufpoi: buffer to store read data
1900 * @page: page number to read
1901 */
nand_read_subpage(struct mtd_info * mtd,struct nand_chip * chip,uint32_t data_offs,uint32_t readlen,uint8_t * bufpoi,int page)1902 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1903 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi,
1904 int page)
1905 {
1906 int start_step, end_step, num_steps;
1907 uint32_t *eccpos = chip->ecc.layout->eccpos;
1908 uint8_t *p;
1909 int data_col_addr, i, gaps = 0;
1910 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1911 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1912 int index;
1913 unsigned int max_bitflips = 0;
1914 int ret;
1915
1916 /* Column address within the page aligned to ECC size (256bytes) */
1917 start_step = data_offs / chip->ecc.size;
1918 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1919 num_steps = end_step - start_step + 1;
1920 index = start_step * chip->ecc.bytes;
1921
1922 /* Data size aligned to ECC ecc.size */
1923 datafrag_len = num_steps * chip->ecc.size;
1924 eccfrag_len = num_steps * chip->ecc.bytes;
1925
1926 data_col_addr = start_step * chip->ecc.size;
1927 /* If we read not a page aligned data */
1928 if (data_col_addr != 0)
1929 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1930
1931 p = bufpoi + data_col_addr;
1932 ret = nand_read_data_op(chip, p, datafrag_len, false);
1933 if (ret)
1934 return ret;
1935
1936 /* Calculate ECC */
1937 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1938 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1939
1940 /*
1941 * The performance is faster if we position offsets according to
1942 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1943 */
1944 for (i = 0; i < eccfrag_len - 1; i++) {
1945 if (eccpos[i + index] + 1 != eccpos[i + index + 1]) {
1946 gaps = 1;
1947 break;
1948 }
1949 }
1950 if (gaps) {
1951 ret = nand_change_read_column_op(chip, mtd->writesize,
1952 chip->oob_poi, mtd->oobsize,
1953 false);
1954 if (ret)
1955 return ret;
1956 } else {
1957 /*
1958 * Send the command to read the particular ECC bytes take care
1959 * about buswidth alignment in read_buf.
1960 */
1961 aligned_pos = eccpos[index] & ~(busw - 1);
1962 aligned_len = eccfrag_len;
1963 if (eccpos[index] & (busw - 1))
1964 aligned_len++;
1965 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1966 aligned_len++;
1967
1968 ret = nand_change_read_column_op(chip,
1969 mtd->writesize + aligned_pos,
1970 &chip->oob_poi[aligned_pos],
1971 aligned_len, false);
1972 if (ret)
1973 return ret;
1974 }
1975
1976 for (i = 0; i < eccfrag_len; i++)
1977 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1978
1979 p = bufpoi + data_col_addr;
1980 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1981 int stat;
1982
1983 stat = chip->ecc.correct(mtd, p,
1984 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1985 if (stat == -EBADMSG &&
1986 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1987 /* check for empty pages with bitflips */
1988 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
1989 &chip->buffers->ecccode[i],
1990 chip->ecc.bytes,
1991 NULL, 0,
1992 chip->ecc.strength);
1993 }
1994
1995 if (stat < 0) {
1996 mtd->ecc_stats.failed++;
1997 } else {
1998 mtd->ecc_stats.corrected += stat;
1999 max_bitflips = max_t(unsigned int, max_bitflips, stat);
2000 }
2001 }
2002 return max_bitflips;
2003 }
2004
2005 /**
2006 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
2007 * @mtd: mtd info structure
2008 * @chip: nand chip info structure
2009 * @buf: buffer to store read data
2010 * @oob_required: caller requires OOB data read to chip->oob_poi
2011 * @page: page number to read
2012 *
2013 * Not for syndrome calculating ECC controllers which need a special oob layout.
2014 */
nand_read_page_hwecc(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)2015 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
2016 uint8_t *buf, int oob_required, int page)
2017 {
2018 int i, eccsize = chip->ecc.size;
2019 int eccbytes = chip->ecc.bytes;
2020 int eccsteps = chip->ecc.steps;
2021 uint8_t *p = buf;
2022 uint8_t *ecc_calc = chip->buffers->ecccalc;
2023 uint8_t *ecc_code = chip->buffers->ecccode;
2024 uint32_t *eccpos = chip->ecc.layout->eccpos;
2025 unsigned int max_bitflips = 0;
2026 int ret;
2027
2028 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2029 chip->ecc.hwctl(mtd, NAND_ECC_READ);
2030
2031 ret = nand_read_data_op(chip, p, eccsize, false);
2032 if (ret)
2033 return ret;
2034
2035 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2036 }
2037
2038 ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, false);
2039 if (ret)
2040 return ret;
2041
2042 for (i = 0; i < chip->ecc.total; i++)
2043 ecc_code[i] = chip->oob_poi[eccpos[i]];
2044
2045 eccsteps = chip->ecc.steps;
2046 p = buf;
2047
2048 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2049 int stat;
2050
2051 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
2052 if (stat == -EBADMSG &&
2053 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
2054 /* check for empty pages with bitflips */
2055 stat = nand_check_erased_ecc_chunk(p, eccsize,
2056 &ecc_code[i], eccbytes,
2057 NULL, 0,
2058 chip->ecc.strength);
2059 }
2060
2061 if (stat < 0) {
2062 mtd->ecc_stats.failed++;
2063 } else {
2064 mtd->ecc_stats.corrected += stat;
2065 max_bitflips = max_t(unsigned int, max_bitflips, stat);
2066 }
2067 }
2068 return max_bitflips;
2069 }
2070
2071 /**
2072 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
2073 * @mtd: mtd info structure
2074 * @chip: nand chip info structure
2075 * @buf: buffer to store read data
2076 * @oob_required: caller requires OOB data read to chip->oob_poi
2077 * @page: page number to read
2078 *
2079 * Hardware ECC for large page chips, require OOB to be read first. For this
2080 * ECC mode, the write_page method is re-used from ECC_HW. These methods
2081 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
2082 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
2083 * the data area, by overwriting the NAND manufacturer bad block markings.
2084 */
nand_read_page_hwecc_oob_first(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)2085 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
2086 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
2087 {
2088 int i, eccsize = chip->ecc.size;
2089 int eccbytes = chip->ecc.bytes;
2090 int eccsteps = chip->ecc.steps;
2091 uint8_t *p = buf;
2092 uint8_t *ecc_code = chip->buffers->ecccode;
2093 uint32_t *eccpos = chip->ecc.layout->eccpos;
2094 uint8_t *ecc_calc = chip->buffers->ecccalc;
2095 unsigned int max_bitflips = 0;
2096 int ret;
2097
2098 /* Read the OOB area first */
2099 ret = nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
2100 if (ret)
2101 return ret;
2102
2103 ret = nand_read_page_op(chip, page, 0, NULL, 0);
2104 if (ret)
2105 return ret;
2106
2107 for (i = 0; i < chip->ecc.total; i++)
2108 ecc_code[i] = chip->oob_poi[eccpos[i]];
2109
2110 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2111 int stat;
2112
2113 chip->ecc.hwctl(mtd, NAND_ECC_READ);
2114
2115 ret = nand_read_data_op(chip, p, eccsize, false);
2116 if (ret)
2117 return ret;
2118
2119 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2120
2121 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
2122 if (stat == -EBADMSG &&
2123 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
2124 /* check for empty pages with bitflips */
2125 stat = nand_check_erased_ecc_chunk(p, eccsize,
2126 &ecc_code[i], eccbytes,
2127 NULL, 0,
2128 chip->ecc.strength);
2129 }
2130
2131 if (stat < 0) {
2132 mtd->ecc_stats.failed++;
2133 } else {
2134 mtd->ecc_stats.corrected += stat;
2135 max_bitflips = max_t(unsigned int, max_bitflips, stat);
2136 }
2137 }
2138 return max_bitflips;
2139 }
2140
2141 /**
2142 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
2143 * @mtd: mtd info structure
2144 * @chip: nand chip info structure
2145 * @buf: buffer to store read data
2146 * @oob_required: caller requires OOB data read to chip->oob_poi
2147 * @page: page number to read
2148 *
2149 * The hw generator calculates the error syndrome automatically. Therefore we
2150 * need a special oob layout and handling.
2151 */
nand_read_page_syndrome(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)2152 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
2153 uint8_t *buf, int oob_required, int page)
2154 {
2155 int ret, i, eccsize = chip->ecc.size;
2156 int eccbytes = chip->ecc.bytes;
2157 int eccsteps = chip->ecc.steps;
2158 int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
2159 uint8_t *p = buf;
2160 uint8_t *oob = chip->oob_poi;
2161 unsigned int max_bitflips = 0;
2162
2163 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2164 int stat;
2165
2166 chip->ecc.hwctl(mtd, NAND_ECC_READ);
2167
2168 ret = nand_read_data_op(chip, p, eccsize, false);
2169 if (ret)
2170 return ret;
2171
2172 if (chip->ecc.prepad) {
2173 ret = nand_read_data_op(chip, oob, chip->ecc.prepad,
2174 false);
2175 if (ret)
2176 return ret;
2177
2178 oob += chip->ecc.prepad;
2179 }
2180
2181 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
2182
2183 ret = nand_read_data_op(chip, oob, eccbytes, false);
2184 if (ret)
2185 return ret;
2186
2187 stat = chip->ecc.correct(mtd, p, oob, NULL);
2188
2189 oob += eccbytes;
2190
2191 if (chip->ecc.postpad) {
2192 ret = nand_read_data_op(chip, oob, chip->ecc.postpad,
2193 false);
2194 if (ret)
2195 return ret;
2196
2197 oob += chip->ecc.postpad;
2198 }
2199
2200 if (stat == -EBADMSG &&
2201 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
2202 /* check for empty pages with bitflips */
2203 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
2204 oob - eccpadbytes,
2205 eccpadbytes,
2206 NULL, 0,
2207 chip->ecc.strength);
2208 }
2209
2210 if (stat < 0) {
2211 mtd->ecc_stats.failed++;
2212 } else {
2213 mtd->ecc_stats.corrected += stat;
2214 max_bitflips = max_t(unsigned int, max_bitflips, stat);
2215 }
2216 }
2217
2218 /* Calculate remaining oob bytes */
2219 i = mtd->oobsize - (oob - chip->oob_poi);
2220 if (i) {
2221 ret = nand_read_data_op(chip, oob, i, false);
2222 if (ret)
2223 return ret;
2224 }
2225
2226 return max_bitflips;
2227 }
2228
2229 /**
2230 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
2231 * @chip: nand chip structure
2232 * @oob: oob destination address
2233 * @ops: oob ops structure
2234 * @len: size of oob to transfer
2235 */
nand_transfer_oob(struct nand_chip * chip,uint8_t * oob,struct mtd_oob_ops * ops,size_t len)2236 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
2237 struct mtd_oob_ops *ops, size_t len)
2238 {
2239 switch (ops->mode) {
2240
2241 case MTD_OPS_PLACE_OOB:
2242 case MTD_OPS_RAW:
2243 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
2244 return oob + len;
2245
2246 case MTD_OPS_AUTO_OOB: {
2247 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2248 uint32_t boffs = 0, roffs = ops->ooboffs;
2249 size_t bytes = 0;
2250
2251 for (; free->length && len; free++, len -= bytes) {
2252 /* Read request not from offset 0? */
2253 if (unlikely(roffs)) {
2254 if (roffs >= free->length) {
2255 roffs -= free->length;
2256 continue;
2257 }
2258 boffs = free->offset + roffs;
2259 bytes = min_t(size_t, len,
2260 (free->length - roffs));
2261 roffs = 0;
2262 } else {
2263 bytes = min_t(size_t, len, free->length);
2264 boffs = free->offset;
2265 }
2266 memcpy(oob, chip->oob_poi + boffs, bytes);
2267 oob += bytes;
2268 }
2269 return oob;
2270 }
2271 default:
2272 BUG();
2273 }
2274 return NULL;
2275 }
2276
2277 /**
2278 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
2279 * @mtd: MTD device structure
2280 * @retry_mode: the retry mode to use
2281 *
2282 * Some vendors supply a special command to shift the Vt threshold, to be used
2283 * when there are too many bitflips in a page (i.e., ECC error). After setting
2284 * a new threshold, the host should retry reading the page.
2285 */
nand_setup_read_retry(struct mtd_info * mtd,int retry_mode)2286 static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
2287 {
2288 struct nand_chip *chip = mtd_to_nand(mtd);
2289
2290 pr_debug("setting READ RETRY mode %d\n", retry_mode);
2291
2292 if (retry_mode >= chip->read_retries)
2293 return -EINVAL;
2294
2295 if (!chip->setup_read_retry)
2296 return -EOPNOTSUPP;
2297
2298 return chip->setup_read_retry(mtd, retry_mode);
2299 }
2300
2301 /**
2302 * nand_do_read_ops - [INTERN] Read data with ECC
2303 * @mtd: MTD device structure
2304 * @from: offset to read from
2305 * @ops: oob ops structure
2306 *
2307 * Internal function. Called with chip held.
2308 */
nand_do_read_ops(struct mtd_info * mtd,loff_t from,struct mtd_oob_ops * ops)2309 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
2310 struct mtd_oob_ops *ops)
2311 {
2312 int chipnr, page, realpage, col, bytes, aligned, oob_required;
2313 struct nand_chip *chip = mtd_to_nand(mtd);
2314 int ret = 0;
2315 uint32_t readlen = ops->len;
2316 uint32_t oobreadlen = ops->ooblen;
2317 uint32_t max_oobsize = mtd_oobavail(mtd, ops);
2318
2319 uint8_t *bufpoi, *oob, *buf;
2320 int use_bufpoi;
2321 unsigned int max_bitflips = 0;
2322 int retry_mode = 0;
2323 bool ecc_fail = false;
2324
2325 chipnr = (int)(from >> chip->chip_shift);
2326 chip->select_chip(mtd, chipnr);
2327
2328 realpage = (int)(from >> chip->page_shift);
2329 page = realpage & chip->pagemask;
2330
2331 col = (int)(from & (mtd->writesize - 1));
2332
2333 buf = ops->datbuf;
2334 oob = ops->oobbuf;
2335 oob_required = oob ? 1 : 0;
2336
2337 while (1) {
2338 unsigned int ecc_failures = mtd->ecc_stats.failed;
2339
2340 WATCHDOG_RESET();
2341 bytes = min(mtd->writesize - col, readlen);
2342 aligned = (bytes == mtd->writesize);
2343
2344 if (!aligned)
2345 use_bufpoi = 1;
2346 else if (chip->options & NAND_USE_BOUNCE_BUFFER)
2347 use_bufpoi = !IS_ALIGNED((unsigned long)buf,
2348 chip->buf_align);
2349 else
2350 use_bufpoi = 0;
2351
2352 /* Is the current page in the buffer? */
2353 if (realpage != chip->pagebuf || oob) {
2354 bufpoi = use_bufpoi ? chip->buffers->databuf : buf;
2355
2356 if (use_bufpoi && aligned)
2357 pr_debug("%s: using read bounce buffer for buf@%p\n",
2358 __func__, buf);
2359
2360 read_retry:
2361 if (nand_standard_page_accessors(&chip->ecc)) {
2362 ret = nand_read_page_op(chip, page, 0, NULL, 0);
2363 if (ret)
2364 break;
2365 }
2366
2367 /*
2368 * Now read the page into the buffer. Absent an error,
2369 * the read methods return max bitflips per ecc step.
2370 */
2371 if (unlikely(ops->mode == MTD_OPS_RAW))
2372 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
2373 oob_required,
2374 page);
2375 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
2376 !oob)
2377 ret = chip->ecc.read_subpage(mtd, chip,
2378 col, bytes, bufpoi,
2379 page);
2380 else
2381 ret = chip->ecc.read_page(mtd, chip, bufpoi,
2382 oob_required, page);
2383 if (ret < 0) {
2384 if (use_bufpoi)
2385 /* Invalidate page cache */
2386 chip->pagebuf = -1;
2387 break;
2388 }
2389
2390 max_bitflips = max_t(unsigned int, max_bitflips, ret);
2391
2392 /* Transfer not aligned data */
2393 if (use_bufpoi) {
2394 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
2395 !(mtd->ecc_stats.failed - ecc_failures) &&
2396 (ops->mode != MTD_OPS_RAW)) {
2397 chip->pagebuf = realpage;
2398 chip->pagebuf_bitflips = ret;
2399 } else {
2400 /* Invalidate page cache */
2401 chip->pagebuf = -1;
2402 }
2403 memcpy(buf, chip->buffers->databuf + col, bytes);
2404 }
2405
2406 if (unlikely(oob)) {
2407 int toread = min(oobreadlen, max_oobsize);
2408
2409 if (toread) {
2410 oob = nand_transfer_oob(chip,
2411 oob, ops, toread);
2412 oobreadlen -= toread;
2413 }
2414 }
2415
2416 if (chip->options & NAND_NEED_READRDY) {
2417 /* Apply delay or wait for ready/busy pin */
2418 if (!chip->dev_ready)
2419 udelay(chip->chip_delay);
2420 else
2421 nand_wait_ready(mtd);
2422 }
2423
2424 if (mtd->ecc_stats.failed - ecc_failures) {
2425 if (retry_mode + 1 < chip->read_retries) {
2426 retry_mode++;
2427 ret = nand_setup_read_retry(mtd,
2428 retry_mode);
2429 if (ret < 0)
2430 break;
2431
2432 /* Reset failures; retry */
2433 mtd->ecc_stats.failed = ecc_failures;
2434 goto read_retry;
2435 } else {
2436 /* No more retry modes; real failure */
2437 ecc_fail = true;
2438 }
2439 }
2440
2441 buf += bytes;
2442 } else {
2443 memcpy(buf, chip->buffers->databuf + col, bytes);
2444 buf += bytes;
2445 max_bitflips = max_t(unsigned int, max_bitflips,
2446 chip->pagebuf_bitflips);
2447 }
2448
2449 readlen -= bytes;
2450
2451 /* Reset to retry mode 0 */
2452 if (retry_mode) {
2453 ret = nand_setup_read_retry(mtd, 0);
2454 if (ret < 0)
2455 break;
2456 retry_mode = 0;
2457 }
2458
2459 if (!readlen)
2460 break;
2461
2462 /* For subsequent reads align to page boundary */
2463 col = 0;
2464 /* Increment page address */
2465 realpage++;
2466
2467 page = realpage & chip->pagemask;
2468 /* Check, if we cross a chip boundary */
2469 if (!page) {
2470 chipnr++;
2471 chip->select_chip(mtd, -1);
2472 chip->select_chip(mtd, chipnr);
2473 }
2474 }
2475 chip->select_chip(mtd, -1);
2476
2477 ops->retlen = ops->len - (size_t) readlen;
2478 if (oob)
2479 ops->oobretlen = ops->ooblen - oobreadlen;
2480
2481 if (ret < 0)
2482 return ret;
2483
2484 if (ecc_fail)
2485 return -EBADMSG;
2486
2487 return max_bitflips;
2488 }
2489
2490 /**
2491 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
2492 * @mtd: mtd info structure
2493 * @chip: nand chip info structure
2494 * @page: page number to read
2495 */
nand_read_oob_std(struct mtd_info * mtd,struct nand_chip * chip,int page)2496 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
2497 int page)
2498 {
2499 return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
2500 }
2501
2502 /**
2503 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
2504 * with syndromes
2505 * @mtd: mtd info structure
2506 * @chip: nand chip info structure
2507 * @page: page number to read
2508 */
nand_read_oob_syndrome(struct mtd_info * mtd,struct nand_chip * chip,int page)2509 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
2510 int page)
2511 {
2512 int length = mtd->oobsize;
2513 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
2514 int eccsize = chip->ecc.size;
2515 uint8_t *bufpoi = chip->oob_poi;
2516 int i, toread, sndrnd = 0, pos, ret;
2517
2518 ret = nand_read_page_op(chip, page, chip->ecc.size, NULL, 0);
2519 if (ret)
2520 return ret;
2521
2522 for (i = 0; i < chip->ecc.steps; i++) {
2523 if (sndrnd) {
2524 int ret;
2525
2526 pos = eccsize + i * (eccsize + chunk);
2527 if (mtd->writesize > 512)
2528 ret = nand_change_read_column_op(chip, pos,
2529 NULL, 0,
2530 false);
2531 else
2532 ret = nand_read_page_op(chip, page, pos, NULL,
2533 0);
2534
2535 if (ret)
2536 return ret;
2537 } else
2538 sndrnd = 1;
2539 toread = min_t(int, length, chunk);
2540
2541 ret = nand_read_data_op(chip, bufpoi, toread, false);
2542 if (ret)
2543 return ret;
2544
2545 bufpoi += toread;
2546 length -= toread;
2547 }
2548 if (length > 0) {
2549 ret = nand_read_data_op(chip, bufpoi, length, false);
2550 if (ret)
2551 return ret;
2552 }
2553
2554 return 0;
2555 }
2556
2557 /**
2558 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
2559 * @mtd: mtd info structure
2560 * @chip: nand chip info structure
2561 * @page: page number to write
2562 */
nand_write_oob_std(struct mtd_info * mtd,struct nand_chip * chip,int page)2563 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
2564 int page)
2565 {
2566 return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi,
2567 mtd->oobsize);
2568 }
2569
2570 /**
2571 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
2572 * with syndrome - only for large page flash
2573 * @mtd: mtd info structure
2574 * @chip: nand chip info structure
2575 * @page: page number to write
2576 */
nand_write_oob_syndrome(struct mtd_info * mtd,struct nand_chip * chip,int page)2577 static int nand_write_oob_syndrome(struct mtd_info *mtd,
2578 struct nand_chip *chip, int page)
2579 {
2580 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
2581 int eccsize = chip->ecc.size, length = mtd->oobsize;
2582 int ret, i, len, pos, sndcmd = 0, steps = chip->ecc.steps;
2583 const uint8_t *bufpoi = chip->oob_poi;
2584
2585 /*
2586 * data-ecc-data-ecc ... ecc-oob
2587 * or
2588 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
2589 */
2590 if (!chip->ecc.prepad && !chip->ecc.postpad) {
2591 pos = steps * (eccsize + chunk);
2592 steps = 0;
2593 } else
2594 pos = eccsize;
2595
2596 ret = nand_prog_page_begin_op(chip, page, pos, NULL, 0);
2597 if (ret)
2598 return ret;
2599
2600 for (i = 0; i < steps; i++) {
2601 if (sndcmd) {
2602 if (mtd->writesize <= 512) {
2603 uint32_t fill = 0xFFFFFFFF;
2604
2605 len = eccsize;
2606 while (len > 0) {
2607 int num = min_t(int, len, 4);
2608
2609 ret = nand_write_data_op(chip, &fill,
2610 num, false);
2611 if (ret)
2612 return ret;
2613
2614 len -= num;
2615 }
2616 } else {
2617 pos = eccsize + i * (eccsize + chunk);
2618 ret = nand_change_write_column_op(chip, pos,
2619 NULL, 0,
2620 false);
2621 if (ret)
2622 return ret;
2623 }
2624 } else
2625 sndcmd = 1;
2626 len = min_t(int, length, chunk);
2627
2628 ret = nand_write_data_op(chip, bufpoi, len, false);
2629 if (ret)
2630 return ret;
2631
2632 bufpoi += len;
2633 length -= len;
2634 }
2635 if (length > 0) {
2636 ret = nand_write_data_op(chip, bufpoi, length, false);
2637 if (ret)
2638 return ret;
2639 }
2640
2641 return nand_prog_page_end_op(chip);
2642 }
2643
2644 /**
2645 * nand_do_read_oob - [INTERN] NAND read out-of-band
2646 * @mtd: MTD device structure
2647 * @from: offset to read from
2648 * @ops: oob operations description structure
2649 *
2650 * NAND read out-of-band data from the spare area.
2651 */
nand_do_read_oob(struct mtd_info * mtd,loff_t from,struct mtd_oob_ops * ops)2652 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
2653 struct mtd_oob_ops *ops)
2654 {
2655 int page, realpage, chipnr;
2656 struct nand_chip *chip = mtd_to_nand(mtd);
2657 struct mtd_ecc_stats stats;
2658 int readlen = ops->ooblen;
2659 int len;
2660 uint8_t *buf = ops->oobbuf;
2661 int ret = 0;
2662
2663 pr_debug("%s: from = 0x%08Lx, len = %i\n",
2664 __func__, (unsigned long long)from, readlen);
2665
2666 stats = mtd->ecc_stats;
2667
2668 len = mtd_oobavail(mtd, ops);
2669
2670 if (unlikely(ops->ooboffs >= len)) {
2671 pr_debug("%s: attempt to start read outside oob\n",
2672 __func__);
2673 return -EINVAL;
2674 }
2675
2676 /* Do not allow reads past end of device */
2677 if (unlikely(from >= mtd->size ||
2678 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
2679 (from >> chip->page_shift)) * len)) {
2680 pr_debug("%s: attempt to read beyond end of device\n",
2681 __func__);
2682 return -EINVAL;
2683 }
2684
2685 chipnr = (int)(from >> chip->chip_shift);
2686 chip->select_chip(mtd, chipnr);
2687
2688 /* Shift to get page */
2689 realpage = (int)(from >> chip->page_shift);
2690 page = realpage & chip->pagemask;
2691
2692 while (1) {
2693 WATCHDOG_RESET();
2694
2695 if (ops->mode == MTD_OPS_RAW)
2696 ret = chip->ecc.read_oob_raw(mtd, chip, page);
2697 else
2698 ret = chip->ecc.read_oob(mtd, chip, page);
2699
2700 if (ret < 0)
2701 break;
2702
2703 len = min(len, readlen);
2704 buf = nand_transfer_oob(chip, buf, ops, len);
2705
2706 if (chip->options & NAND_NEED_READRDY) {
2707 /* Apply delay or wait for ready/busy pin */
2708 if (!chip->dev_ready)
2709 udelay(chip->chip_delay);
2710 else
2711 nand_wait_ready(mtd);
2712 }
2713
2714 readlen -= len;
2715 if (!readlen)
2716 break;
2717
2718 /* Increment page address */
2719 realpage++;
2720
2721 page = realpage & chip->pagemask;
2722 /* Check, if we cross a chip boundary */
2723 if (!page) {
2724 chipnr++;
2725 chip->select_chip(mtd, -1);
2726 chip->select_chip(mtd, chipnr);
2727 }
2728 }
2729 chip->select_chip(mtd, -1);
2730
2731 ops->oobretlen = ops->ooblen - readlen;
2732
2733 if (ret < 0)
2734 return ret;
2735
2736 if (mtd->ecc_stats.failed - stats.failed)
2737 return -EBADMSG;
2738
2739 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
2740 }
2741
2742 /**
2743 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
2744 * @mtd: MTD device structure
2745 * @from: offset to read from
2746 * @ops: oob operation description structure
2747 *
2748 * NAND read data and/or out-of-band data.
2749 */
nand_read_oob(struct mtd_info * mtd,loff_t from,struct mtd_oob_ops * ops)2750 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
2751 struct mtd_oob_ops *ops)
2752 {
2753 int ret = -ENOTSUPP;
2754
2755 ops->retlen = 0;
2756
2757 /* Do not allow reads past end of device */
2758 if (ops->datbuf && (from + ops->len) > mtd->size) {
2759 pr_debug("%s: attempt to read beyond end of device\n",
2760 __func__);
2761 return -EINVAL;
2762 }
2763
2764 nand_get_device(mtd, FL_READING);
2765
2766 switch (ops->mode) {
2767 case MTD_OPS_PLACE_OOB:
2768 case MTD_OPS_AUTO_OOB:
2769 case MTD_OPS_RAW:
2770 break;
2771
2772 default:
2773 goto out;
2774 }
2775
2776 if (!ops->datbuf)
2777 ret = nand_do_read_oob(mtd, from, ops);
2778 else
2779 ret = nand_do_read_ops(mtd, from, ops);
2780
2781 out:
2782 nand_release_device(mtd);
2783 return ret;
2784 }
2785
2786
2787 /**
2788 * nand_write_page_raw - [INTERN] raw page write function
2789 * @mtd: mtd info structure
2790 * @chip: nand chip info structure
2791 * @buf: data buffer
2792 * @oob_required: must write chip->oob_poi to OOB
2793 * @page: page number to write
2794 *
2795 * Not for syndrome calculating ECC controllers, which use a special oob layout.
2796 */
nand_write_page_raw(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)2797 static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
2798 const uint8_t *buf, int oob_required, int page)
2799 {
2800 int ret;
2801
2802 ret = nand_write_data_op(chip, buf, mtd->writesize, false);
2803 if (ret)
2804 return ret;
2805
2806 if (oob_required) {
2807 ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize,
2808 false);
2809 if (ret)
2810 return ret;
2811 }
2812
2813 return 0;
2814 }
2815
2816 /**
2817 * nand_write_page_raw_syndrome - [INTERN] raw page write function
2818 * @mtd: mtd info structure
2819 * @chip: nand chip info structure
2820 * @buf: data buffer
2821 * @oob_required: must write chip->oob_poi to OOB
2822 * @page: page number to write
2823 *
2824 * We need a special oob layout and handling even when ECC isn't checked.
2825 */
nand_write_page_raw_syndrome(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)2826 static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
2827 struct nand_chip *chip,
2828 const uint8_t *buf, int oob_required,
2829 int page)
2830 {
2831 int eccsize = chip->ecc.size;
2832 int eccbytes = chip->ecc.bytes;
2833 uint8_t *oob = chip->oob_poi;
2834 int steps, size, ret;
2835
2836 for (steps = chip->ecc.steps; steps > 0; steps--) {
2837 ret = nand_write_data_op(chip, buf, eccsize, false);
2838 if (ret)
2839 return ret;
2840
2841 buf += eccsize;
2842
2843 if (chip->ecc.prepad) {
2844 ret = nand_write_data_op(chip, oob, chip->ecc.prepad,
2845 false);
2846 if (ret)
2847 return ret;
2848
2849 oob += chip->ecc.prepad;
2850 }
2851
2852 ret = nand_write_data_op(chip, oob, eccbytes, false);
2853 if (ret)
2854 return ret;
2855
2856 oob += eccbytes;
2857
2858 if (chip->ecc.postpad) {
2859 ret = nand_write_data_op(chip, oob, chip->ecc.postpad,
2860 false);
2861 if (ret)
2862 return ret;
2863
2864 oob += chip->ecc.postpad;
2865 }
2866 }
2867
2868 size = mtd->oobsize - (oob - chip->oob_poi);
2869 if (size) {
2870 ret = nand_write_data_op(chip, oob, size, false);
2871 if (ret)
2872 return ret;
2873 }
2874
2875 return 0;
2876 }
2877 /**
2878 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
2879 * @mtd: mtd info structure
2880 * @chip: nand chip info structure
2881 * @buf: data buffer
2882 * @oob_required: must write chip->oob_poi to OOB
2883 * @page: page number to write
2884 */
nand_write_page_swecc(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)2885 static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
2886 const uint8_t *buf, int oob_required,
2887 int page)
2888 {
2889 int i, eccsize = chip->ecc.size;
2890 int eccbytes = chip->ecc.bytes;
2891 int eccsteps = chip->ecc.steps;
2892 uint8_t *ecc_calc = chip->buffers->ecccalc;
2893 const uint8_t *p = buf;
2894 uint32_t *eccpos = chip->ecc.layout->eccpos;
2895
2896 /* Software ECC calculation */
2897 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
2898 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2899
2900 for (i = 0; i < chip->ecc.total; i++)
2901 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2902
2903 return chip->ecc.write_page_raw(mtd, chip, buf, 1, page);
2904 }
2905
2906 /**
2907 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
2908 * @mtd: mtd info structure
2909 * @chip: nand chip info structure
2910 * @buf: data buffer
2911 * @oob_required: must write chip->oob_poi to OOB
2912 * @page: page number to write
2913 */
nand_write_page_hwecc(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)2914 static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
2915 const uint8_t *buf, int oob_required,
2916 int page)
2917 {
2918 int i, eccsize = chip->ecc.size;
2919 int eccbytes = chip->ecc.bytes;
2920 int eccsteps = chip->ecc.steps;
2921 uint8_t *ecc_calc = chip->buffers->ecccalc;
2922 const uint8_t *p = buf;
2923 uint32_t *eccpos = chip->ecc.layout->eccpos;
2924 int ret;
2925
2926 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2927 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2928
2929 ret = nand_write_data_op(chip, p, eccsize, false);
2930 if (ret)
2931 return ret;
2932
2933 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2934 }
2935
2936 for (i = 0; i < chip->ecc.total; i++)
2937 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2938
2939 ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);
2940 if (ret)
2941 return ret;
2942
2943 return 0;
2944 }
2945
2946
2947 /**
2948 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
2949 * @mtd: mtd info structure
2950 * @chip: nand chip info structure
2951 * @offset: column address of subpage within the page
2952 * @data_len: data length
2953 * @buf: data buffer
2954 * @oob_required: must write chip->oob_poi to OOB
2955 * @page: page number to write
2956 */
nand_write_subpage_hwecc(struct mtd_info * mtd,struct nand_chip * chip,uint32_t offset,uint32_t data_len,const uint8_t * buf,int oob_required,int page)2957 static int nand_write_subpage_hwecc(struct mtd_info *mtd,
2958 struct nand_chip *chip, uint32_t offset,
2959 uint32_t data_len, const uint8_t *buf,
2960 int oob_required, int page)
2961 {
2962 uint8_t *oob_buf = chip->oob_poi;
2963 uint8_t *ecc_calc = chip->buffers->ecccalc;
2964 int ecc_size = chip->ecc.size;
2965 int ecc_bytes = chip->ecc.bytes;
2966 int ecc_steps = chip->ecc.steps;
2967 uint32_t *eccpos = chip->ecc.layout->eccpos;
2968 uint32_t start_step = offset / ecc_size;
2969 uint32_t end_step = (offset + data_len - 1) / ecc_size;
2970 int oob_bytes = mtd->oobsize / ecc_steps;
2971 int step, i;
2972 int ret;
2973
2974 for (step = 0; step < ecc_steps; step++) {
2975 /* configure controller for WRITE access */
2976 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2977
2978 /* write data (untouched subpages already masked by 0xFF) */
2979 ret = nand_write_data_op(chip, buf, ecc_size, false);
2980 if (ret)
2981 return ret;
2982
2983 /* mask ECC of un-touched subpages by padding 0xFF */
2984 if ((step < start_step) || (step > end_step))
2985 memset(ecc_calc, 0xff, ecc_bytes);
2986 else
2987 chip->ecc.calculate(mtd, buf, ecc_calc);
2988
2989 /* mask OOB of un-touched subpages by padding 0xFF */
2990 /* if oob_required, preserve OOB metadata of written subpage */
2991 if (!oob_required || (step < start_step) || (step > end_step))
2992 memset(oob_buf, 0xff, oob_bytes);
2993
2994 buf += ecc_size;
2995 ecc_calc += ecc_bytes;
2996 oob_buf += oob_bytes;
2997 }
2998
2999 /* copy calculated ECC for whole page to chip->buffer->oob */
3000 /* this include masked-value(0xFF) for unwritten subpages */
3001 ecc_calc = chip->buffers->ecccalc;
3002 for (i = 0; i < chip->ecc.total; i++)
3003 chip->oob_poi[eccpos[i]] = ecc_calc[i];
3004
3005 /* write OOB buffer to NAND device */
3006 ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);
3007 if (ret)
3008 return ret;
3009
3010 return 0;
3011 }
3012
3013
3014 /**
3015 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
3016 * @mtd: mtd info structure
3017 * @chip: nand chip info structure
3018 * @buf: data buffer
3019 * @oob_required: must write chip->oob_poi to OOB
3020 * @page: page number to write
3021 *
3022 * The hw generator calculates the error syndrome automatically. Therefore we
3023 * need a special oob layout and handling.
3024 */
nand_write_page_syndrome(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)3025 static int nand_write_page_syndrome(struct mtd_info *mtd,
3026 struct nand_chip *chip,
3027 const uint8_t *buf, int oob_required,
3028 int page)
3029 {
3030 int i, eccsize = chip->ecc.size;
3031 int eccbytes = chip->ecc.bytes;
3032 int eccsteps = chip->ecc.steps;
3033 const uint8_t *p = buf;
3034 uint8_t *oob = chip->oob_poi;
3035 int ret;
3036
3037 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
3038 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
3039
3040 ret = nand_write_data_op(chip, p, eccsize, false);
3041 if (ret)
3042 return ret;
3043
3044 if (chip->ecc.prepad) {
3045 ret = nand_write_data_op(chip, oob, chip->ecc.prepad,
3046 false);
3047 if (ret)
3048 return ret;
3049
3050 oob += chip->ecc.prepad;
3051 }
3052
3053 chip->ecc.calculate(mtd, p, oob);
3054
3055 ret = nand_write_data_op(chip, oob, eccbytes, false);
3056 if (ret)
3057 return ret;
3058
3059 oob += eccbytes;
3060
3061 if (chip->ecc.postpad) {
3062 ret = nand_write_data_op(chip, oob, chip->ecc.postpad,
3063 false);
3064 if (ret)
3065 return ret;
3066
3067 oob += chip->ecc.postpad;
3068 }
3069 }
3070
3071 /* Calculate remaining oob bytes */
3072 i = mtd->oobsize - (oob - chip->oob_poi);
3073 if (i) {
3074 ret = nand_write_data_op(chip, oob, i, false);
3075 if (ret)
3076 return ret;
3077 }
3078
3079 return 0;
3080 }
3081
3082 /**
3083 * nand_write_page - [REPLACEABLE] write one page
3084 * @mtd: MTD device structure
3085 * @chip: NAND chip descriptor
3086 * @offset: address offset within the page
3087 * @data_len: length of actual data to be written
3088 * @buf: the data to write
3089 * @oob_required: must write chip->oob_poi to OOB
3090 * @page: page number to write
3091 * @raw: use _raw version of write_page
3092 */
nand_write_page(struct mtd_info * mtd,struct nand_chip * chip,uint32_t offset,int data_len,const uint8_t * buf,int oob_required,int page,int raw)3093 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
3094 uint32_t offset, int data_len, const uint8_t *buf,
3095 int oob_required, int page, int raw)
3096 {
3097 int status, subpage;
3098
3099 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3100 chip->ecc.write_subpage)
3101 subpage = offset || (data_len < mtd->writesize);
3102 else
3103 subpage = 0;
3104
3105 if (nand_standard_page_accessors(&chip->ecc)) {
3106 status = nand_prog_page_begin_op(chip, page, 0, NULL, 0);
3107 if (status)
3108 return status;
3109 }
3110
3111 if (unlikely(raw))
3112 status = chip->ecc.write_page_raw(mtd, chip, buf,
3113 oob_required, page);
3114 else if (subpage)
3115 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
3116 buf, oob_required, page);
3117 else
3118 status = chip->ecc.write_page(mtd, chip, buf, oob_required,
3119 page);
3120
3121 if (status < 0)
3122 return status;
3123
3124 if (nand_standard_page_accessors(&chip->ecc))
3125 return nand_prog_page_end_op(chip);
3126
3127 return 0;
3128 }
3129
3130 /**
3131 * nand_fill_oob - [INTERN] Transfer client buffer to oob
3132 * @mtd: MTD device structure
3133 * @oob: oob data buffer
3134 * @len: oob data write length
3135 * @ops: oob ops structure
3136 */
nand_fill_oob(struct mtd_info * mtd,uint8_t * oob,size_t len,struct mtd_oob_ops * ops)3137 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
3138 struct mtd_oob_ops *ops)
3139 {
3140 struct nand_chip *chip = mtd_to_nand(mtd);
3141
3142 /*
3143 * Initialise to all 0xFF, to avoid the possibility of left over OOB
3144 * data from a previous OOB read.
3145 */
3146 memset(chip->oob_poi, 0xff, mtd->oobsize);
3147
3148 switch (ops->mode) {
3149
3150 case MTD_OPS_PLACE_OOB:
3151 case MTD_OPS_RAW:
3152 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
3153 return oob + len;
3154
3155 case MTD_OPS_AUTO_OOB: {
3156 struct nand_oobfree *free = chip->ecc.layout->oobfree;
3157 uint32_t boffs = 0, woffs = ops->ooboffs;
3158 size_t bytes = 0;
3159
3160 for (; free->length && len; free++, len -= bytes) {
3161 /* Write request not from offset 0? */
3162 if (unlikely(woffs)) {
3163 if (woffs >= free->length) {
3164 woffs -= free->length;
3165 continue;
3166 }
3167 boffs = free->offset + woffs;
3168 bytes = min_t(size_t, len,
3169 (free->length - woffs));
3170 woffs = 0;
3171 } else {
3172 bytes = min_t(size_t, len, free->length);
3173 boffs = free->offset;
3174 }
3175 memcpy(chip->oob_poi + boffs, oob, bytes);
3176 oob += bytes;
3177 }
3178 return oob;
3179 }
3180 default:
3181 BUG();
3182 }
3183 return NULL;
3184 }
3185
3186 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
3187
3188 /**
3189 * nand_do_write_ops - [INTERN] NAND write with ECC
3190 * @mtd: MTD device structure
3191 * @to: offset to write to
3192 * @ops: oob operations description structure
3193 *
3194 * NAND write with ECC.
3195 */
nand_do_write_ops(struct mtd_info * mtd,loff_t to,struct mtd_oob_ops * ops)3196 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
3197 struct mtd_oob_ops *ops)
3198 {
3199 int chipnr, realpage, page, column;
3200 struct nand_chip *chip = mtd_to_nand(mtd);
3201 uint32_t writelen = ops->len;
3202
3203 uint32_t oobwritelen = ops->ooblen;
3204 uint32_t oobmaxlen = mtd_oobavail(mtd, ops);
3205
3206 uint8_t *oob = ops->oobbuf;
3207 uint8_t *buf = ops->datbuf;
3208 int ret;
3209 int oob_required = oob ? 1 : 0;
3210
3211 ops->retlen = 0;
3212 if (!writelen)
3213 return 0;
3214
3215 /* Reject writes, which are not page aligned */
3216 if (NOTALIGNED(to)) {
3217 pr_notice("%s: attempt to write non page aligned data\n",
3218 __func__);
3219 return -EINVAL;
3220 }
3221
3222 column = to & (mtd->writesize - 1);
3223
3224 chipnr = (int)(to >> chip->chip_shift);
3225 chip->select_chip(mtd, chipnr);
3226
3227 /* Check, if it is write protected */
3228 if (nand_check_wp(mtd)) {
3229 ret = -EIO;
3230 goto err_out;
3231 }
3232
3233 realpage = (int)(to >> chip->page_shift);
3234 page = realpage & chip->pagemask;
3235
3236 /* Invalidate the page cache, when we write to the cached page */
3237 if (to <= ((loff_t)chip->pagebuf << chip->page_shift) &&
3238 ((loff_t)chip->pagebuf << chip->page_shift) < (to + ops->len))
3239 chip->pagebuf = -1;
3240
3241 /* Don't allow multipage oob writes with offset */
3242 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
3243 ret = -EINVAL;
3244 goto err_out;
3245 }
3246
3247 while (1) {
3248 int bytes = mtd->writesize;
3249 uint8_t *wbuf = buf;
3250 int use_bufpoi;
3251 int part_pagewr = (column || writelen < mtd->writesize);
3252
3253 if (part_pagewr)
3254 use_bufpoi = 1;
3255 else if (chip->options & NAND_USE_BOUNCE_BUFFER)
3256 use_bufpoi = !IS_ALIGNED((unsigned long)buf,
3257 chip->buf_align);
3258 else
3259 use_bufpoi = 0;
3260
3261 WATCHDOG_RESET();
3262 /* Partial page write?, or need to use bounce buffer */
3263 if (use_bufpoi) {
3264 pr_debug("%s: using write bounce buffer for buf@%p\n",
3265 __func__, buf);
3266 if (part_pagewr)
3267 bytes = min_t(int, bytes - column, writelen);
3268 chip->pagebuf = -1;
3269 memset(chip->buffers->databuf, 0xff, mtd->writesize);
3270 memcpy(&chip->buffers->databuf[column], buf, bytes);
3271 wbuf = chip->buffers->databuf;
3272 }
3273
3274 if (unlikely(oob)) {
3275 size_t len = min(oobwritelen, oobmaxlen);
3276 oob = nand_fill_oob(mtd, oob, len, ops);
3277 oobwritelen -= len;
3278 } else {
3279 /* We still need to erase leftover OOB data */
3280 memset(chip->oob_poi, 0xff, mtd->oobsize);
3281 }
3282 ret = chip->write_page(mtd, chip, column, bytes, wbuf,
3283 oob_required, page,
3284 (ops->mode == MTD_OPS_RAW));
3285 if (ret)
3286 break;
3287
3288 writelen -= bytes;
3289 if (!writelen)
3290 break;
3291
3292 column = 0;
3293 buf += bytes;
3294 realpage++;
3295
3296 page = realpage & chip->pagemask;
3297 /* Check, if we cross a chip boundary */
3298 if (!page) {
3299 chipnr++;
3300 chip->select_chip(mtd, -1);
3301 chip->select_chip(mtd, chipnr);
3302 }
3303 }
3304
3305 ops->retlen = ops->len - writelen;
3306 if (unlikely(oob))
3307 ops->oobretlen = ops->ooblen;
3308
3309 err_out:
3310 chip->select_chip(mtd, -1);
3311 return ret;
3312 }
3313
3314 /**
3315 * panic_nand_write - [MTD Interface] NAND write with ECC
3316 * @mtd: MTD device structure
3317 * @to: offset to write to
3318 * @len: number of bytes to write
3319 * @retlen: pointer to variable to store the number of written bytes
3320 * @buf: the data to write
3321 *
3322 * NAND write with ECC. Used when performing writes in interrupt context, this
3323 * may for example be called by mtdoops when writing an oops while in panic.
3324 */
panic_nand_write(struct mtd_info * mtd,loff_t to,size_t len,size_t * retlen,const uint8_t * buf)3325 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
3326 size_t *retlen, const uint8_t *buf)
3327 {
3328 struct nand_chip *chip = mtd_to_nand(mtd);
3329 struct mtd_oob_ops ops;
3330 int ret;
3331
3332 /* Wait for the device to get ready */
3333 panic_nand_wait(mtd, chip, 400);
3334
3335 /* Grab the device */
3336 panic_nand_get_device(chip, mtd, FL_WRITING);
3337
3338 memset(&ops, 0, sizeof(ops));
3339 ops.len = len;
3340 ops.datbuf = (uint8_t *)buf;
3341 ops.mode = MTD_OPS_PLACE_OOB;
3342
3343 ret = nand_do_write_ops(mtd, to, &ops);
3344
3345 *retlen = ops.retlen;
3346 return ret;
3347 }
3348
3349 /**
3350 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
3351 * @mtd: MTD device structure
3352 * @to: offset to write to
3353 * @ops: oob operation description structure
3354 *
3355 * NAND write out-of-band.
3356 */
nand_do_write_oob(struct mtd_info * mtd,loff_t to,struct mtd_oob_ops * ops)3357 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
3358 struct mtd_oob_ops *ops)
3359 {
3360 int chipnr, page, status, len;
3361 struct nand_chip *chip = mtd_to_nand(mtd);
3362
3363 pr_debug("%s: to = 0x%08x, len = %i\n",
3364 __func__, (unsigned int)to, (int)ops->ooblen);
3365
3366 len = mtd_oobavail(mtd, ops);
3367
3368 /* Do not allow write past end of page */
3369 if ((ops->ooboffs + ops->ooblen) > len) {
3370 pr_debug("%s: attempt to write past end of page\n",
3371 __func__);
3372 return -EINVAL;
3373 }
3374
3375 if (unlikely(ops->ooboffs >= len)) {
3376 pr_debug("%s: attempt to start write outside oob\n",
3377 __func__);
3378 return -EINVAL;
3379 }
3380
3381 /* Do not allow write past end of device */
3382 if (unlikely(to >= mtd->size ||
3383 ops->ooboffs + ops->ooblen >
3384 ((mtd->size >> chip->page_shift) -
3385 (to >> chip->page_shift)) * len)) {
3386 pr_debug("%s: attempt to write beyond end of device\n",
3387 __func__);
3388 return -EINVAL;
3389 }
3390
3391 chipnr = (int)(to >> chip->chip_shift);
3392
3393 /*
3394 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
3395 * of my DiskOnChip 2000 test units) will clear the whole data page too
3396 * if we don't do this. I have no clue why, but I seem to have 'fixed'
3397 * it in the doc2000 driver in August 1999. dwmw2.
3398 */
3399 nand_reset(chip, chipnr);
3400
3401 chip->select_chip(mtd, chipnr);
3402
3403 /* Shift to get page */
3404 page = (int)(to >> chip->page_shift);
3405
3406 /* Check, if it is write protected */
3407 if (nand_check_wp(mtd)) {
3408 chip->select_chip(mtd, -1);
3409 return -EROFS;
3410 }
3411
3412 /* Invalidate the page cache, if we write to the cached page */
3413 if (page == chip->pagebuf)
3414 chip->pagebuf = -1;
3415
3416 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
3417
3418 if (ops->mode == MTD_OPS_RAW)
3419 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
3420 else
3421 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
3422
3423 chip->select_chip(mtd, -1);
3424
3425 if (status)
3426 return status;
3427
3428 ops->oobretlen = ops->ooblen;
3429
3430 return 0;
3431 }
3432
3433 /**
3434 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
3435 * @mtd: MTD device structure
3436 * @to: offset to write to
3437 * @ops: oob operation description structure
3438 */
nand_write_oob(struct mtd_info * mtd,loff_t to,struct mtd_oob_ops * ops)3439 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
3440 struct mtd_oob_ops *ops)
3441 {
3442 int ret = -ENOTSUPP;
3443
3444 ops->retlen = 0;
3445
3446 /* Do not allow writes past end of device */
3447 if (ops->datbuf && (to + ops->len) > mtd->size) {
3448 pr_debug("%s: attempt to write beyond end of device\n",
3449 __func__);
3450 return -EINVAL;
3451 }
3452
3453 nand_get_device(mtd, FL_WRITING);
3454
3455 switch (ops->mode) {
3456 case MTD_OPS_PLACE_OOB:
3457 case MTD_OPS_AUTO_OOB:
3458 case MTD_OPS_RAW:
3459 break;
3460
3461 default:
3462 goto out;
3463 }
3464
3465 if (!ops->datbuf)
3466 ret = nand_do_write_oob(mtd, to, ops);
3467 else
3468 ret = nand_do_write_ops(mtd, to, ops);
3469
3470 out:
3471 nand_release_device(mtd);
3472 return ret;
3473 }
3474
3475 /**
3476 * single_erase - [GENERIC] NAND standard block erase command function
3477 * @mtd: MTD device structure
3478 * @page: the page address of the block which will be erased
3479 *
3480 * Standard erase command for NAND chips. Returns NAND status.
3481 */
single_erase(struct mtd_info * mtd,int page)3482 static int single_erase(struct mtd_info *mtd, int page)
3483 {
3484 struct nand_chip *chip = mtd_to_nand(mtd);
3485 unsigned int eraseblock;
3486
3487 /* Send commands to erase a block */
3488 eraseblock = page >> (chip->phys_erase_shift - chip->page_shift);
3489
3490 return nand_erase_op(chip, eraseblock);
3491 }
3492
3493 /**
3494 * nand_erase - [MTD Interface] erase block(s)
3495 * @mtd: MTD device structure
3496 * @instr: erase instruction
3497 *
3498 * Erase one ore more blocks.
3499 */
nand_erase(struct mtd_info * mtd,struct erase_info * instr)3500 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
3501 {
3502 return nand_erase_nand(mtd, instr, 0);
3503 }
3504
3505 /**
3506 * nand_erase_nand - [INTERN] erase block(s)
3507 * @mtd: MTD device structure
3508 * @instr: erase instruction
3509 * @allowbbt: allow erasing the bbt area
3510 *
3511 * Erase one ore more blocks.
3512 */
nand_erase_nand(struct mtd_info * mtd,struct erase_info * instr,int allowbbt)3513 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
3514 int allowbbt)
3515 {
3516 int page, status, pages_per_block, ret, chipnr;
3517 struct nand_chip *chip = mtd_to_nand(mtd);
3518 loff_t len;
3519
3520 pr_debug("%s: start = 0x%012llx, len = %llu\n",
3521 __func__, (unsigned long long)instr->addr,
3522 (unsigned long long)instr->len);
3523
3524 if (check_offs_len(mtd, instr->addr, instr->len))
3525 return -EINVAL;
3526
3527 /* Grab the lock and see if the device is available */
3528 nand_get_device(mtd, FL_ERASING);
3529
3530 /* Shift to get first page */
3531 page = (int)(instr->addr >> chip->page_shift);
3532 chipnr = (int)(instr->addr >> chip->chip_shift);
3533
3534 /* Calculate pages in each block */
3535 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
3536
3537 /* Select the NAND device */
3538 chip->select_chip(mtd, chipnr);
3539
3540 /* Check, if it is write protected */
3541 if (nand_check_wp(mtd)) {
3542 pr_debug("%s: device is write protected!\n",
3543 __func__);
3544 instr->state = MTD_ERASE_FAILED;
3545 goto erase_exit;
3546 }
3547
3548 /* Loop through the pages */
3549 len = instr->len;
3550
3551 instr->state = MTD_ERASING;
3552
3553 while (len) {
3554 WATCHDOG_RESET();
3555
3556 /* Check if we have a bad block, we do not erase bad blocks! */
3557 if (!instr->scrub && nand_block_checkbad(mtd, ((loff_t) page) <<
3558 chip->page_shift, allowbbt)) {
3559 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
3560 __func__, page);
3561 instr->state = MTD_ERASE_FAILED;
3562 instr->fail_addr =
3563 ((loff_t)page << chip->page_shift);
3564 goto erase_exit;
3565 }
3566
3567 /*
3568 * Invalidate the page cache, if we erase the block which
3569 * contains the current cached page.
3570 */
3571 if (page <= chip->pagebuf && chip->pagebuf <
3572 (page + pages_per_block))
3573 chip->pagebuf = -1;
3574
3575 status = chip->erase(mtd, page & chip->pagemask);
3576
3577 /* See if block erase succeeded */
3578 if (status & NAND_STATUS_FAIL) {
3579 pr_debug("%s: failed erase, page 0x%08x\n",
3580 __func__, page);
3581 instr->state = MTD_ERASE_FAILED;
3582 instr->fail_addr =
3583 ((loff_t)page << chip->page_shift);
3584 goto erase_exit;
3585 }
3586
3587 /* Increment page address and decrement length */
3588 len -= (1ULL << chip->phys_erase_shift);
3589 page += pages_per_block;
3590
3591 /* Check, if we cross a chip boundary */
3592 if (len && !(page & chip->pagemask)) {
3593 chipnr++;
3594 chip->select_chip(mtd, -1);
3595 chip->select_chip(mtd, chipnr);
3596 }
3597 }
3598 instr->state = MTD_ERASE_DONE;
3599
3600 erase_exit:
3601
3602 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
3603
3604 /* Deselect and wake up anyone waiting on the device */
3605 chip->select_chip(mtd, -1);
3606 nand_release_device(mtd);
3607
3608 /* Do call back function */
3609 if (!ret)
3610 mtd_erase_callback(instr);
3611
3612 /* Return more or less happy */
3613 return ret;
3614 }
3615
3616 /**
3617 * nand_sync - [MTD Interface] sync
3618 * @mtd: MTD device structure
3619 *
3620 * Sync is actually a wait for chip ready function.
3621 */
nand_sync(struct mtd_info * mtd)3622 static void nand_sync(struct mtd_info *mtd)
3623 {
3624 pr_debug("%s: called\n", __func__);
3625
3626 /* Grab the lock and see if the device is available */
3627 nand_get_device(mtd, FL_SYNCING);
3628 /* Release it and go back */
3629 nand_release_device(mtd);
3630 }
3631
3632 /**
3633 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
3634 * @mtd: MTD device structure
3635 * @offs: offset relative to mtd start
3636 */
nand_block_isbad(struct mtd_info * mtd,loff_t offs)3637 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
3638 {
3639 struct nand_chip *chip = mtd_to_nand(mtd);
3640 int chipnr = (int)(offs >> chip->chip_shift);
3641 int ret;
3642
3643 /* Select the NAND device */
3644 nand_get_device(mtd, FL_READING);
3645 chip->select_chip(mtd, chipnr);
3646
3647 ret = nand_block_checkbad(mtd, offs, 0);
3648
3649 chip->select_chip(mtd, -1);
3650 nand_release_device(mtd);
3651
3652 return ret;
3653 }
3654
3655 /**
3656 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
3657 * @mtd: MTD device structure
3658 * @ofs: offset relative to mtd start
3659 */
nand_block_markbad(struct mtd_info * mtd,loff_t ofs)3660 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
3661 {
3662 int ret;
3663
3664 ret = nand_block_isbad(mtd, ofs);
3665 if (ret) {
3666 /* If it was bad already, return success and do nothing */
3667 if (ret > 0)
3668 return 0;
3669 return ret;
3670 }
3671
3672 return nand_block_markbad_lowlevel(mtd, ofs);
3673 }
3674
3675 /**
3676 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
3677 * @mtd: MTD device structure
3678 * @chip: nand chip info structure
3679 * @addr: feature address.
3680 * @subfeature_param: the subfeature parameters, a four bytes array.
3681 */
nand_onfi_set_features(struct mtd_info * mtd,struct nand_chip * chip,int addr,uint8_t * subfeature_param)3682 static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
3683 int addr, uint8_t *subfeature_param)
3684 {
3685 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3686 if (!chip->onfi_version ||
3687 !(le16_to_cpu(chip->onfi_params.opt_cmd)
3688 & ONFI_OPT_CMD_SET_GET_FEATURES))
3689 return -ENOTSUPP;
3690 #endif
3691
3692 return nand_set_features_op(chip, addr, subfeature_param);
3693 }
3694
3695 /**
3696 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
3697 * @mtd: MTD device structure
3698 * @chip: nand chip info structure
3699 * @addr: feature address.
3700 * @subfeature_param: the subfeature parameters, a four bytes array.
3701 */
nand_onfi_get_features(struct mtd_info * mtd,struct nand_chip * chip,int addr,uint8_t * subfeature_param)3702 static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
3703 int addr, uint8_t *subfeature_param)
3704 {
3705 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3706 if (!chip->onfi_version ||
3707 !(le16_to_cpu(chip->onfi_params.opt_cmd)
3708 & ONFI_OPT_CMD_SET_GET_FEATURES))
3709 return -ENOTSUPP;
3710 #endif
3711
3712 return nand_get_features_op(chip, addr, subfeature_param);
3713 }
3714
3715 /* Set default functions */
nand_set_defaults(struct nand_chip * chip,int busw)3716 static void nand_set_defaults(struct nand_chip *chip, int busw)
3717 {
3718 /* check for proper chip_delay setup, set 20us if not */
3719 if (!chip->chip_delay)
3720 chip->chip_delay = 20;
3721
3722 /* check, if a user supplied command function given */
3723 if (chip->cmdfunc == NULL)
3724 chip->cmdfunc = nand_command;
3725
3726 /* check, if a user supplied wait function given */
3727 if (chip->waitfunc == NULL)
3728 chip->waitfunc = nand_wait;
3729
3730 if (!chip->select_chip)
3731 chip->select_chip = nand_select_chip;
3732
3733 /* set for ONFI nand */
3734 if (!chip->onfi_set_features)
3735 chip->onfi_set_features = nand_onfi_set_features;
3736 if (!chip->onfi_get_features)
3737 chip->onfi_get_features = nand_onfi_get_features;
3738
3739 /* If called twice, pointers that depend on busw may need to be reset */
3740 if (!chip->read_byte || chip->read_byte == nand_read_byte)
3741 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
3742 if (!chip->read_word)
3743 chip->read_word = nand_read_word;
3744 if (!chip->block_bad)
3745 chip->block_bad = nand_block_bad;
3746 if (!chip->block_markbad)
3747 chip->block_markbad = nand_default_block_markbad;
3748 if (!chip->write_buf || chip->write_buf == nand_write_buf)
3749 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
3750 if (!chip->write_byte || chip->write_byte == nand_write_byte)
3751 chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
3752 if (!chip->read_buf || chip->read_buf == nand_read_buf)
3753 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
3754 if (!chip->scan_bbt)
3755 chip->scan_bbt = nand_default_bbt;
3756
3757 if (!chip->controller) {
3758 chip->controller = &chip->hwcontrol;
3759 spin_lock_init(&chip->controller->lock);
3760 init_waitqueue_head(&chip->controller->wq);
3761 }
3762
3763 if (!chip->buf_align)
3764 chip->buf_align = 1;
3765 }
3766
3767 /* Sanitize ONFI strings so we can safely print them */
sanitize_string(char * s,size_t len)3768 static void sanitize_string(char *s, size_t len)
3769 {
3770 ssize_t i;
3771
3772 /* Null terminate */
3773 s[len - 1] = 0;
3774
3775 /* Remove non printable chars */
3776 for (i = 0; i < len - 1; i++) {
3777 if (s[i] < ' ' || s[i] > 127)
3778 s[i] = '?';
3779 }
3780
3781 /* Remove trailing spaces */
3782 strim(s);
3783 }
3784
onfi_crc16(u16 crc,u8 const * p,size_t len)3785 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
3786 {
3787 int i;
3788 while (len--) {
3789 crc ^= *p++ << 8;
3790 for (i = 0; i < 8; i++)
3791 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
3792 }
3793
3794 return crc;
3795 }
3796
3797 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3798 /* Parse the Extended Parameter Page. */
nand_flash_detect_ext_param_page(struct mtd_info * mtd,struct nand_chip * chip,struct nand_onfi_params * p)3799 static int nand_flash_detect_ext_param_page(struct mtd_info *mtd,
3800 struct nand_chip *chip, struct nand_onfi_params *p)
3801 {
3802 struct onfi_ext_param_page *ep;
3803 struct onfi_ext_section *s;
3804 struct onfi_ext_ecc_info *ecc;
3805 uint8_t *cursor;
3806 int ret;
3807 int len;
3808 int i;
3809
3810 len = le16_to_cpu(p->ext_param_page_length) * 16;
3811 ep = kmalloc(len, GFP_KERNEL);
3812 if (!ep)
3813 return -ENOMEM;
3814
3815 /* Send our own NAND_CMD_PARAM. */
3816 ret = nand_read_param_page_op(chip, 0, NULL, 0);
3817 if (ret)
3818 goto ext_out;
3819
3820 /* Use the Change Read Column command to skip the ONFI param pages. */
3821 ret = nand_change_read_column_op(chip,
3822 sizeof(*p) * p->num_of_param_pages,
3823 ep, len, true);
3824 if (ret)
3825 goto ext_out;
3826
3827 ret = -EINVAL;
3828 if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
3829 != le16_to_cpu(ep->crc))) {
3830 pr_debug("fail in the CRC.\n");
3831 goto ext_out;
3832 }
3833
3834 /*
3835 * Check the signature.
3836 * Do not strictly follow the ONFI spec, maybe changed in future.
3837 */
3838 if (strncmp((char *)ep->sig, "EPPS", 4)) {
3839 pr_debug("The signature is invalid.\n");
3840 goto ext_out;
3841 }
3842
3843 /* find the ECC section. */
3844 cursor = (uint8_t *)(ep + 1);
3845 for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
3846 s = ep->sections + i;
3847 if (s->type == ONFI_SECTION_TYPE_2)
3848 break;
3849 cursor += s->length * 16;
3850 }
3851 if (i == ONFI_EXT_SECTION_MAX) {
3852 pr_debug("We can not find the ECC section.\n");
3853 goto ext_out;
3854 }
3855
3856 /* get the info we want. */
3857 ecc = (struct onfi_ext_ecc_info *)cursor;
3858
3859 if (!ecc->codeword_size) {
3860 pr_debug("Invalid codeword size\n");
3861 goto ext_out;
3862 }
3863
3864 chip->ecc_strength_ds = ecc->ecc_bits;
3865 chip->ecc_step_ds = 1 << ecc->codeword_size;
3866 ret = 0;
3867
3868 ext_out:
3869 kfree(ep);
3870 return ret;
3871 }
3872
nand_setup_read_retry_micron(struct mtd_info * mtd,int retry_mode)3873 static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode)
3874 {
3875 struct nand_chip *chip = mtd_to_nand(mtd);
3876 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode};
3877
3878 return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY,
3879 feature);
3880 }
3881
3882 /*
3883 * Configure chip properties from Micron vendor-specific ONFI table
3884 */
nand_onfi_detect_micron(struct nand_chip * chip,struct nand_onfi_params * p)3885 static void nand_onfi_detect_micron(struct nand_chip *chip,
3886 struct nand_onfi_params *p)
3887 {
3888 struct nand_onfi_vendor_micron *micron = (void *)p->vendor;
3889
3890 if (le16_to_cpu(p->vendor_revision) < 1)
3891 return;
3892
3893 chip->read_retries = micron->read_retry_options;
3894 chip->setup_read_retry = nand_setup_read_retry_micron;
3895 }
3896
3897 /*
3898 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
3899 */
nand_flash_detect_onfi(struct mtd_info * mtd,struct nand_chip * chip,int * busw)3900 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
3901 int *busw)
3902 {
3903 struct nand_onfi_params *p = &chip->onfi_params;
3904 char id[4];
3905 int i, ret, val;
3906
3907 /* Try ONFI for unknown chip or LP */
3908 ret = nand_readid_op(chip, 0x20, id, sizeof(id));
3909 if (ret || strncmp(id, "ONFI", 4))
3910 return 0;
3911
3912 ret = nand_read_param_page_op(chip, 0, NULL, 0);
3913 if (ret)
3914 return 0;
3915
3916 for (i = 0; i < 3; i++) {
3917 ret = nand_read_data_op(chip, p, sizeof(*p), true);
3918 if (ret)
3919 return 0;
3920
3921 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
3922 le16_to_cpu(p->crc)) {
3923 break;
3924 }
3925 }
3926
3927 if (i == 3) {
3928 pr_err("Could not find valid ONFI parameter page; aborting\n");
3929 return 0;
3930 }
3931
3932 /* Check version */
3933 val = le16_to_cpu(p->revision);
3934 if (val & (1 << 5))
3935 chip->onfi_version = 23;
3936 else if (val & (1 << 4))
3937 chip->onfi_version = 22;
3938 else if (val & (1 << 3))
3939 chip->onfi_version = 21;
3940 else if (val & (1 << 2))
3941 chip->onfi_version = 20;
3942 else if (val & (1 << 1))
3943 chip->onfi_version = 10;
3944
3945 if (!chip->onfi_version) {
3946 pr_info("unsupported ONFI version: %d\n", val);
3947 return 0;
3948 }
3949
3950 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3951 sanitize_string(p->model, sizeof(p->model));
3952 if (!mtd->name)
3953 mtd->name = p->model;
3954
3955 mtd->writesize = le32_to_cpu(p->byte_per_page);
3956
3957 /*
3958 * pages_per_block and blocks_per_lun may not be a power-of-2 size
3959 * (don't ask me who thought of this...). MTD assumes that these
3960 * dimensions will be power-of-2, so just truncate the remaining area.
3961 */
3962 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3963 mtd->erasesize *= mtd->writesize;
3964
3965 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3966
3967 /* See erasesize comment */
3968 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3969 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3970 chip->bits_per_cell = p->bits_per_cell;
3971
3972 if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
3973 *busw = NAND_BUSWIDTH_16;
3974 else
3975 *busw = 0;
3976
3977 if (p->ecc_bits != 0xff) {
3978 chip->ecc_strength_ds = p->ecc_bits;
3979 chip->ecc_step_ds = 512;
3980 } else if (chip->onfi_version >= 21 &&
3981 (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
3982
3983 /*
3984 * The nand_flash_detect_ext_param_page() uses the
3985 * Change Read Column command which maybe not supported
3986 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3987 * now. We do not replace user supplied command function.
3988 */
3989 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3990 chip->cmdfunc = nand_command_lp;
3991
3992 /* The Extended Parameter Page is supported since ONFI 2.1. */
3993 if (nand_flash_detect_ext_param_page(mtd, chip, p))
3994 pr_warn("Failed to detect ONFI extended param page\n");
3995 } else {
3996 pr_warn("Could not retrieve ONFI ECC requirements\n");
3997 }
3998
3999 if (p->jedec_id == NAND_MFR_MICRON)
4000 nand_onfi_detect_micron(chip, p);
4001
4002 return 1;
4003 }
4004 #else
nand_flash_detect_onfi(struct mtd_info * mtd,struct nand_chip * chip,int * busw)4005 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
4006 int *busw)
4007 {
4008 return 0;
4009 }
4010 #endif
4011
4012 /*
4013 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
4014 */
nand_flash_detect_jedec(struct mtd_info * mtd,struct nand_chip * chip,int * busw)4015 static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip,
4016 int *busw)
4017 {
4018 struct nand_jedec_params *p = &chip->jedec_params;
4019 struct jedec_ecc_info *ecc;
4020 char id[5];
4021 int i, val, ret;
4022
4023 /* Try JEDEC for unknown chip or LP */
4024 ret = nand_readid_op(chip, 0x40, id, sizeof(id));
4025 if (ret || strncmp(id, "JEDEC", sizeof(id)))
4026 return 0;
4027
4028 ret = nand_read_param_page_op(chip, 0x40, NULL, 0);
4029 if (ret)
4030 return 0;
4031
4032 for (i = 0; i < 3; i++) {
4033 ret = nand_read_data_op(chip, p, sizeof(*p), true);
4034 if (ret)
4035 return 0;
4036
4037 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) ==
4038 le16_to_cpu(p->crc))
4039 break;
4040 }
4041
4042 if (i == 3) {
4043 pr_err("Could not find valid JEDEC parameter page; aborting\n");
4044 return 0;
4045 }
4046
4047 /* Check version */
4048 val = le16_to_cpu(p->revision);
4049 if (val & (1 << 2))
4050 chip->jedec_version = 10;
4051 else if (val & (1 << 1))
4052 chip->jedec_version = 1; /* vendor specific version */
4053
4054 if (!chip->jedec_version) {
4055 pr_info("unsupported JEDEC version: %d\n", val);
4056 return 0;
4057 }
4058
4059 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
4060 sanitize_string(p->model, sizeof(p->model));
4061 if (!mtd->name)
4062 mtd->name = p->model;
4063
4064 mtd->writesize = le32_to_cpu(p->byte_per_page);
4065
4066 /* Please reference to the comment for nand_flash_detect_onfi. */
4067 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
4068 mtd->erasesize *= mtd->writesize;
4069
4070 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
4071
4072 /* Please reference to the comment for nand_flash_detect_onfi. */
4073 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
4074 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
4075 chip->bits_per_cell = p->bits_per_cell;
4076
4077 if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS)
4078 *busw = NAND_BUSWIDTH_16;
4079 else
4080 *busw = 0;
4081
4082 /* ECC info */
4083 ecc = &p->ecc_info[0];
4084
4085 if (ecc->codeword_size >= 9) {
4086 chip->ecc_strength_ds = ecc->ecc_bits;
4087 chip->ecc_step_ds = 1 << ecc->codeword_size;
4088 } else {
4089 pr_warn("Invalid codeword size\n");
4090 }
4091
4092 return 1;
4093 }
4094
4095 /*
4096 * nand_id_has_period - Check if an ID string has a given wraparound period
4097 * @id_data: the ID string
4098 * @arrlen: the length of the @id_data array
4099 * @period: the period of repitition
4100 *
4101 * Check if an ID string is repeated within a given sequence of bytes at
4102 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
4103 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
4104 * if the repetition has a period of @period; otherwise, returns zero.
4105 */
nand_id_has_period(u8 * id_data,int arrlen,int period)4106 static int nand_id_has_period(u8 *id_data, int arrlen, int period)
4107 {
4108 int i, j;
4109 for (i = 0; i < period; i++)
4110 for (j = i + period; j < arrlen; j += period)
4111 if (id_data[i] != id_data[j])
4112 return 0;
4113 return 1;
4114 }
4115
4116 /*
4117 * nand_id_len - Get the length of an ID string returned by CMD_READID
4118 * @id_data: the ID string
4119 * @arrlen: the length of the @id_data array
4120
4121 * Returns the length of the ID string, according to known wraparound/trailing
4122 * zero patterns. If no pattern exists, returns the length of the array.
4123 */
nand_id_len(u8 * id_data,int arrlen)4124 static int nand_id_len(u8 *id_data, int arrlen)
4125 {
4126 int last_nonzero, period;
4127
4128 /* Find last non-zero byte */
4129 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
4130 if (id_data[last_nonzero])
4131 break;
4132
4133 /* All zeros */
4134 if (last_nonzero < 0)
4135 return 0;
4136
4137 /* Calculate wraparound period */
4138 for (period = 1; period < arrlen; period++)
4139 if (nand_id_has_period(id_data, arrlen, period))
4140 break;
4141
4142 /* There's a repeated pattern */
4143 if (period < arrlen)
4144 return period;
4145
4146 /* There are trailing zeros */
4147 if (last_nonzero < arrlen - 1)
4148 return last_nonzero + 1;
4149
4150 /* No pattern detected */
4151 return arrlen;
4152 }
4153
4154 /* Extract the bits of per cell from the 3rd byte of the extended ID */
nand_get_bits_per_cell(u8 cellinfo)4155 static int nand_get_bits_per_cell(u8 cellinfo)
4156 {
4157 int bits;
4158
4159 bits = cellinfo & NAND_CI_CELLTYPE_MSK;
4160 bits >>= NAND_CI_CELLTYPE_SHIFT;
4161 return bits + 1;
4162 }
4163
4164 /*
4165 * Many new NAND share similar device ID codes, which represent the size of the
4166 * chip. The rest of the parameters must be decoded according to generic or
4167 * manufacturer-specific "extended ID" decoding patterns.
4168 */
nand_decode_ext_id(struct mtd_info * mtd,struct nand_chip * chip,u8 id_data[8],int * busw)4169 static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
4170 u8 id_data[8], int *busw)
4171 {
4172 int extid, id_len;
4173 /* The 3rd id byte holds MLC / multichip data */
4174 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
4175 /* The 4th id byte is the important one */
4176 extid = id_data[3];
4177
4178 id_len = nand_id_len(id_data, 8);
4179
4180 /*
4181 * Field definitions are in the following datasheets:
4182 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
4183 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
4184 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
4185 *
4186 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
4187 * ID to decide what to do.
4188 */
4189 if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
4190 !nand_is_slc(chip) && id_data[5] != 0x00) {
4191 /* Calc pagesize */
4192 mtd->writesize = 2048 << (extid & 0x03);
4193 extid >>= 2;
4194 /* Calc oobsize */
4195 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
4196 case 1:
4197 mtd->oobsize = 128;
4198 break;
4199 case 2:
4200 mtd->oobsize = 218;
4201 break;
4202 case 3:
4203 mtd->oobsize = 400;
4204 break;
4205 case 4:
4206 mtd->oobsize = 436;
4207 break;
4208 case 5:
4209 mtd->oobsize = 512;
4210 break;
4211 case 6:
4212 mtd->oobsize = 640;
4213 break;
4214 case 7:
4215 default: /* Other cases are "reserved" (unknown) */
4216 mtd->oobsize = 1024;
4217 break;
4218 }
4219 extid >>= 2;
4220 /* Calc blocksize */
4221 mtd->erasesize = (128 * 1024) <<
4222 (((extid >> 1) & 0x04) | (extid & 0x03));
4223 *busw = 0;
4224 } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
4225 !nand_is_slc(chip)) {
4226 unsigned int tmp;
4227
4228 /* Calc pagesize */
4229 mtd->writesize = 2048 << (extid & 0x03);
4230 extid >>= 2;
4231 /* Calc oobsize */
4232 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
4233 case 0:
4234 mtd->oobsize = 128;
4235 break;
4236 case 1:
4237 mtd->oobsize = 224;
4238 break;
4239 case 2:
4240 mtd->oobsize = 448;
4241 break;
4242 case 3:
4243 mtd->oobsize = 64;
4244 break;
4245 case 4:
4246 mtd->oobsize = 32;
4247 break;
4248 case 5:
4249 mtd->oobsize = 16;
4250 break;
4251 default:
4252 mtd->oobsize = 640;
4253 break;
4254 }
4255 extid >>= 2;
4256 /* Calc blocksize */
4257 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
4258 if (tmp < 0x03)
4259 mtd->erasesize = (128 * 1024) << tmp;
4260 else if (tmp == 0x03)
4261 mtd->erasesize = 768 * 1024;
4262 else
4263 mtd->erasesize = (64 * 1024) << tmp;
4264 *busw = 0;
4265 } else {
4266 /* Calc pagesize */
4267 mtd->writesize = 1024 << (extid & 0x03);
4268 extid >>= 2;
4269 /* Calc oobsize */
4270 mtd->oobsize = (8 << (extid & 0x01)) *
4271 (mtd->writesize >> 9);
4272 extid >>= 2;
4273 /* Calc blocksize. Blocksize is multiples of 64KiB */
4274 mtd->erasesize = (64 * 1024) << (extid & 0x03);
4275 extid >>= 2;
4276 /* Get buswidth information */
4277 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
4278
4279 /*
4280 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
4281 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
4282 * follows:
4283 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
4284 * 110b -> 24nm
4285 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
4286 */
4287 if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
4288 nand_is_slc(chip) &&
4289 (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
4290 !(id_data[4] & 0x80) /* !BENAND */) {
4291 mtd->oobsize = 32 * mtd->writesize >> 9;
4292 }
4293
4294 }
4295 }
4296
4297 /*
4298 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
4299 * decodes a matching ID table entry and assigns the MTD size parameters for
4300 * the chip.
4301 */
nand_decode_id(struct mtd_info * mtd,struct nand_chip * chip,struct nand_flash_dev * type,u8 id_data[8],int * busw)4302 static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
4303 struct nand_flash_dev *type, u8 id_data[8],
4304 int *busw)
4305 {
4306 int maf_id = id_data[0];
4307
4308 mtd->erasesize = type->erasesize;
4309 mtd->writesize = type->pagesize;
4310 mtd->oobsize = mtd->writesize / 32;
4311 *busw = type->options & NAND_BUSWIDTH_16;
4312
4313 /* All legacy ID NAND are small-page, SLC */
4314 chip->bits_per_cell = 1;
4315
4316 /*
4317 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
4318 * some Spansion chips have erasesize that conflicts with size
4319 * listed in nand_ids table.
4320 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
4321 */
4322 if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
4323 && id_data[6] == 0x00 && id_data[7] == 0x00
4324 && mtd->writesize == 512) {
4325 mtd->erasesize = 128 * 1024;
4326 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
4327 }
4328 }
4329
4330 /*
4331 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
4332 * heuristic patterns using various detected parameters (e.g., manufacturer,
4333 * page size, cell-type information).
4334 */
nand_decode_bbm_options(struct mtd_info * mtd,struct nand_chip * chip,u8 id_data[8])4335 static void nand_decode_bbm_options(struct mtd_info *mtd,
4336 struct nand_chip *chip, u8 id_data[8])
4337 {
4338 int maf_id = id_data[0];
4339
4340 /* Set the bad block position */
4341 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
4342 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
4343 else
4344 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
4345
4346 /*
4347 * Bad block marker is stored in the last page of each block on Samsung
4348 * and Hynix MLC devices; stored in first two pages of each block on
4349 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
4350 * AMD/Spansion, and Macronix. All others scan only the first page.
4351 */
4352 if (!nand_is_slc(chip) &&
4353 (maf_id == NAND_MFR_SAMSUNG ||
4354 maf_id == NAND_MFR_HYNIX))
4355 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
4356 else if ((nand_is_slc(chip) &&
4357 (maf_id == NAND_MFR_SAMSUNG ||
4358 maf_id == NAND_MFR_HYNIX ||
4359 maf_id == NAND_MFR_TOSHIBA ||
4360 maf_id == NAND_MFR_AMD ||
4361 maf_id == NAND_MFR_MACRONIX)) ||
4362 (mtd->writesize == 2048 &&
4363 maf_id == NAND_MFR_MICRON))
4364 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
4365 }
4366
is_full_id_nand(struct nand_flash_dev * type)4367 static inline bool is_full_id_nand(struct nand_flash_dev *type)
4368 {
4369 return type->id_len;
4370 }
4371
find_full_id_nand(struct mtd_info * mtd,struct nand_chip * chip,struct nand_flash_dev * type,u8 * id_data,int * busw)4372 static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
4373 struct nand_flash_dev *type, u8 *id_data, int *busw)
4374 {
4375 if (!strncmp((char *)type->id, (char *)id_data, type->id_len)) {
4376 mtd->writesize = type->pagesize;
4377 mtd->erasesize = type->erasesize;
4378 mtd->oobsize = type->oobsize;
4379
4380 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
4381 chip->chipsize = (uint64_t)type->chipsize << 20;
4382 chip->options |= type->options;
4383 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
4384 chip->ecc_step_ds = NAND_ECC_STEP(type);
4385 chip->onfi_timing_mode_default =
4386 type->onfi_timing_mode_default;
4387
4388 *busw = type->options & NAND_BUSWIDTH_16;
4389
4390 if (!mtd->name)
4391 mtd->name = type->name;
4392
4393 return true;
4394 }
4395 return false;
4396 }
4397
4398 /*
4399 * Get the flash and manufacturer id and lookup if the type is supported.
4400 */
nand_get_flash_type(struct mtd_info * mtd,struct nand_chip * chip,int * maf_id,int * dev_id,struct nand_flash_dev * type)4401 struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
4402 struct nand_chip *chip,
4403 int *maf_id, int *dev_id,
4404 struct nand_flash_dev *type)
4405 {
4406 int busw, ret;
4407 int maf_idx;
4408 u8 id_data[8];
4409
4410 /*
4411 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
4412 * after power-up.
4413 */
4414 ret = nand_reset(chip, 0);
4415 if (ret)
4416 return ERR_PTR(ret);
4417
4418 /* Select the device */
4419 chip->select_chip(mtd, 0);
4420
4421 /* Send the command for reading device ID */
4422 ret = nand_readid_op(chip, 0, id_data, 2);
4423 if (ret)
4424 return ERR_PTR(ret);
4425
4426 /* Read manufacturer and device IDs */
4427 *maf_id = id_data[0];
4428 *dev_id = id_data[1];
4429
4430 /*
4431 * Try again to make sure, as some systems the bus-hold or other
4432 * interface concerns can cause random data which looks like a
4433 * possibly credible NAND flash to appear. If the two results do
4434 * not match, ignore the device completely.
4435 */
4436
4437 /* Read entire ID string */
4438 ret = nand_readid_op(chip, 0, id_data, 8);
4439 if (ret)
4440 return ERR_PTR(ret);
4441
4442 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
4443 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
4444 *maf_id, *dev_id, id_data[0], id_data[1]);
4445 return ERR_PTR(-ENODEV);
4446 }
4447
4448 if (!type)
4449 type = nand_flash_ids;
4450
4451 for (; type->name != NULL; type++) {
4452 if (is_full_id_nand(type)) {
4453 if (find_full_id_nand(mtd, chip, type, id_data, &busw))
4454 goto ident_done;
4455 } else if (*dev_id == type->dev_id) {
4456 break;
4457 }
4458 }
4459
4460 chip->onfi_version = 0;
4461 if (!type->name || !type->pagesize) {
4462 /* Check if the chip is ONFI compliant */
4463 if (nand_flash_detect_onfi(mtd, chip, &busw))
4464 goto ident_done;
4465
4466 /* Check if the chip is JEDEC compliant */
4467 if (nand_flash_detect_jedec(mtd, chip, &busw))
4468 goto ident_done;
4469 }
4470
4471 if (!type->name)
4472 return ERR_PTR(-ENODEV);
4473
4474 if (!mtd->name)
4475 mtd->name = type->name;
4476
4477 chip->chipsize = (uint64_t)type->chipsize << 20;
4478
4479 if (!type->pagesize) {
4480 /* Decode parameters from extended ID */
4481 nand_decode_ext_id(mtd, chip, id_data, &busw);
4482 } else {
4483 nand_decode_id(mtd, chip, type, id_data, &busw);
4484 }
4485 /* Get chip options */
4486 chip->options |= type->options;
4487
4488 /*
4489 * Check if chip is not a Samsung device. Do not clear the
4490 * options for chips which do not have an extended id.
4491 */
4492 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
4493 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
4494 ident_done:
4495
4496 /* Try to identify manufacturer */
4497 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
4498 if (nand_manuf_ids[maf_idx].id == *maf_id)
4499 break;
4500 }
4501
4502 if (chip->options & NAND_BUSWIDTH_AUTO) {
4503 WARN_ON(chip->options & NAND_BUSWIDTH_16);
4504 chip->options |= busw;
4505 nand_set_defaults(chip, busw);
4506 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
4507 /*
4508 * Check, if buswidth is correct. Hardware drivers should set
4509 * chip correct!
4510 */
4511 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
4512 *maf_id, *dev_id);
4513 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name);
4514 pr_warn("bus width %d instead %d bit\n",
4515 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
4516 busw ? 16 : 8);
4517 return ERR_PTR(-EINVAL);
4518 }
4519
4520 nand_decode_bbm_options(mtd, chip, id_data);
4521
4522 /* Calculate the address shift from the page size */
4523 chip->page_shift = ffs(mtd->writesize) - 1;
4524 /* Convert chipsize to number of pages per chip -1 */
4525 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
4526
4527 chip->bbt_erase_shift = chip->phys_erase_shift =
4528 ffs(mtd->erasesize) - 1;
4529 if (chip->chipsize & 0xffffffff)
4530 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
4531 else {
4532 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
4533 chip->chip_shift += 32 - 1;
4534 }
4535
4536 if (chip->chip_shift - chip->page_shift > 16)
4537 chip->options |= NAND_ROW_ADDR_3;
4538
4539 chip->badblockbits = 8;
4540 chip->erase = single_erase;
4541
4542 /* Do not replace user supplied command function! */
4543 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
4544 chip->cmdfunc = nand_command_lp;
4545
4546 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
4547 *maf_id, *dev_id);
4548
4549 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
4550 if (chip->onfi_version)
4551 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
4552 chip->onfi_params.model);
4553 else if (chip->jedec_version)
4554 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
4555 chip->jedec_params.model);
4556 else
4557 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
4558 type->name);
4559 #else
4560 if (chip->jedec_version)
4561 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
4562 chip->jedec_params.model);
4563 else
4564 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
4565 type->name);
4566
4567 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
4568 type->name);
4569 #endif
4570
4571 pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
4572 (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
4573 mtd->erasesize >> 10, mtd->writesize, mtd->oobsize);
4574 return type;
4575 }
4576 EXPORT_SYMBOL(nand_get_flash_type);
4577
4578 #if CONFIG_IS_ENABLED(OF_CONTROL)
4579 #include <asm/global_data.h>
4580 DECLARE_GLOBAL_DATA_PTR;
4581
nand_dt_init(struct mtd_info * mtd,struct nand_chip * chip,int node)4582 static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, int node)
4583 {
4584 int ret, ecc_mode = -1, ecc_strength, ecc_step;
4585 const void *blob = gd->fdt_blob;
4586 const char *str;
4587
4588 ret = fdtdec_get_int(blob, node, "nand-bus-width", -1);
4589 if (ret == 16)
4590 chip->options |= NAND_BUSWIDTH_16;
4591
4592 if (fdtdec_get_bool(blob, node, "nand-on-flash-bbt"))
4593 chip->bbt_options |= NAND_BBT_USE_FLASH;
4594
4595 str = fdt_getprop(blob, node, "nand-ecc-mode", NULL);
4596 if (str) {
4597 if (!strcmp(str, "none"))
4598 ecc_mode = NAND_ECC_NONE;
4599 else if (!strcmp(str, "soft"))
4600 ecc_mode = NAND_ECC_SOFT;
4601 else if (!strcmp(str, "hw"))
4602 ecc_mode = NAND_ECC_HW;
4603 else if (!strcmp(str, "hw_syndrome"))
4604 ecc_mode = NAND_ECC_HW_SYNDROME;
4605 else if (!strcmp(str, "hw_oob_first"))
4606 ecc_mode = NAND_ECC_HW_OOB_FIRST;
4607 else if (!strcmp(str, "soft_bch"))
4608 ecc_mode = NAND_ECC_SOFT_BCH;
4609 }
4610
4611
4612 ecc_strength = fdtdec_get_int(blob, node, "nand-ecc-strength", -1);
4613 ecc_step = fdtdec_get_int(blob, node, "nand-ecc-step-size", -1);
4614
4615 if ((ecc_step >= 0 && !(ecc_strength >= 0)) ||
4616 (!(ecc_step >= 0) && ecc_strength >= 0)) {
4617 pr_err("must set both strength and step size in DT\n");
4618 return -EINVAL;
4619 }
4620
4621 if (ecc_mode >= 0)
4622 chip->ecc.mode = ecc_mode;
4623
4624 if (ecc_strength >= 0)
4625 chip->ecc.strength = ecc_strength;
4626
4627 if (ecc_step > 0)
4628 chip->ecc.size = ecc_step;
4629
4630 if (fdt_getprop(blob, node, "nand-ecc-maximize", NULL))
4631 chip->ecc.options |= NAND_ECC_MAXIMIZE;
4632
4633 return 0;
4634 }
4635 #else
nand_dt_init(struct mtd_info * mtd,struct nand_chip * chip,int node)4636 static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, int node)
4637 {
4638 return 0;
4639 }
4640 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
4641
4642 /**
4643 * nand_scan_ident - [NAND Interface] Scan for the NAND device
4644 * @mtd: MTD device structure
4645 * @maxchips: number of chips to scan for
4646 * @table: alternative NAND ID table
4647 *
4648 * This is the first phase of the normal nand_scan() function. It reads the
4649 * flash ID and sets up MTD fields accordingly.
4650 *
4651 */
nand_scan_ident(struct mtd_info * mtd,int maxchips,struct nand_flash_dev * table)4652 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
4653 struct nand_flash_dev *table)
4654 {
4655 int i, nand_maf_id, nand_dev_id;
4656 struct nand_chip *chip = mtd_to_nand(mtd);
4657 struct nand_flash_dev *type;
4658 int ret;
4659
4660 if (chip->flash_node) {
4661 ret = nand_dt_init(mtd, chip, chip->flash_node);
4662 if (ret)
4663 return ret;
4664 }
4665
4666 /* Set the default functions */
4667 nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16);
4668
4669 /* Read the flash type */
4670 type = nand_get_flash_type(mtd, chip, &nand_maf_id,
4671 &nand_dev_id, table);
4672
4673 if (IS_ERR(type)) {
4674 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
4675 pr_warn("No NAND device found\n");
4676 chip->select_chip(mtd, -1);
4677 return PTR_ERR(type);
4678 }
4679
4680 /* Initialize the ->data_interface field. */
4681 ret = nand_init_data_interface(chip);
4682 if (ret)
4683 return ret;
4684
4685 /*
4686 * Setup the data interface correctly on the chip and controller side.
4687 * This explicit call to nand_setup_data_interface() is only required
4688 * for the first die, because nand_reset() has been called before
4689 * ->data_interface and ->default_onfi_timing_mode were set.
4690 * For the other dies, nand_reset() will automatically switch to the
4691 * best mode for us.
4692 */
4693 ret = nand_setup_data_interface(chip, 0);
4694 if (ret)
4695 return ret;
4696
4697 chip->select_chip(mtd, -1);
4698
4699 /* Check for a chip array */
4700 for (i = 1; i < maxchips; i++) {
4701 u8 id[2];
4702
4703 /* See comment in nand_get_flash_type for reset */
4704 nand_reset(chip, i);
4705
4706 chip->select_chip(mtd, i);
4707 /* Send the command for reading device ID */
4708 nand_readid_op(chip, 0, id, sizeof(id));
4709
4710 /* Read manufacturer and device IDs */
4711 if (nand_maf_id != id[0] || nand_dev_id != id[1]) {
4712 chip->select_chip(mtd, -1);
4713 break;
4714 }
4715 chip->select_chip(mtd, -1);
4716 }
4717
4718 #ifdef DEBUG
4719 if (i > 1)
4720 pr_info("%d chips detected\n", i);
4721 #endif
4722
4723 /* Store the number of chips and calc total size for mtd */
4724 chip->numchips = i;
4725 mtd->size = i * chip->chipsize;
4726
4727 return 0;
4728 }
4729 EXPORT_SYMBOL(nand_scan_ident);
4730
4731 /**
4732 * nand_check_ecc_caps - check the sanity of preset ECC settings
4733 * @chip: nand chip info structure
4734 * @caps: ECC caps info structure
4735 * @oobavail: OOB size that the ECC engine can use
4736 *
4737 * When ECC step size and strength are already set, check if they are supported
4738 * by the controller and the calculated ECC bytes fit within the chip's OOB.
4739 * On success, the calculated ECC bytes is set.
4740 */
nand_check_ecc_caps(struct nand_chip * chip,const struct nand_ecc_caps * caps,int oobavail)4741 int nand_check_ecc_caps(struct nand_chip *chip,
4742 const struct nand_ecc_caps *caps, int oobavail)
4743 {
4744 struct mtd_info *mtd = nand_to_mtd(chip);
4745 const struct nand_ecc_step_info *stepinfo;
4746 int preset_step = chip->ecc.size;
4747 int preset_strength = chip->ecc.strength;
4748 int nsteps, ecc_bytes;
4749 int i, j;
4750
4751 if (WARN_ON(oobavail < 0))
4752 return -EINVAL;
4753
4754 if (!preset_step || !preset_strength)
4755 return -ENODATA;
4756
4757 nsteps = mtd->writesize / preset_step;
4758
4759 for (i = 0; i < caps->nstepinfos; i++) {
4760 stepinfo = &caps->stepinfos[i];
4761
4762 if (stepinfo->stepsize != preset_step)
4763 continue;
4764
4765 for (j = 0; j < stepinfo->nstrengths; j++) {
4766 if (stepinfo->strengths[j] != preset_strength)
4767 continue;
4768
4769 ecc_bytes = caps->calc_ecc_bytes(preset_step,
4770 preset_strength);
4771 if (WARN_ON_ONCE(ecc_bytes < 0))
4772 return ecc_bytes;
4773
4774 if (ecc_bytes * nsteps > oobavail) {
4775 pr_err("ECC (step, strength) = (%d, %d) does not fit in OOB",
4776 preset_step, preset_strength);
4777 return -ENOSPC;
4778 }
4779
4780 chip->ecc.bytes = ecc_bytes;
4781
4782 return 0;
4783 }
4784 }
4785
4786 pr_err("ECC (step, strength) = (%d, %d) not supported on this controller",
4787 preset_step, preset_strength);
4788
4789 return -ENOTSUPP;
4790 }
4791 EXPORT_SYMBOL_GPL(nand_check_ecc_caps);
4792
4793 /**
4794 * nand_match_ecc_req - meet the chip's requirement with least ECC bytes
4795 * @chip: nand chip info structure
4796 * @caps: ECC engine caps info structure
4797 * @oobavail: OOB size that the ECC engine can use
4798 *
4799 * If a chip's ECC requirement is provided, try to meet it with the least
4800 * number of ECC bytes (i.e. with the largest number of OOB-free bytes).
4801 * On success, the chosen ECC settings are set.
4802 */
nand_match_ecc_req(struct nand_chip * chip,const struct nand_ecc_caps * caps,int oobavail)4803 int nand_match_ecc_req(struct nand_chip *chip,
4804 const struct nand_ecc_caps *caps, int oobavail)
4805 {
4806 struct mtd_info *mtd = nand_to_mtd(chip);
4807 const struct nand_ecc_step_info *stepinfo;
4808 int req_step = chip->ecc_step_ds;
4809 int req_strength = chip->ecc_strength_ds;
4810 int req_corr, step_size, strength, nsteps, ecc_bytes, ecc_bytes_total;
4811 int best_step, best_strength, best_ecc_bytes;
4812 int best_ecc_bytes_total = INT_MAX;
4813 int i, j;
4814
4815 if (WARN_ON(oobavail < 0))
4816 return -EINVAL;
4817
4818 /* No information provided by the NAND chip */
4819 if (!req_step || !req_strength)
4820 return -ENOTSUPP;
4821
4822 /* number of correctable bits the chip requires in a page */
4823 req_corr = mtd->writesize / req_step * req_strength;
4824
4825 for (i = 0; i < caps->nstepinfos; i++) {
4826 stepinfo = &caps->stepinfos[i];
4827 step_size = stepinfo->stepsize;
4828
4829 for (j = 0; j < stepinfo->nstrengths; j++) {
4830 strength = stepinfo->strengths[j];
4831
4832 /*
4833 * If both step size and strength are smaller than the
4834 * chip's requirement, it is not easy to compare the
4835 * resulted reliability.
4836 */
4837 if (step_size < req_step && strength < req_strength)
4838 continue;
4839
4840 if (mtd->writesize % step_size)
4841 continue;
4842
4843 nsteps = mtd->writesize / step_size;
4844
4845 ecc_bytes = caps->calc_ecc_bytes(step_size, strength);
4846 if (WARN_ON_ONCE(ecc_bytes < 0))
4847 continue;
4848 ecc_bytes_total = ecc_bytes * nsteps;
4849
4850 if (ecc_bytes_total > oobavail ||
4851 strength * nsteps < req_corr)
4852 continue;
4853
4854 /*
4855 * We assume the best is to meet the chip's requrement
4856 * with the least number of ECC bytes.
4857 */
4858 if (ecc_bytes_total < best_ecc_bytes_total) {
4859 best_ecc_bytes_total = ecc_bytes_total;
4860 best_step = step_size;
4861 best_strength = strength;
4862 best_ecc_bytes = ecc_bytes;
4863 }
4864 }
4865 }
4866
4867 if (best_ecc_bytes_total == INT_MAX)
4868 return -ENOTSUPP;
4869
4870 chip->ecc.size = best_step;
4871 chip->ecc.strength = best_strength;
4872 chip->ecc.bytes = best_ecc_bytes;
4873
4874 return 0;
4875 }
4876 EXPORT_SYMBOL_GPL(nand_match_ecc_req);
4877
4878 /**
4879 * nand_maximize_ecc - choose the max ECC strength available
4880 * @chip: nand chip info structure
4881 * @caps: ECC engine caps info structure
4882 * @oobavail: OOB size that the ECC engine can use
4883 *
4884 * Choose the max ECC strength that is supported on the controller, and can fit
4885 * within the chip's OOB. On success, the chosen ECC settings are set.
4886 */
nand_maximize_ecc(struct nand_chip * chip,const struct nand_ecc_caps * caps,int oobavail)4887 int nand_maximize_ecc(struct nand_chip *chip,
4888 const struct nand_ecc_caps *caps, int oobavail)
4889 {
4890 struct mtd_info *mtd = nand_to_mtd(chip);
4891 const struct nand_ecc_step_info *stepinfo;
4892 int step_size, strength, nsteps, ecc_bytes, corr;
4893 int best_corr = 0;
4894 int best_step = 0;
4895 int best_strength, best_ecc_bytes;
4896 int i, j;
4897
4898 if (WARN_ON(oobavail < 0))
4899 return -EINVAL;
4900
4901 for (i = 0; i < caps->nstepinfos; i++) {
4902 stepinfo = &caps->stepinfos[i];
4903 step_size = stepinfo->stepsize;
4904
4905 /* If chip->ecc.size is already set, respect it */
4906 if (chip->ecc.size && step_size != chip->ecc.size)
4907 continue;
4908
4909 for (j = 0; j < stepinfo->nstrengths; j++) {
4910 strength = stepinfo->strengths[j];
4911
4912 if (mtd->writesize % step_size)
4913 continue;
4914
4915 nsteps = mtd->writesize / step_size;
4916
4917 ecc_bytes = caps->calc_ecc_bytes(step_size, strength);
4918 if (WARN_ON_ONCE(ecc_bytes < 0))
4919 continue;
4920
4921 if (ecc_bytes * nsteps > oobavail)
4922 continue;
4923
4924 corr = strength * nsteps;
4925
4926 /*
4927 * If the number of correctable bits is the same,
4928 * bigger step_size has more reliability.
4929 */
4930 if (corr > best_corr ||
4931 (corr == best_corr && step_size > best_step)) {
4932 best_corr = corr;
4933 best_step = step_size;
4934 best_strength = strength;
4935 best_ecc_bytes = ecc_bytes;
4936 }
4937 }
4938 }
4939
4940 if (!best_corr)
4941 return -ENOTSUPP;
4942
4943 chip->ecc.size = best_step;
4944 chip->ecc.strength = best_strength;
4945 chip->ecc.bytes = best_ecc_bytes;
4946
4947 return 0;
4948 }
4949 EXPORT_SYMBOL_GPL(nand_maximize_ecc);
4950
4951 /*
4952 * Check if the chip configuration meet the datasheet requirements.
4953
4954 * If our configuration corrects A bits per B bytes and the minimum
4955 * required correction level is X bits per Y bytes, then we must ensure
4956 * both of the following are true:
4957 *
4958 * (1) A / B >= X / Y
4959 * (2) A >= X
4960 *
4961 * Requirement (1) ensures we can correct for the required bitflip density.
4962 * Requirement (2) ensures we can correct even when all bitflips are clumped
4963 * in the same sector.
4964 */
nand_ecc_strength_good(struct mtd_info * mtd)4965 static bool nand_ecc_strength_good(struct mtd_info *mtd)
4966 {
4967 struct nand_chip *chip = mtd_to_nand(mtd);
4968 struct nand_ecc_ctrl *ecc = &chip->ecc;
4969 int corr, ds_corr;
4970
4971 if (ecc->size == 0 || chip->ecc_step_ds == 0)
4972 /* Not enough information */
4973 return true;
4974
4975 /*
4976 * We get the number of corrected bits per page to compare
4977 * the correction density.
4978 */
4979 corr = (mtd->writesize * ecc->strength) / ecc->size;
4980 ds_corr = (mtd->writesize * chip->ecc_strength_ds) / chip->ecc_step_ds;
4981
4982 return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds;
4983 }
4984
invalid_ecc_page_accessors(struct nand_chip * chip)4985 static bool invalid_ecc_page_accessors(struct nand_chip *chip)
4986 {
4987 struct nand_ecc_ctrl *ecc = &chip->ecc;
4988
4989 if (nand_standard_page_accessors(ecc))
4990 return false;
4991
4992 /*
4993 * NAND_ECC_CUSTOM_PAGE_ACCESS flag is set, make sure the NAND
4994 * controller driver implements all the page accessors because
4995 * default helpers are not suitable when the core does not
4996 * send the READ0/PAGEPROG commands.
4997 */
4998 return (!ecc->read_page || !ecc->write_page ||
4999 !ecc->read_page_raw || !ecc->write_page_raw ||
5000 (NAND_HAS_SUBPAGE_READ(chip) && !ecc->read_subpage) ||
5001 (NAND_HAS_SUBPAGE_WRITE(chip) && !ecc->write_subpage &&
5002 ecc->hwctl && ecc->calculate));
5003 }
5004
5005 /**
5006 * nand_scan_tail - [NAND Interface] Scan for the NAND device
5007 * @mtd: MTD device structure
5008 *
5009 * This is the second phase of the normal nand_scan() function. It fills out
5010 * all the uninitialized function pointers with the defaults and scans for a
5011 * bad block table if appropriate.
5012 */
nand_scan_tail(struct mtd_info * mtd)5013 int nand_scan_tail(struct mtd_info *mtd)
5014 {
5015 int i;
5016 struct nand_chip *chip = mtd_to_nand(mtd);
5017 struct nand_ecc_ctrl *ecc = &chip->ecc;
5018 struct nand_buffers *nbuf;
5019
5020 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
5021 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
5022 !(chip->bbt_options & NAND_BBT_USE_FLASH));
5023
5024 if (invalid_ecc_page_accessors(chip)) {
5025 pr_err("Invalid ECC page accessors setup\n");
5026 return -EINVAL;
5027 }
5028
5029 if (!(chip->options & NAND_OWN_BUFFERS)) {
5030 nbuf = kzalloc(sizeof(struct nand_buffers), GFP_KERNEL);
5031 chip->buffers = nbuf;
5032 } else {
5033 if (!chip->buffers)
5034 return -ENOMEM;
5035 }
5036
5037 /* Set the internal oob buffer location, just after the page data */
5038 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
5039
5040 /*
5041 * If no default placement scheme is given, select an appropriate one.
5042 */
5043 if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
5044 switch (mtd->oobsize) {
5045 #ifndef CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
5046 case 8:
5047 ecc->layout = &nand_oob_8;
5048 break;
5049 case 16:
5050 ecc->layout = &nand_oob_16;
5051 break;
5052 case 64:
5053 ecc->layout = &nand_oob_64;
5054 break;
5055 case 128:
5056 ecc->layout = &nand_oob_128;
5057 break;
5058 #endif
5059 default:
5060 pr_warn("No oob scheme defined for oobsize %d\n",
5061 mtd->oobsize);
5062 BUG();
5063 }
5064 }
5065
5066 if (!chip->write_page)
5067 chip->write_page = nand_write_page;
5068
5069 /*
5070 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
5071 * selected and we have 256 byte pagesize fallback to software ECC
5072 */
5073
5074 switch (ecc->mode) {
5075 case NAND_ECC_HW_OOB_FIRST:
5076 /* Similar to NAND_ECC_HW, but a separate read_page handle */
5077 if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
5078 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
5079 BUG();
5080 }
5081 if (!ecc->read_page)
5082 ecc->read_page = nand_read_page_hwecc_oob_first;
5083
5084 case NAND_ECC_HW:
5085 /* Use standard hwecc read page function? */
5086 if (!ecc->read_page)
5087 ecc->read_page = nand_read_page_hwecc;
5088 if (!ecc->write_page)
5089 ecc->write_page = nand_write_page_hwecc;
5090 if (!ecc->read_page_raw)
5091 ecc->read_page_raw = nand_read_page_raw;
5092 if (!ecc->write_page_raw)
5093 ecc->write_page_raw = nand_write_page_raw;
5094 if (!ecc->read_oob)
5095 ecc->read_oob = nand_read_oob_std;
5096 if (!ecc->write_oob)
5097 ecc->write_oob = nand_write_oob_std;
5098 if (!ecc->read_subpage)
5099 ecc->read_subpage = nand_read_subpage;
5100 if (!ecc->write_subpage && ecc->hwctl && ecc->calculate)
5101 ecc->write_subpage = nand_write_subpage_hwecc;
5102
5103 case NAND_ECC_HW_SYNDROME:
5104 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
5105 (!ecc->read_page ||
5106 ecc->read_page == nand_read_page_hwecc ||
5107 !ecc->write_page ||
5108 ecc->write_page == nand_write_page_hwecc)) {
5109 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
5110 BUG();
5111 }
5112 /* Use standard syndrome read/write page function? */
5113 if (!ecc->read_page)
5114 ecc->read_page = nand_read_page_syndrome;
5115 if (!ecc->write_page)
5116 ecc->write_page = nand_write_page_syndrome;
5117 if (!ecc->read_page_raw)
5118 ecc->read_page_raw = nand_read_page_raw_syndrome;
5119 if (!ecc->write_page_raw)
5120 ecc->write_page_raw = nand_write_page_raw_syndrome;
5121 if (!ecc->read_oob)
5122 ecc->read_oob = nand_read_oob_syndrome;
5123 if (!ecc->write_oob)
5124 ecc->write_oob = nand_write_oob_syndrome;
5125
5126 if (mtd->writesize >= ecc->size) {
5127 if (!ecc->strength) {
5128 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
5129 BUG();
5130 }
5131 break;
5132 }
5133 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
5134 ecc->size, mtd->writesize);
5135 ecc->mode = NAND_ECC_SOFT;
5136
5137 case NAND_ECC_SOFT:
5138 ecc->calculate = nand_calculate_ecc;
5139 ecc->correct = nand_correct_data;
5140 ecc->read_page = nand_read_page_swecc;
5141 ecc->read_subpage = nand_read_subpage;
5142 ecc->write_page = nand_write_page_swecc;
5143 ecc->read_page_raw = nand_read_page_raw;
5144 ecc->write_page_raw = nand_write_page_raw;
5145 ecc->read_oob = nand_read_oob_std;
5146 ecc->write_oob = nand_write_oob_std;
5147 if (!ecc->size)
5148 ecc->size = 256;
5149 ecc->bytes = 3;
5150 ecc->strength = 1;
5151 break;
5152
5153 case NAND_ECC_SOFT_BCH:
5154 if (!mtd_nand_has_bch()) {
5155 pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n");
5156 BUG();
5157 }
5158 ecc->calculate = nand_bch_calculate_ecc;
5159 ecc->correct = nand_bch_correct_data;
5160 ecc->read_page = nand_read_page_swecc;
5161 ecc->read_subpage = nand_read_subpage;
5162 ecc->write_page = nand_write_page_swecc;
5163 ecc->read_page_raw = nand_read_page_raw;
5164 ecc->write_page_raw = nand_write_page_raw;
5165 ecc->read_oob = nand_read_oob_std;
5166 ecc->write_oob = nand_write_oob_std;
5167 /*
5168 * Board driver should supply ecc.size and ecc.strength values
5169 * to select how many bits are correctable. Otherwise, default
5170 * to 4 bits for large page devices.
5171 */
5172 if (!ecc->size && (mtd->oobsize >= 64)) {
5173 ecc->size = 512;
5174 ecc->strength = 4;
5175 }
5176
5177 /* See nand_bch_init() for details. */
5178 ecc->bytes = 0;
5179 ecc->priv = nand_bch_init(mtd);
5180 if (!ecc->priv) {
5181 pr_warn("BCH ECC initialization failed!\n");
5182 BUG();
5183 }
5184 break;
5185
5186 case NAND_ECC_NONE:
5187 pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n");
5188 ecc->read_page = nand_read_page_raw;
5189 ecc->write_page = nand_write_page_raw;
5190 ecc->read_oob = nand_read_oob_std;
5191 ecc->read_page_raw = nand_read_page_raw;
5192 ecc->write_page_raw = nand_write_page_raw;
5193 ecc->write_oob = nand_write_oob_std;
5194 ecc->size = mtd->writesize;
5195 ecc->bytes = 0;
5196 ecc->strength = 0;
5197 break;
5198
5199 default:
5200 pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode);
5201 BUG();
5202 }
5203
5204 /* For many systems, the standard OOB write also works for raw */
5205 if (!ecc->read_oob_raw)
5206 ecc->read_oob_raw = ecc->read_oob;
5207 if (!ecc->write_oob_raw)
5208 ecc->write_oob_raw = ecc->write_oob;
5209
5210 /*
5211 * The number of bytes available for a client to place data into
5212 * the out of band area.
5213 */
5214 mtd->oobavail = 0;
5215 if (ecc->layout) {
5216 for (i = 0; ecc->layout->oobfree[i].length; i++)
5217 mtd->oobavail += ecc->layout->oobfree[i].length;
5218 }
5219
5220 /* ECC sanity check: warn if it's too weak */
5221 if (!nand_ecc_strength_good(mtd))
5222 pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n",
5223 mtd->name);
5224
5225 /*
5226 * Set the number of read / write steps for one page depending on ECC
5227 * mode.
5228 */
5229 ecc->steps = mtd->writesize / ecc->size;
5230 if (ecc->steps * ecc->size != mtd->writesize) {
5231 pr_warn("Invalid ECC parameters\n");
5232 BUG();
5233 }
5234 ecc->total = ecc->steps * ecc->bytes;
5235
5236 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
5237 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
5238 switch (ecc->steps) {
5239 case 2:
5240 mtd->subpage_sft = 1;
5241 break;
5242 case 4:
5243 case 8:
5244 case 16:
5245 mtd->subpage_sft = 2;
5246 break;
5247 }
5248 }
5249 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
5250
5251 /* Initialize state */
5252 chip->state = FL_READY;
5253
5254 /* Invalidate the pagebuffer reference */
5255 chip->pagebuf = -1;
5256
5257 /* Large page NAND with SOFT_ECC should support subpage reads */
5258 switch (ecc->mode) {
5259 case NAND_ECC_SOFT:
5260 case NAND_ECC_SOFT_BCH:
5261 if (chip->page_shift > 9)
5262 chip->options |= NAND_SUBPAGE_READ;
5263 break;
5264
5265 default:
5266 break;
5267 }
5268
5269 /* Fill in remaining MTD driver data */
5270 mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
5271 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
5272 MTD_CAP_NANDFLASH;
5273 mtd->_erase = nand_erase;
5274 mtd->_panic_write = panic_nand_write;
5275 mtd->_read_oob = nand_read_oob;
5276 mtd->_write_oob = nand_write_oob;
5277 mtd->_sync = nand_sync;
5278 mtd->_lock = NULL;
5279 mtd->_unlock = NULL;
5280 mtd->_block_isreserved = nand_block_isreserved;
5281 mtd->_block_isbad = nand_block_isbad;
5282 mtd->_block_markbad = nand_block_markbad;
5283 mtd->writebufsize = mtd->writesize;
5284
5285 /* propagate ecc info to mtd_info */
5286 mtd->ecclayout = ecc->layout;
5287 mtd->ecc_strength = ecc->strength;
5288 mtd->ecc_step_size = ecc->size;
5289 /*
5290 * Initialize bitflip_threshold to its default prior scan_bbt() call.
5291 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
5292 * properly set.
5293 */
5294 if (!mtd->bitflip_threshold)
5295 mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4);
5296
5297 return 0;
5298 }
5299 EXPORT_SYMBOL(nand_scan_tail);
5300
5301 /**
5302 * nand_scan - [NAND Interface] Scan for the NAND device
5303 * @mtd: MTD device structure
5304 * @maxchips: number of chips to scan for
5305 *
5306 * This fills out all the uninitialized function pointers with the defaults.
5307 * The flash ID is read and the mtd/chip structures are filled with the
5308 * appropriate values.
5309 */
nand_scan(struct mtd_info * mtd,int maxchips)5310 int nand_scan(struct mtd_info *mtd, int maxchips)
5311 {
5312 int ret;
5313
5314 ret = nand_scan_ident(mtd, maxchips, NULL);
5315 if (!ret)
5316 ret = nand_scan_tail(mtd);
5317 return ret;
5318 }
5319 EXPORT_SYMBOL(nand_scan);
5320
5321 MODULE_LICENSE("GPL");
5322 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
5323 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
5324 MODULE_DESCRIPTION("Generic NAND flash driver code");
5325