1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2018 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7 #ifndef __SOC_ROCKCHIP_RK3399_PMU_H__ 8 #define __SOC_ROCKCHIP_RK3399_PMU_H__ 9 10 struct rk3399_pmu_regs { 11 u32 pmu_wakeup_cfg[5]; 12 u32 pmu_pwrdn_con; 13 u32 pmu_pwrdn_st; 14 u32 pmu_pll_con; 15 u32 pmu_pwrmode_con; 16 u32 pmu_sft_con; 17 u32 pmu_int_con; 18 u32 pmu_int_st; 19 u32 pmu_gpio0_pos_int_con; 20 u32 pmu_gpio0_net_int_con; 21 u32 pmu_gpio1_pos_int_con; 22 u32 pmu_gpio1_net_int_con; 23 u32 pmu_gpio0_pos_int_st; 24 u32 pmu_gpio0_net_int_st; 25 u32 pmu_gpio1_pos_int_st; 26 u32 pmu_gpio1_net_int_st; 27 u32 pmu_pwrdn_inten; 28 u32 pmu_pwrdn_status; 29 u32 pmu_wakeup_status; 30 u32 pmu_bus_clr; 31 u32 pmu_bus_idle_req; 32 u32 pmu_bus_idle_st; 33 u32 pmu_bus_idle_ack; 34 u32 pmu_cci500_con; 35 u32 pmu_adb400_con; 36 u32 pmu_adb400_st; 37 u32 pmu_power_st; 38 u32 pmu_core_pwr_st; 39 u32 pmu_osc_cnt; 40 u32 pmu_plllock_cnt; 41 u32 pmu_pllrst_cnt; 42 u32 pmu_stable_cnt; 43 u32 pmu_ddrio_pwron_cnt; 44 u32 pmu_wakeup_rst_clr_cnt; 45 u32 pmu_ddr_sref_st; 46 u32 pmu_scu_l_pwrdn_cnt; 47 u32 pmu_scu_l_pwrup_cnt; 48 u32 pmu_scu_b_pwrdn_cnt; 49 u32 pmu_scu_b_pwrup_cnt; 50 u32 pmu_gpu_pwrdn_cnt; 51 u32 pmu_gpu_pwrup_cnt; 52 u32 pmu_center_pwrdn_cnt; 53 u32 pmu_center_pwrup_cnt; 54 u32 pmu_timeout_cnt; 55 u32 pmu_cpu0apm_con; 56 u32 pmu_cpu1apm_con; 57 u32 pmu_cpu2apm_con; 58 u32 pmu_cpu3apm_con; 59 u32 pmu_cpu0bpm_con; 60 u32 pmu_cpu1bpm_con; 61 u32 pmu_noc_auto_ena; 62 u32 pmu_pwrdn_con1; 63 u32 reserved0[0x4]; 64 u32 pmu_sys_reg_reg0; 65 u32 pmu_sys_reg_reg1; 66 u32 pmu_sys_reg_reg2; 67 u32 pmu_sys_reg_reg3; 68 }; 69 70 check_member(rk3399_pmu_regs, pmu_sys_reg_reg3, 0xfc); 71 72 #endif /* __SOC_ROCKCHIP_RK3399_PMU_H__ */ 73