1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2014 Google, Inc 4 * 5 * From Coreboot file of the same name 6 * 7 * Copyright (C) 2007-2008 coresystems GmbH 8 * Copyright (C) 2011 Google Inc. 9 */ 10 11 #ifndef _ACH_ASM_SANDYBRIDGE_H 12 #define _ACH_ASM_SANDYBRIDGE_H 13 14 /* Chipset types */ 15 #define SANDYBRIDGE_MOBILE 0 16 #define SANDYBRIDGE_DESKTOP 1 17 #define SANDYBRIDGE_SERVER 2 18 19 /* Device ID for SandyBridge and IvyBridge */ 20 #define BASE_REV_SNB 0x00 21 #define BASE_REV_IVB 0x50 22 #define BASE_REV_MASK 0x50 23 24 /* SandyBridge CPU stepping */ 25 #define SNB_STEP_D0 (BASE_REV_SNB + 5) /* Also J0 */ 26 #define SNB_STEP_D1 (BASE_REV_SNB + 6) 27 #define SNB_STEP_D2 (BASE_REV_SNB + 7) /* Also J1/Q0 */ 28 29 /* IvyBridge CPU stepping */ 30 #define IVB_STEP_A0 (BASE_REV_IVB + 0) 31 #define IVB_STEP_B0 (BASE_REV_IVB + 2) 32 #define IVB_STEP_C0 (BASE_REV_IVB + 4) 33 #define IVB_STEP_K0 (BASE_REV_IVB + 5) 34 #define IVB_STEP_D0 (BASE_REV_IVB + 6) 35 36 /* Intel Enhanced Debug region must be 4MB */ 37 #define IED_SIZE 0x400000 38 39 /* Northbridge BARs */ 40 #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ 41 #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ 42 #define DEFAULT_RCBABASE 0xfed1c000 43 /* 4 KB per PCIe device */ 44 #define DEFAULT_PCIEXBAR CONFIG_PCIE_ECAM_BASE 45 46 #define IOMMU_BASE1 0xfed90000ULL 47 #define IOMMU_BASE2 0xfed91000ULL 48 49 /* Device 0:0.0 PCI configuration space (Host Bridge) */ 50 #define EPBAR 0x40 51 #define MCHBAR 0x48 52 #define PCIEXBAR 0x60 53 #define DMIBAR 0x68 54 #define X60BAR 0x60 55 56 #define GGC 0x50 /* GMCH Graphics Control */ 57 58 #define DEVEN 0x54 /* Device Enable */ 59 #define DEVEN_PEG60 (1 << 13) 60 #define DEVEN_IGD (1 << 4) 61 #define DEVEN_PEG10 (1 << 3) 62 #define DEVEN_PEG11 (1 << 2) 63 #define DEVEN_PEG12 (1 << 1) 64 #define DEVEN_HOST (1 << 0) 65 66 #define PAM0 0x80 67 #define PAM1 0x81 68 #define PAM2 0x82 69 #define PAM3 0x83 70 #define PAM4 0x84 71 #define PAM5 0x85 72 #define PAM6 0x86 73 74 #define LAC 0x87 /* Legacy Access Control */ 75 #define SMRAM 0x88 /* System Management RAM Control */ 76 #define D_OPEN (1 << 6) 77 #define D_CLS (1 << 5) 78 #define D_LCK (1 << 4) 79 #define G_SMRAME (1 << 3) 80 #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) 81 82 #define TOM 0xa0 83 #define TOUUD 0xa8 /* Top of Upper Usable DRAM */ 84 #define TSEG 0xb8 /* TSEG base */ 85 #define TOLUD 0xbc /* Top of Low Used Memory */ 86 87 #define SKPAD 0xdc /* Scratchpad Data */ 88 89 /* Device 0:1.0 PCI configuration space (PCI Express) */ 90 #define BCTRL1 0x3e /* 16bit */ 91 92 /* Device 0:2.0 PCI configuration space (Graphics Device) */ 93 94 #define MSAC 0x62 /* Multi Size Aperture Control */ 95 #define SWSCI 0xe8 /* SWSCI enable */ 96 #define ASLS 0xfc /* OpRegion Base */ 97 98 /* 99 * MCHBAR 100 */ 101 #define SSKPD 0x5d14 /* 16bit (scratchpad) */ 102 #define BIOS_RESET_CPL 0x5da8 /* 8bit */ 103 104 /* 105 * DMIBAR 106 */ 107 108 #define DMIBAR_REG(x) (DEFAULT_DMIBAR + x) 109 110 /** 111 * bridge_silicon_revision() - Get the Northbridge revision 112 * 113 * @dev: Northbridge device 114 * @return revision ID (bits 3:0) and bridge ID (bits 7:4) 115 */ 116 int bridge_silicon_revision(struct udevice *dev); 117 118 #endif 119