1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <vsprintf.h>
8 #include <asm/global_data.h>
9 #include <asm/mmu.h>
10 #include <asm/immap_85xx.h>
11 #include <asm/processor.h>
12 #include <fsl_ddr_sdram.h>
13 #include <fsl_ddr_dimm_params.h>
14 #include <asm/io.h>
15 #include <asm/fsl_law.h>
16
17 DECLARE_GLOBAL_DATA_PTR;
18
19 #ifndef CONFIG_SYS_DDR_RAW_TIMING
20 #define CONFIG_SYS_DRAM_SIZE 1024
21
22 fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
23 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
24 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
25 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
26 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
27 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
28 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
29 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
30 .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
31 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
32 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
33 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
34 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
35 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
36 .ddr_data_init = CONFIG_MEM_INIT_VALUE,
37 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
38 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
39 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
40 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
41 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
42 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
43 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800,
44 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
45 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
46 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
47 };
48
49 fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = {
50 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
51 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
52 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
53 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_667,
54 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_667,
55 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667,
56 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667,
57 .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
58 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
59 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_667,
60 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_667,
61 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
62 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_667,
63 .ddr_data_init = CONFIG_MEM_INIT_VALUE,
64 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_667,
65 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
66 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
67 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
68 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
69 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
70 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_667,
71 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
72 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
73 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
74 };
75
76 fixed_ddr_parm_t fixed_ddr_parm_0[] = {
77 {750, 850, &ddr_cfg_regs_800},
78 {607, 749, &ddr_cfg_regs_667},
79 {0, 0, NULL}
80 };
81
get_sdram_size(void)82 unsigned long get_sdram_size(void)
83 {
84 struct cpu_type *cpu;
85 phys_size_t ddr_size;
86
87 cpu = gd->arch.cpu;
88 /* P1014 and it's derivatives support max 16it DDR width */
89 if (cpu->soc_ver == SVR_P1014)
90 ddr_size = (CONFIG_SYS_DRAM_SIZE / 2);
91 else
92 ddr_size = CONFIG_SYS_DRAM_SIZE;
93
94 return ddr_size;
95 }
96
97 /*
98 * Fixed sdram init -- doesn't use serial presence detect.
99 */
fixed_sdram(void)100 phys_size_t fixed_sdram(void)
101 {
102 int i;
103 char buf[32];
104 fsl_ddr_cfg_regs_t ddr_cfg_regs;
105 phys_size_t ddr_size;
106 ulong ddr_freq, ddr_freq_mhz;
107 struct cpu_type *cpu;
108
109 #if defined(CONFIG_SYS_RAMBOOT)
110 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
111 #endif
112
113 ddr_freq = get_ddr_freq(0);
114 ddr_freq_mhz = ddr_freq / 1000000;
115
116 printf("Configuring DDR for %s MT/s data rate\n",
117 strmhz(buf, ddr_freq));
118
119 for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
120 if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
121 (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
122 memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
123 sizeof(ddr_cfg_regs));
124 break;
125 }
126 }
127
128 if (fixed_ddr_parm_0[i].max_freq == 0)
129 panic("Unsupported DDR data rate %s MT/s data rate\n",
130 strmhz(buf, ddr_freq));
131
132 cpu = gd->arch.cpu;
133 /* P1014 and it's derivatives support max 16bit DDR width */
134 if (cpu->soc_ver == SVR_P1014) {
135 ddr_cfg_regs.ddr_sdram_cfg &= ~SDRAM_CFG_DBW_MASK;
136 ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_16_BE;
137 /* divide SA and EA by two and then mask the rest so we don't
138 * write to reserved fields */
139 ddr_cfg_regs.cs[0].bnds = (CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff;
140 }
141
142 ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
143 fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
144
145 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
146 LAW_TRGT_IF_DDR_1) < 0) {
147 printf("ERROR setting Local Access Windows for DDR\n");
148 return 0;
149 }
150
151 return ddr_size;
152 }
153
154 #else /* CONFIG_SYS_DDR_RAW_TIMING */
155 /*
156 * Samsung K4B2G0846C-HCF8
157 * The following timing are for "downshift"
158 * i.e. to use CL9 part as CL7
159 * otherwise, tAA, tRCD, tRP will be 13500ps
160 * and tRC will be 49500ps
161 */
162 dimm_params_t ddr_raw_timing = {
163 .n_ranks = 1,
164 .rank_density = 1073741824u,
165 .capacity = 1073741824u,
166 .primary_sdram_width = 32,
167 .ec_sdram_width = 0,
168 .registered_dimm = 0,
169 .mirrored_dimm = 0,
170 .n_row_addr = 15,
171 .n_col_addr = 10,
172 .n_banks_per_sdram_device = 8,
173 .edc_config = 0,
174 .burst_lengths_bitmask = 0x0c,
175
176 .tckmin_x_ps = 1875,
177 .caslat_x = 0x1e << 4, /* 5,6,7,8 */
178 .taa_ps = 13125,
179 .twr_ps = 15000,
180 .trcd_ps = 13125,
181 .trrd_ps = 7500,
182 .trp_ps = 13125,
183 .tras_ps = 37500,
184 .trc_ps = 50625,
185 .trfc_ps = 160000,
186 .twtr_ps = 7500,
187 .trtp_ps = 7500,
188 .refresh_rate_ps = 7800000,
189 .tfaw_ps = 37500,
190 };
191
fsl_ddr_get_dimm_params(dimm_params_t * pdimm,unsigned int controller_number,unsigned int dimm_number)192 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
193 unsigned int controller_number,
194 unsigned int dimm_number)
195 {
196 const char dimm_model[] = "Fixed DDR on board";
197
198 if ((controller_number == 0) && (dimm_number == 0)) {
199 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
200 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
201 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
202 }
203
204 return 0;
205 }
206
fsl_ddr_board_options(memctl_options_t * popts,dimm_params_t * pdimm,unsigned int ctrl_num)207 void fsl_ddr_board_options(memctl_options_t *popts,
208 dimm_params_t *pdimm,
209 unsigned int ctrl_num)
210 {
211 struct cpu_type *cpu;
212 int i;
213 popts->clk_adjust = 6;
214 popts->cpo_override = 0x1f;
215 popts->write_data_delay = 2;
216 popts->half_strength_driver_enable = 1;
217 /* Write leveling override */
218 popts->wrlvl_en = 1;
219 popts->wrlvl_override = 1;
220 popts->wrlvl_sample = 0xf;
221 popts->wrlvl_start = 0x8;
222 popts->trwt_override = 1;
223 popts->trwt = 0;
224
225 cpu = gd->arch.cpu;
226 /* P1014 and it's derivatives support max 16it DDR width */
227 if (cpu->soc_ver == SVR_P1014)
228 popts->data_bus_width = DDR_DATA_BUS_WIDTH_16;
229
230 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
231 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
232 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
233 }
234 }
235
236 #endif /* CONFIG_SYS_DDR_RAW_TIMING */
237