1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG 4 * Patrick Bruenn <p.bruenn@beckhoff.com> 5 * 6 * Configuration settings for Beckhoff CX9020. 7 * 8 * Based on Freescale's Linux i.MX mx53loco.h file: 9 * Copyright (C) 2010-2011 Freescale Semiconductor. 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 #include <asm/arch/imx-regs.h> 16 17 #define CONFIG_CMDLINE_TAG 18 #define CONFIG_SETUP_MEMORY_TAGS 19 #define CONFIG_INITRD_TAG 20 21 #define CONFIG_SYS_FSL_CLK 22 23 /* Size of malloc() pool */ 24 #define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) 25 26 #define CONFIG_REVISION_TAG 27 28 #define CONFIG_MXC_UART_BASE UART2_BASE 29 30 #define CONFIG_FPGA_COUNT 1 31 32 /* MMC Configs */ 33 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 34 #define CONFIG_SYS_FSL_ESDHC_NUM 2 35 36 /* bootz: zImage/initrd.img support */ 37 38 39 /* USB Configs */ 40 #define CONFIG_MXC_USB_PORT 1 41 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 42 #define CONFIG_MXC_USB_FLAGS 0 43 44 /* Command definition */ 45 46 #define CONFIG_LOADADDR 0x70010000 /* loadaddr env var */ 47 48 #define BOOT_TARGET_DEVICES(func) \ 49 func(MMC, mmc, 0) \ 50 func(MMC, mmc, 1) \ 51 func(USB, usb, 0) \ 52 func(PXE, pxe, na) 53 54 #include <config_distro_bootcmd.h> 55 56 #define CONFIG_EXTRA_ENV_SETTINGS \ 57 "fdt_addr_r=0x75000000\0" \ 58 "pxefile_addr_r=0x73000000\0" \ 59 "scriptaddr=0x74000000\0" \ 60 "ramdisk_addr_r=0x80000000\0" \ 61 "kernel_addr_r=0x72000000\0" \ 62 "fdt_high=0xffffffff\0" \ 63 "console=ttymxc1,115200\0" \ 64 "stdin=serial\0" \ 65 "stdout=serial,vidconsole\0" \ 66 "stderr=serial,vidconsole\0" \ 67 "fdtfile=imx53-cx9020.dtb\0" \ 68 BOOTENV 69 70 #define CONFIG_ARP_TIMEOUT 200UL 71 72 /* Miscellaneous configurable options */ 73 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 74 75 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 76 77 /* Physical Memory Map */ 78 #define PHYS_SDRAM_1 CSD0_BASE_ADDR 79 #define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) 80 #define PHYS_SDRAM_2 CSD1_BASE_ADDR 81 #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) 82 #define PHYS_SDRAM_SIZE (gd->ram_size) 83 84 #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) 85 #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) 86 #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) 87 88 #define CONFIG_SYS_INIT_SP_OFFSET \ 89 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 90 #define CONFIG_SYS_INIT_SP_ADDR \ 91 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 92 93 /* environment organization */ 94 95 /* Framebuffer and LCD */ 96 #define CONFIG_IMX_VIDEO_SKIP 97 98 #endif /* __CONFIG_H */ 99