1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (c) 2011 The Chromium OS Authors. 4 */ 5 6 /* Tegra clock control functions */ 7 8 #ifndef _TEGRA_CLOCK_H_ 9 #define _TEGRA_CLOCK_H_ 10 11 struct udevice; 12 13 /* Set of oscillator frequencies supported in the internal API. */ 14 enum clock_osc_freq { 15 /* All in MHz, so 13_0 is 13.0MHz */ 16 CLOCK_OSC_FREQ_13_0, 17 CLOCK_OSC_FREQ_19_2, 18 CLOCK_OSC_FREQ_12_0, 19 CLOCK_OSC_FREQ_26_0, 20 CLOCK_OSC_FREQ_38_4, 21 CLOCK_OSC_FREQ_48_0, 22 23 CLOCK_OSC_FREQ_COUNT, 24 }; 25 26 /* 27 * Note that no Tegra clock register actually uses all of bits 31:28 as 28 * the mux field. Rather, bits 30:28, 29:28, or 28 are used. However, in 29 * those cases, nothing is stored in the bits about the mux field, so it's 30 * safe to pretend that the mux field extends all the way to the end of the 31 * register. As such, the U-Boot clock driver is currently a bit lazy, and 32 * doesn't distinguish between 31:28, 30:28, 29:28 and 28; it just lumps 33 * them all together and pretends they're all 31:28. 34 */ 35 enum { 36 MASK_BITS_31_30, 37 MASK_BITS_31_29, 38 MASK_BITS_31_28, 39 }; 40 41 #include <asm/arch/clock-tables.h> 42 /* PLL stabilization delay in usec */ 43 #define CLOCK_PLL_STABLE_DELAY_US 300 44 45 /* return the current oscillator clock frequency */ 46 enum clock_osc_freq clock_get_osc_freq(void); 47 48 /* return the clk_m frequency */ 49 unsigned int clk_m_get_rate(unsigned int parent_rate); 50 51 /** 52 * Start PLL using the provided configuration parameters. 53 * 54 * @param id clock id 55 * @param divm input divider 56 * @param divn feedback divider 57 * @param divp post divider 2^n 58 * @param cpcon charge pump setup control 59 * @param lfcon loop filter setup control 60 * 61 * @returns monotonic time in us that the PLL will be stable 62 */ 63 unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn, 64 u32 divp, u32 cpcon, u32 lfcon); 65 66 /** 67 * Set PLL output frequency 68 * 69 * @param clkid clock id 70 * @param pllout pll output id 71 * @param rate desired output rate 72 * 73 * @return 0 if ok, -1 on error (invalid clock id or no suitable divider) 74 */ 75 int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, 76 unsigned rate); 77 78 /** 79 * Read low-level parameters of a PLL. 80 * 81 * @param id clock id to read (note: USB is not supported) 82 * @param divm returns input divider 83 * @param divn returns feedback divider 84 * @param divp returns post divider 2^n 85 * @param cpcon returns charge pump setup control 86 * @param lfcon returns loop filter setup control 87 * 88 * @returns 0 if ok, -1 on error (invalid clock id) 89 */ 90 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn, 91 u32 *divp, u32 *cpcon, u32 *lfcon); 92 93 /* 94 * Enable a clock 95 * 96 * @param id clock id 97 */ 98 void clock_enable(enum periph_id clkid); 99 100 /* 101 * Disable a clock 102 * 103 * @param id clock id 104 */ 105 void clock_disable(enum periph_id clkid); 106 107 /* 108 * Set whether a clock is enabled or disabled. 109 * 110 * @param id clock id 111 * @param enable 1 to enable, 0 to disable 112 */ 113 void clock_set_enable(enum periph_id clkid, int enable); 114 115 /** 116 * Reset a peripheral. This puts it in reset, waits for a delay, then takes 117 * it out of reset and waits for th delay again. 118 * 119 * @param periph_id peripheral to reset 120 * @param us_delay time to delay in microseconds 121 */ 122 void reset_periph(enum periph_id periph_id, int us_delay); 123 124 /** 125 * Put a peripheral into or out of reset. 126 * 127 * @param periph_id peripheral to reset 128 * @param enable 1 to put into reset, 0 to take out of reset 129 */ 130 void reset_set_enable(enum periph_id periph_id, int enable); 131 132 133 /* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */ 134 enum crc_reset_id { 135 /* Things we can hold in reset for each CPU */ 136 crc_rst_cpu = 1, 137 crc_rst_de = 1 << 4, /* What is de? */ 138 crc_rst_watchdog = 1 << 8, 139 crc_rst_debug = 1 << 12, 140 }; 141 142 /** 143 * Put parts of the CPU complex into or out of reset.\ 144 * 145 * @param cpu cpu number (0 or 1 on Tegra2, 0-3 on Tegra3) 146 * @param which which parts of the complex to affect (OR of crc_reset_id) 147 * @param reset 1 to assert reset, 0 to de-assert 148 */ 149 void reset_cmplx_set_enable(int cpu, int which, int reset); 150 151 /** 152 * Set the source for a peripheral clock. This plus the divisor sets the 153 * clock rate. You need to look up the datasheet to see the meaning of the 154 * source parameter as it changes for each peripheral. 155 * 156 * Warning: This function is only for use pre-relocation. Please use 157 * clock_start_periph_pll() instead. 158 * 159 * @param periph_id peripheral to adjust 160 * @param source source clock (0, 1, 2 or 3) 161 */ 162 void clock_ll_set_source(enum periph_id periph_id, unsigned source); 163 164 /** 165 * This function is similar to clock_ll_set_source() except that it can be 166 * used for clocks with more than 2 mux bits. 167 * 168 * @param periph_id peripheral to adjust 169 * @param mux_bits number of mux bits for the clock 170 * @param source source clock (0-15 depending on mux_bits) 171 */ 172 int clock_ll_set_source_bits(enum periph_id periph_id, int mux_bits, 173 unsigned source); 174 175 /** 176 * Set the source and divisor for a peripheral clock. This sets the 177 * clock rate. You need to look up the datasheet to see the meaning of the 178 * source parameter as it changes for each peripheral. 179 * 180 * Warning: This function is only for use pre-relocation. Please use 181 * clock_start_periph_pll() instead. 182 * 183 * @param periph_id peripheral to adjust 184 * @param source source clock (0, 1, 2 or 3) 185 * @param divisor divisor value to use 186 */ 187 void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source, 188 unsigned divisor); 189 190 /** 191 * Returns the current parent clock ID of a given peripheral. This can be 192 * useful in order to call clock_*_periph_*() from generic code that has no 193 * specific knowledge of system-level clock tree structure. 194 * 195 * @param periph_id peripheral to query 196 * @return clock ID of the peripheral's current parent clock 197 */ 198 enum clock_id clock_get_periph_parent(enum periph_id periph_id); 199 200 /** 201 * Start a peripheral PLL clock at the given rate. This also resets the 202 * peripheral. 203 * 204 * @param periph_id peripheral to start 205 * @param parent PLL id of required parent clock 206 * @param rate Required clock rate in Hz 207 * @return rate selected in Hz, or -1U if something went wrong 208 */ 209 unsigned clock_start_periph_pll(enum periph_id periph_id, 210 enum clock_id parent, unsigned rate); 211 212 /** 213 * Returns the rate of a peripheral clock in Hz. Since the caller almost 214 * certainly knows the parent clock (having just set it) we require that 215 * this be passed in so we don't need to work it out. 216 * 217 * @param periph_id peripheral to start 218 * @param parent PLL id of parent clock (used to calculate rate, you 219 * must know this!) 220 * @return clock rate of peripheral in Hz 221 */ 222 unsigned long clock_get_periph_rate(enum periph_id periph_id, 223 enum clock_id parent); 224 225 /** 226 * Adjust peripheral PLL clock to the given rate. This does not reset the 227 * peripheral. If a second stage divisor is not available, pass NULL for 228 * extra_div. If it is available, then this parameter will return the 229 * divisor selected (which will be a power of 2 from 1 to 256). 230 * 231 * @param periph_id peripheral to start 232 * @param parent PLL id of required parent clock 233 * @param rate Required clock rate in Hz 234 * @param extra_div value for the second-stage divisor (NULL if one is 235 not available) 236 * @return rate selected in Hz, or -1U if something went wrong 237 */ 238 unsigned clock_adjust_periph_pll_div(enum periph_id periph_id, 239 enum clock_id parent, unsigned rate, int *extra_div); 240 241 /** 242 * Returns the clock rate of a specified clock, in Hz. 243 * 244 * @param parent PLL id of clock to check 245 * @return rate of clock in Hz 246 */ 247 unsigned clock_get_rate(enum clock_id clkid); 248 249 /** 250 * Start up a UART using low-level calls 251 * 252 * Prior to relocation clock_start_periph_pll() cannot be called. This 253 * function provides a way to set up a UART using low-level calls which 254 * do not require BSS. 255 * 256 * @param periph_id Peripheral ID of UART to enable (e,g, PERIPH_ID_UART1) 257 */ 258 void clock_ll_start_uart(enum periph_id periph_id); 259 260 /** 261 * Decode a peripheral ID from a device tree node. 262 * 263 * This works by looking up the peripheral's 'clocks' node and reading out 264 * the second cell, which is the clock number / peripheral ID. 265 * 266 * @param blob FDT blob to use 267 * @param node Node to look at 268 * @return peripheral ID, or PERIPH_ID_NONE if none 269 */ 270 int clock_decode_periph_id(struct udevice *dev); 271 272 /** 273 * Checks if the oscillator bypass is enabled (XOBP bit) 274 * 275 * @return 1 if bypass is enabled, 0 if not 276 */ 277 int clock_get_osc_bypass(void); 278 279 /* 280 * Checks that clocks are valid and prints a warning if not 281 * 282 * @return 0 if ok, -1 on error 283 */ 284 int clock_verify(void); 285 286 /* Initialize the clocks */ 287 void clock_init(void); 288 289 /* Initialize the PLLs */ 290 void clock_early_init(void); 291 292 /* @return true if hardware indicates that clock_early_init() was called */ 293 bool clock_early_init_done(void); 294 295 /* Returns a pointer to the clock source register for a peripheral */ 296 u32 *get_periph_source_reg(enum periph_id periph_id); 297 298 /* Returns a pointer to the given 'simple' PLL */ 299 struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid); 300 301 /* 302 * Given a peripheral ID, determine where the mux bits are in the peripheral 303 * clock's register, the number of divider bits the clock has, and the SoC- 304 * specific clock type. 305 * 306 * This is an internal API between the core Tegra clock code and the SoC- 307 * specific clock code. 308 * 309 * @param periph_id peripheral to query 310 * @param mux_bits Set to number of bits in mux register 311 * @param divider_bits Set to the relevant MASK_BITS_* value 312 * @param type Set to the SoC-specific clock type 313 * @return 0 on success, -1 on error 314 */ 315 int get_periph_clock_info(enum periph_id periph_id, int *mux_bits, 316 int *divider_bits, int *type); 317 318 /* 319 * Given a peripheral ID and clock source mux value, determine the clock_id 320 * of that peripheral's parent. 321 * 322 * This is an internal API between the core Tegra clock code and the SoC- 323 * specific clock code. 324 * 325 * @param periph_id peripheral to query 326 * @param source raw clock source mux value 327 * @return the CLOCK_ID_* value @source represents 328 */ 329 enum clock_id get_periph_clock_id(enum periph_id periph_id, int source); 330 331 /** 332 * Given a peripheral ID and the required source clock, this returns which 333 * value should be programmed into the source mux for that peripheral. 334 * 335 * There is special code here to handle the one source type with 5 sources. 336 * 337 * @param periph_id peripheral to start 338 * @param source PLL id of required parent clock 339 * @param mux_bits Set to number of bits in mux register: 2 or 4 340 * @param divider_bits Set to number of divider bits (8 or 16) 341 * @return mux value (0-4, or -1 if not found) 342 */ 343 int get_periph_clock_source(enum periph_id periph_id, 344 enum clock_id parent, int *mux_bits, int *divider_bits); 345 346 /* 347 * Convert a device tree clock ID to our peripheral ID. They are mostly 348 * the same but we are very cautious so we check that a valid clock ID is 349 * provided. 350 * 351 * @param clk_id Clock ID according to tegra30 device tree binding 352 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid 353 */ 354 enum periph_id clk_id_to_periph_id(int clk_id); 355 356 /** 357 * Set the output frequency you want for each PLL clock. 358 * PLL output frequencies are programmed by setting their N, M and P values. 359 * The governing equations are: 360 * VCO = (Fi / m) * n, Fo = VCO / (2^p) 361 * where Fo is the output frequency from the PLL. 362 * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi) 363 * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1 364 * Please see Tegra TRM section 5.3 to get the detail for PLL Programming 365 * 366 * @param n PLL feedback divider(DIVN) 367 * @param m PLL input divider(DIVN) 368 * @param p post divider(DIVP) 369 * @param cpcon base PLL charge pump(CPCON) 370 * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot 371 * be overridden), 1 if PLL is already correct 372 */ 373 int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon); 374 375 /* return 1 if a peripheral ID is in range */ 376 #define clock_type_id_isvalid(id) ((id) >= 0 && \ 377 (id) < CLOCK_TYPE_COUNT) 378 379 /* return 1 if a periphc_internal_id is in range */ 380 #define periphc_internal_id_isvalid(id) ((id) >= 0 && \ 381 (id) < PERIPHC_COUNT) 382 383 /* SoC-specific TSC init */ 384 void arch_timer_init(void); 385 386 void tegra30_set_up_pllp(void); 387 388 /* Number of PLL-based clocks (i.e. not OSC, MCLK or 32KHz) */ 389 #define CLOCK_ID_PLL_COUNT (CLOCK_ID_COUNT - 3) 390 391 struct clk_pll_info { 392 u32 m_shift:5; /* DIVM_SHIFT */ 393 u32 n_shift:5; /* DIVN_SHIFT */ 394 u32 p_shift:5; /* DIVP_SHIFT */ 395 u32 kcp_shift:5; /* KCP/cpcon SHIFT */ 396 u32 kvco_shift:5; /* KVCO/lfcon SHIFT */ 397 u32 lock_ena:6; /* LOCK_ENABLE/EN_LOCKDET shift */ 398 u32 rsvd:1; 399 u32 m_mask:10; /* DIVM_MASK */ 400 u32 n_mask:12; /* DIVN_MASK */ 401 u32 p_mask:10; /* DIVP_MASK or VCO_MASK */ 402 u32 kcp_mask:10; /* KCP/CPCON MASK */ 403 u32 kvco_mask:10; /* KVCO/LFCON MASK */ 404 u32 lock_det:6; /* LOCK_DETECT/LOCKED shift */ 405 u32 rsvd2:6; 406 }; 407 extern struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT]; 408 409 struct periph_clk_init { 410 enum periph_id periph_id; 411 enum clock_id parent_clock_id; 412 }; 413 extern struct periph_clk_init periph_clk_init_table[]; 414 415 /** 416 * Enable output clock for external peripherals 417 * 418 * @param clk_id Clock ID to output (1, 2 or 3) 419 * @return 0 if OK. -ve on error 420 */ 421 int clock_external_output(int clk_id); 422 423 #endif /* _TEGRA_CLOCK_H_ */ 424