1/* SPDX-License-Identifier: GPL-2.0 */ 2/dts-v1/; 3 4#include <dt-bindings/gpio/gpio.h> 5#include <dt-bindings/gpio/x86-gpio.h> 6 7/include/ "skeleton.dtsi" 8/include/ "keyboard.dtsi" 9/include/ "reset.dtsi" 10/include/ "rtc.dtsi" 11/include/ "tsc_timer.dtsi" 12 13#ifdef CONFIG_CHROMEOS_VBOOT 14#include "chromeos-x86.dtsi" 15#include "flashmap-x86-ro.dtsi" 16#include "flashmap-16mb-rw.dtsi" 17#endif 18 19#include <dt-bindings/clock/intel-clock.h> 20#include <dt-bindings/interrupt-controller/irq.h> 21#include <dt-bindings/interrupt-controller/x86-irq.h> 22#include <asm/e820.h> 23#include <asm/intel_pinctrl_defs.h> 24#include <asm/arch-apollolake/cpu.h> 25#include <asm/arch-apollolake/gpe.h> 26#include <asm/arch-apollolake/gpio.h> 27#include <asm/arch-apollolake/iomap.h> 28#include <asm/arch-apollolake/pm.h> 29#include <dt-bindings/clock/intel-clock.h> 30#include <asm/arch-apollolake/fsp/fsp_m_upd.h> 31#include <asm/arch-apollolake/fsp/fsp_s_upd.h> 32#include <dt-bindings/sound/nhlt.h> 33 34/ { 35 model = "Google Coral"; 36 compatible = "google,coral", "intel,apollolake"; 37 38 aliases { 39 cros-ec0 = &cros_ec; 40 fsp = &fsp_s; 41 spi0 = &spi; 42 i2c0 = &i2c_0; 43 i2c1 = &i2c_1; 44 i2c2 = &i2c_2; 45 i2c3 = &i2c_3; 46 i2c4 = &i2c_4; 47 i2c5 = &i2c_5; 48 i2c6 = &i2c_6; 49 i2c7 = &i2c_7; 50 mmc0 = &emmc; 51 mmc1 = &sdmmc; 52 }; 53 54 board: board { 55 compatible = "google,coral"; 56 recovery-gpios = <&gpio_nw (-1) GPIO_ACTIVE_LOW>; 57 write-protect-gpios = <&gpio_nw GPIO_75 GPIO_ACTIVE_HIGH>; 58 phase-enforce-gpios = <&gpio_n GPIO_10 GPIO_ACTIVE_HIGH>; 59 memconfig-gpios = <&gpio_nw GPIO_101 GPIO_ACTIVE_HIGH 60 &gpio_nw GPIO_102 GPIO_ACTIVE_HIGH 61 &gpio_n GPIO_38 GPIO_ACTIVE_HIGH 62 &gpio_n GPIO_45 GPIO_ACTIVE_HIGH>; 63 64 /* 65 * This is used for reef only: 66 * 67 * skuconfig-gpios = <&gpio_nw GPIO_16 GPIO_ACTIVE_HIGH 68 * &gpio_nw GPIO_17 GPIO_ACTIVE_HIGH>; 69 */ 70 smbios { 71 /* Type 1 table */ 72 system { 73 manufacturer = "Google"; 74 product = "Coral"; 75 version = "rev2"; 76 serial = "123456789"; 77 sku = "sku3"; 78 family = "Google_Coral"; 79 }; 80 81 /* Type 2 table */ 82 baseboard { 83 manufacturer = "Google"; 84 product = "Coral"; 85 asset-tag = "ABC123"; 86 }; 87 88 /* Type 3 table */ 89 chassis { 90 manufacturer = "Google"; 91 }; 92 }; 93 }; 94 95 config { 96 silent_console = <0>; 97 }; 98 99 chosen { 100 stdout-path = &serial; 101 e820-entries = /bits/ 64 < 102 IOMAP_P2SB_BAR IOMAP_P2SB_SIZE E820_RESERVED 103 MCH_BASE_ADDRESS MCH_SIZE E820_RESERVED>; 104 u-boot,acpi-ssdt-order = <&cpu_0 &cpu_1 &cpu_2 &cpu_3 105 &i2c_0 &i2c_1 &i2c_2 &i2c_3 &i2c_4 &i2c_5 106 &sdmmc &maxim_codec &wifi &da_codec &tpm 107 &elan_touchscreen &raydium_touchscreen 108 &elan_touchpad &synaptics_touchpad &wacom_digitizer>; 109 u-boot,acpi-dsdt-order = <&board &lpc>; 110 }; 111 112 clk: clock { 113 compatible = "intel,apl-clk"; 114 #clock-cells = <1>; 115 u-boot,dm-pre-proper; 116 }; 117 118 cpus { 119 u-boot,dm-pre-proper; 120 #address-cells = <1>; 121 #size-cells = <0>; 122 123 cpu_0: cpu@0 { 124 u-boot,dm-pre-proper; 125 u-boot,dm-spl; 126 device_type = "cpu"; 127 compatible = "intel,apl-cpu"; 128 reg = <0>; 129 intel,apic-id = <0>; 130 }; 131 132 cpu_1: cpu@1 { 133 device_type = "cpu"; 134 compatible = "intel,apl-cpu"; 135 reg = <1>; 136 intel,apic-id = <2>; 137 }; 138 139 cpu_2: cpu@2 { 140 device_type = "cpu"; 141 compatible = "intel,apl-cpu"; 142 reg = <2>; 143 intel,apic-id = <4>; 144 }; 145 146 cpu_3: cpu@3 { 147 device_type = "cpu"; 148 compatible = "intel,apl-cpu"; 149 reg = <3>; 150 intel,apic-id = <6>; 151 }; 152 153 }; 154 155 acpi_gpe: general-purpose-events { 156 u-boot,dm-pre-proper; 157 reg = <IOMAP_ACPI_BASE IOMAP_ACPI_SIZE>; 158 compatible = "intel,acpi-gpe"; 159 interrupt-controller; 160 #interrupt-cells = <2>; 161 }; 162 163 coreboot-video { 164 /* This will only activate when booted from coreboot */ 165 compatible = "coreboot-fb"; 166 }; 167 168 keyboard { 169 intel,duplicate-por; 170 }; 171 172 pci { 173 compatible = "pci-x86"; 174 #address-cells = <3>; 175 #size-cells = <2>; 176 u-boot,dm-pre-reloc; 177 ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000 178 0x42000000 0x0 0xb0000000 0xb0000000 0 0x10000000 179 0x01000000 0x0 0x1000 0x1000 0 0xefff>; 180 u-boot,skip-auto-config-until-reloc; 181 182 host_bridge: host-bridge@0,0 { 183 u-boot,dm-pre-reloc; 184 reg = <0x00000000 0 0 0 0>; 185 compatible = "intel,apl-hostbridge"; 186 pciex-region-size = <0x10000000>; 187 fspm,training-delay = <21>; 188 /* 189 * Parameters used by the FSP-S binary blob. This is 190 * really unfortunate since these parameters mostly 191 * relate to drivers but we need them in one place. We 192 * could put them in the driver nodes easily, but then 193 * would have to scan each node to find them. So just 194 * dump them here for now. 195 */ 196 fsp_s: fsp-s { 197 }; 198 fsp_m: fsp-m { 199 u-boot,dm-spl; 200 }; 201 202 nhlt { 203 intel,dmic-channels = <4>; 204 }; 205 }; 206 207 punit@0,1 { 208 u-boot,dm-pre-proper; 209 u-boot,dm-spl; 210 reg = <0x00000800 0 0 0 0>; 211 compatible = "intel,apl-punit"; 212 }; 213 214 gma@2,0 { 215 u-boot,dm-pre-proper; 216 reg = <0x00001000 0 0 0 0>; 217 compatible = "fsp-fb"; 218 }; 219 220 p2sb: p2sb@d,0 { 221 u-boot,dm-pre-reloc; 222 reg = <0x02006810 0 0 0 0>; 223 compatible = "intel,p2sb"; 224 early-regs = <IOMAP_P2SB_BAR 0x100000>; 225 pci,no-autoconfig; 226 227 n { 228 compatible = "intel,apl-pinctrl"; 229 u-boot,dm-pre-reloc; 230 intel,p2sb-port-id = <PID_GPIO_N>; 231 acpi,path = "\\_SB.GPO0"; 232 gpio_n: gpio-n { 233 compatible = "intel,gpio"; 234 u-boot,dm-pre-reloc; 235 gpio-controller; 236 #gpio-cells = <2>; 237 linux-name = "INT3452:00"; 238 }; 239 }; 240 241 nw { 242 u-boot,dm-pre-reloc; 243 compatible = "intel,apl-pinctrl"; 244 intel,p2sb-port-id = <PID_GPIO_NW>; 245 #gpio-cells = <2>; 246 acpi,path = "\\_SB.GPO1"; 247 gpio_nw: gpio-nw { 248 compatible = "intel,gpio"; 249 u-boot,dm-pre-reloc; 250 gpio-controller; 251 #gpio-cells = <2>; 252 linux-name = "INT3452:01"; 253 }; 254 }; 255 256 w { 257 u-boot,dm-pre-reloc; 258 compatible = "intel,apl-pinctrl"; 259 intel,p2sb-port-id = <PID_GPIO_W>; 260 #gpio-cells = <2>; 261 acpi,path = "\\_SB.GPO2"; 262 gpio_w: gpio-w { 263 compatible = "intel,gpio"; 264 u-boot,dm-pre-reloc; 265 gpio-controller; 266 #gpio-cells = <2>; 267 linux-name = "INT3452:02"; 268 }; 269 }; 270 271 sw { 272 u-boot,dm-pre-reloc; 273 compatible = "intel,apl-pinctrl"; 274 intel,p2sb-port-id = <PID_GPIO_SW>; 275 #gpio-cells = <2>; 276 acpi,path = "\\_SB.GPO3"; 277 gpio_sw: gpio-sw { 278 compatible = "intel,gpio"; 279 u-boot,dm-pre-reloc; 280 gpio-controller; 281 #gpio-cells = <2>; 282 linux-name = "INT3452:03"; 283 }; 284 }; 285 286 itss { 287 u-boot,dm-pre-reloc; 288 compatible = "intel,itss"; 289 intel,p2sb-port-id = <PID_ITSS>; 290 intel,pmc-routes = < 291 PMC_GPE_SW_31_0 GPIO_GPE_SW_31_0 292 PMC_GPE_SW_63_32 GPIO_GPE_SW_63_32 293 PMC_GPE_NW_31_0 GPIO_GPE_NW_31_0 294 PMC_GPE_NW_63_32 GPIO_GPE_NW_63_32 295 PMC_GPE_NW_95_64 GPIO_GPE_NW_95_64 296 PMC_GPE_N_31_0 GPIO_GPE_N_31_0 297 PMC_GPE_N_63_32 GPIO_GPE_N_63_32 298 PMC_GPE_W_31_0 GPIO_GPE_W_31_0>; 299 }; 300 }; 301 302 pmc@d,1 { 303 u-boot,dm-pre-reloc; 304 reg = <0x6900 0 0 0 0>; 305 306 /* 307 * Values for BAR0, BAR2 and ACPI_BASE for when PCI 308 * auto-configure is not available 309 */ 310 early-regs = <0xfe042000 0x2000 311 0xfe044000 0x2000 312 IOMAP_ACPI_BASE IOMAP_ACPI_SIZE>; 313 compatible = "intel,apl-pmc"; 314 gpe0-dwx-mask = <0xf>; 315 gpe0-dwx-shift-base = <4>; 316 317 /* 318 * GPE configuration 319 * Note that GPE events called out in ASL code rely on 320 * this route, i.e., if this route changes then the 321 * affected GPE * offset bits also need to be changed. 322 * This sets the PMC register GPE_CFG fields. 323 */ 324 gpe0-dw = <PMC_GPE_N_31_0 325 PMC_GPE_N_63_32 326 PMC_GPE_SW_31_0>; 327 gpe0-sts = <0x20>; 328 gpe0-en = <0x30>; 329 }; 330 331 audio@e,0 { 332 reg = <0x7000 0 0 0 0>; 333 compatible = "simple-bus"; 334 acpi,name = "HDAS"; 335 i2s { 336 compatible = "fred"; 337 }; 338 maxim_codec: maxim-codec { 339 compatible = "maxim,max98357a"; 340 acpi,ddn = "Maxim Integrated 98357A Amplifier"; 341 sdmode-gpios = <&gpio_n GPIO_76 GPIO_ACTIVE_HIGH>; 342 sdmode-delay = <5>; 343 acpi,name = "MAXM"; 344 acpi,hid = "MX98357A"; 345 acpi,audio-link = <AUDIO_LINK_SSP5>; 346 }; 347 }; 348 349 spi: fast-spi@d,2 { 350 u-boot,dm-pre-proper; 351 u-boot,dm-spl; 352 reg = <0x02006a10 0 0 0 0>; 353 #address-cells = <1>; 354 #size-cells = <0>; 355 compatible = "intel,fast-spi"; 356 early-regs = <IOMAP_SPI_BASE 0x1000>; 357 intel,hardware-seq = <1>; 358 359 fwstore_spi: spi-flash@0 { 360 #size-cells = <1>; 361 #address-cells = <1>; 362 u-boot,dm-pre-proper; 363 u-boot,dm-spl; 364 reg = <0>; 365 compatible = "winbond,w25q128fw", 366 "jedec,spi-nor"; 367 rw-mrc-cache { 368 label = "rw-mrc-cache"; 369 reg = <0x008e0000 0x00010000>; 370 u-boot,dm-pre-reloc; 371 }; 372 rw-var-mrc-cache { 373 label = "rw-mrc-cache"; 374 reg = <0x008f0000 0x0001000>; 375 u-boot,dm-pre-reloc; 376 }; 377 }; 378 }; 379 380 /* WiFi */ 381 pcie-a0@14,0 { 382 reg = <0x0000a000 0 0 0 0>; 383 acpi,name = "RP01"; 384 wifi: wifi { 385 compatible = "intel,generic-wifi"; 386 acpi,ddn = "Intel WiFi"; 387 acpi,name = "WF00"; 388 acpi,wake = <GPE0_DW3_00>; 389 interrupts-extended = <&acpi_gpe 0x3c 0>; 390 }; 391 }; 392 393 i2c_0: i2c2@16,0 { 394 compatible = "intel,apl-i2c"; 395 reg = <0x0200b010 0 0 0 0>; 396 clocks = <&clk CLK_I2C>; 397 i2c-scl-rising-time-ns = <104>; 398 i2c-scl-falling-time-ns = <52>; 399 clock-frequency = <400000>; 400 i2c,speeds = <100000 400000 1000000>; 401 #address-cells = <1>; 402 #size-cells = <0>; 403 da_codec: da-codec { 404 reg = <0x1a>; 405 compatible = "dlg,da7219"; 406 interrupts-extended = <&acpi_gpe GPIO_116_IRQ 407 (IRQ_TYPE_LEVEL_LOW | X86_IRQ_TYPE_SHARED)>; 408 acpi,name = "DLG7"; 409 acpi,ddn = "Dialog Semiconductor DA7219 Audio Codec"; 410 acpi,audio-link = <AUDIO_LINK_SSP1>; 411 dlg,micbias-lvl = <2600>; 412 dlg,mic-amp-in-sel = "diff"; 413 da7219_aad { 414 dlg,btn-cfg = <50>; 415 dlg,mic-det-thr = <500>; 416 dlg,jack-ins-deb = <20>; 417 dlg,jack-det-rate = "32ms_64ms"; 418 dlg,jack-rem-deb = <1>; 419 dlg,a-d-btn-thr = <0xa>; 420 dlg,d-b-btn-thr = <0x16>; 421 dlg,b-c-btn-thr = <0x21>; 422 dlg,c-mic-btn-thr = <0x3e>; 423 dlg,btn-avg = <4>; 424 dlg,adc-1bit-rpt = <1>; 425 }; 426 }; 427 }; 428 429 i2c_1: i2c2@16,1 { 430 compatible = "intel,apl-i2c"; 431 reg = <0x0200b110 0 0 0 0>; 432 clocks = <&clk CLK_I2C>; 433 clock-frequency = <400000>; 434 i2c,speeds = <100000 400000 1000000 3400000>; 435 i2c-scl-rising-time-ns = <52>; 436 i2c-scl-falling-time-ns = <52>; 437 }; 438 439 i2c_2: i2c2@16,2 { 440 compatible = "intel,apl-i2c", "snps,designware-i2c-pci"; 441 reg = <0x0200b210 0 0 0 0>; 442 early-regs = <IOMAP_I2C2_BASE 0x1000>; 443 u-boot,dm-pre-proper; 444 #address-cells = <1>; 445 #size-cells = <0>; 446 clock-frequency = <400000>; 447 i2c,speeds = <100000 400000 1000000>; 448 clocks = <&clk CLK_I2C>; 449 i2c-scl-rising-time-ns = <57>; 450 i2c-scl-falling-time-ns = <28>; 451 tpm: tpm@50 { 452 reg = <0x50>; 453 compatible = "google,cr50"; 454 u-boot,dm-pre-proper; 455 u-boot,i2c-offset-len = <0>; 456 ready-gpios = <&gpio_n 28 GPIO_ACTIVE_LOW>; 457 interrupts-extended = <&acpi_gpe GPIO_28_IRQ 458 IRQ_TYPE_EDGE_FALLING>; 459 acpi,hid = "GOOG0005"; 460 acpi,ddn = "I2C TPM"; 461 acpi,name = "TPMI"; 462 }; 463 }; 464 465 i2c_3: i2c2@16,3 { 466 compatible = "intel,apl-i2c"; 467 reg = <0x0200b310 0 0 0 0>; 468 #address-cells = <1>; 469 #size-cells = <0>; 470 clocks = <&clk CLK_I2C>; 471 i2c-scl-rising-time-ns = <76>; 472 i2c-scl-falling-time-ns = <164>; 473 clock-frequency = <400000>; 474 i2c,speeds = <100000 400000>; 475 elan_touchscreen: elan-touchscreen@10 { 476 compatible = "i2c-chip"; 477 reg = <0x10>; 478 acpi,hid = "ELAN0001"; 479 acpi,ddn = "ELAN Touchscreen"; 480 interrupts-extended = <&acpi_gpe GPIO_21_IRQ 481 IRQ_TYPE_EDGE_FALLING>; 482 linux,probed; 483 reset-gpios = <&gpio_n GPIO_36 GPIO_ACTIVE_HIGH>; 484 reset-delay-ms = <20>; 485 enable-gpios = <&gpio_n GPIO_152 GPIO_ACTIVE_HIGH>; 486 enable-delay-ms = <1>; 487 acpi,has-power-resource; 488 }; 489 490 raydium_touchscreen: raydium-touchscreen@39 { 491 compatible = "i2c-chip"; 492 reg = <0x39>; 493 acpi,hid = "RAYD0001"; 494 acpi,ddn = "Raydium Touchscreen"; 495 interrupts-extended = <&acpi_gpe GPIO_21_IRQ 496 IRQ_TYPE_EDGE_FALLING>; 497 linux,probed; 498 reset-gpios = <&gpio_n GPIO_36 GPIO_ACTIVE_HIGH>; 499 reset-delay-ms = <1>; 500 enable-gpios = <&gpio_n GPIO_152 GPIO_ACTIVE_HIGH>; 501 enable-delay-ms = <50>; 502 acpi,has-power-resource; 503 }; 504 }; 505 506 i2c_4: i2c2@17,0 { 507 compatible = "intel,apl-i2c"; 508 reg = <0x0200b810 0 0 0 0>; 509 #address-cells = <1>; 510 #size-cells = <0>; 511 clocks = <&clk CLK_I2C>; 512 i2c-sda-hold-time-ns = <350>; 513 i2c-scl-rising-time-ns = <114>; 514 i2c-scl-falling-time-ns = <164>; 515 clock-frequency = <400000>; 516 i2c,speeds = <100000 400000>; 517 elan_touchpad: elan-touchpad@15 { 518 compatible = "i2c-chip"; 519 reg = <0x15>; 520 u-boot,i2c-offset-len = <0>; 521 acpi,hid = "ELAN0000"; 522 acpi,ddn = "ELAN Touchpad"; 523 interrupts-extended = <&acpi_gpe GPIO_18_IRQ 524 IRQ_TYPE_EDGE_FALLING>; 525 acpi,wake = <GPE0_DW1_15>; 526 linux,probed; 527 }; 528 synaptics_touchpad: synaptics-touchpad@2c { 529 compatible = "hid-over-i2c"; 530 reg = <0x2c>; 531 acpi,hid = "PNP0C50"; 532 acpi,ddn = "Synaptics Touchpad"; 533 interrupts-extended = <&acpi_gpe GPIO_18_IRQ 534 IRQ_TYPE_EDGE_FALLING>; 535 acpi,wake = <GPE0_DW1_15>; 536 linux,probed; 537 hid-descr-addr = <0x20>; 538 }; 539 }; 540 541 i2c_5: i2c2@17,1 { 542 compatible = "intel,apl-i2c"; 543 reg = <0x0200b910 0 0 0 0>; 544 #address-cells = <1>; 545 #size-cells = <0>; 546 clocks = <&clk CLK_I2C>; 547 i2c-scl-rising-time-ns = <76>; 548 i2c-scl-falling-time-ns = <164>; 549 clock-frequency = <400000>; 550 i2c,speeds = <100000 400000 1000000>; 551 wacom_digitizer: wacom-digitizer@9 { 552 compatible = "hid-over-i2c"; 553 reg = <0x9>; 554 acpi,hid = "WCOM50C1"; 555 acpi,ddn = "WCOM Digitizer"; 556 interrupts-extended = <&acpi_gpe GPIO_13_IRQ 557 (IRQ_TYPE_LEVEL_LOW | X86_IRQ_TYPE_SHARED)>; 558 hid-descr-addr = <0x1>; 559 }; 560 }; 561 562 i2c_6: i2c2@17,2 { 563 compatible = "intel,apl-i2c"; 564 reg = <0x0200ba10 0 0 0 0>; 565 clocks = <&clk CLK_I2C>; 566 status = "disabled"; 567 }; 568 569 i2c_7: i2c2@17,3 { 570 compatible = "intel,apl-i2c"; 571 reg = <0x0200bb10 0 0 0 0>; 572 clocks = <&clk CLK_I2C>; 573 status = "disabled"; 574 }; 575 576 serial: serial@18,2 { 577 reg = <0x0200c210 0 0 0 0>; 578 u-boot,dm-pre-reloc; 579 compatible = "intel,apl-ns16550"; 580 early-regs = <0xde000000 0x20>; 581 reg-shift = <2>; 582 clock-frequency = <1843200>; 583 current-speed = <115200>; 584 acpi,name = "URT3"; 585 pci,no-autoconfig; 586 }; 587 588 sdmmc: sdmmc@1b,0 { 589 reg = <0x0000d800 0 0 0 0>; 590 compatible = "intel,apl-sd"; 591 cd-gpios = <&gpio_sw GPIO_177 GPIO_ACTIVE_LOW>; 592 acpi,name = "SDCD"; 593 }; 594 595 emmc: emmc@1c,0 { 596 reg = <0x0000e000 0 0 0 0>; 597 compatible = "intel,apl-emmc"; 598 non-removable; 599 }; 600 601 pch: pch@1f,0 { 602 reg = <0x0000f800 0 0 0 0>; 603 compatible = "intel,apl-pch"; 604 u-boot,dm-pre-reloc; 605 #address-cells = <1>; 606 #size-cells = <1>; 607 608 lpc: lpc { 609 compatible = "intel,apl-lpc"; 610 #address-cells = <1>; 611 #size-cells = <0>; 612 u-boot,dm-pre-reloc; 613 cros_ec: cros-ec { 614 u-boot,dm-pre-proper; 615 u-boot,dm-vpl; 616 compatible = "google,cros-ec-lpc"; 617 reg = <0x204 1 0x200 1 0x880 0x80>; 618 619 /* 620 * Describes the flash memory within 621 * the EC 622 */ 623 #address-cells = <1>; 624 #size-cells = <1>; 625 flash@8000000 { 626 reg = <0x08000000 0x20000>; 627 erase-value = <0xff>; 628 }; 629 }; 630 }; 631 }; 632 }; 633 634}; 635 636&host_bridge { 637 /* 638 * PL1 override 12000 mW: the energy calculation is wrong with the 639 * current VR solution. Experiments show that SoC TDP max (6W) can be 640 * reached when RAPL PL1 is set to 12W. Set RAPL PL2 to 15W. 641 */ 642 tdp-pl-override-mw = <12000 15000>; 643 644 early-pads = < 645 /* These two are for the debug UART */ 646 GPIO_46 /* UART2 RX */ 647 (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP) 648 (PAD_CFG1_PULL_NATIVE | PAD_CFG1_IOSSTATE_TX_LAST_RXE) 649 650 GPIO_47 /* UART2 TX */ 651 (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP) 652 (PAD_CFG1_PULL_NATIVE | PAD_CFG1_IOSSTATE_TX_LAST_RXE) 653 654 GPIO_75 /* I2S1_BCLK -- PCH_WP */ 655 (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP) 656 (PAD_CFG1_PULL_UP_20K | PAD_CFG1_IOSSTATE_TXD_RXE) 657 658 /* I2C2 - TPM */ 659 GPIO_128 /* LPSS_I2C2_SDA */ 660 (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP) 661 (PAD_CFG1_PULL_UP_2K | PAD_CFG1_IOSSTATE_TX_LAST_RXE) 662 GPIO_129 /* LPSS_I2C2_SCL */ 663 (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP) 664 (PAD_CFG1_PULL_UP_2K | PAD_CFG1_IOSSTATE_TX_LAST_RXE) 665 GPIO_28 /* TPM IRQ */ 666 (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP | 667 PAD_CFG0_TX_DISABLE | PAD_CFG0_ROUTE_IOAPIC | 668 PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_INVERT) 669 (PAD_CFG1_PULL_NONE | PAD_CFG1_IOSSTATE_TXD_RXE) 670 PAD_CFG_GPI(GPIO_25, UP_20K, DEEP) /* unused */ 671 672 /* 673 * WLAN_PE_RST - default to deasserted just in case FSP 674 * misbehaves 675 */ 676 GPIO_122 /* SIO_SPI_2_RXD */ 677 (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP | 678 PAD_CFG0_RX_DISABLE | 0) 679 (PAD_CFG1_PULL_NONE | PAD_CFG1_IOSSTATE_TX_LAST_RXE) 680 681 /* LPC */ 682 PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1) /* LPC_SERIRQ */ 683 PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1) /* LPC_CLKOUT0 */ 684 PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1) 685 PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1) /* LPC_AD0 */ 686 PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1) /* LPC_AD1 */ 687 PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1) /* LPC_AD2 */ 688 PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1) /* LPC_AD3 */ 689 PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1) /* LPC_CLKRUN_N */ 690 PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */ 691 692 PAD_CFG_GPI(GPIO_101, NONE, DEEP) /* FST_IO2 -- MEM_CONFIG0 */ 693 PAD_CFG_GPI(GPIO_102, NONE, DEEP) /* FST_IO3 -- MEM_CONFIG1 */ 694 PAD_CFG_GPI(GPIO_38, NONE, DEEP) /* LPSS_UART0_RXD - MEM_CONFIG2*/ 695 PAD_CFG_GPI(GPIO_45, NONE, DEEP) /* LPSS_UART1_CTS - MEM_CONFIG3 */ 696 >; 697}; 698 699&fsp_m { 700 fspm,package = <PACKAGE_BGA>; 701 fspm,profile = <PROFILE_LPDDR4_2400_24_22_22>; 702 fspm,memory-down = <MEMORY_DOWN_YES>; 703 fspm,scrambler-support = <1>; 704 fspm,interleaved-mode = <INTERLEAVED_MODE_ENABLE>; 705 fspm,channel-hash-mask = <0x36>; 706 fspm,slice-hash-mask = <0x9>; 707 fspm,dual-rank-support-enable = <1>; 708 fspm,low-memory-max-value = <2048>; 709 fspm,ch0-rank-enable = <1>; 710 fspm,ch0-device-width = <CHX_DEVICE_WIDTH_X16>; 711 fspm,ch0-dram-density = <CHX_DEVICE_DENSITY_8GB>; 712 fspm,ch0-option = <(CHX_OPTION_RANK_INTERLEAVING | 713 CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>; 714 fspm,ch0-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>; 715 fspm,ch1-rank-enable = <1>; 716 fspm,ch1-device-width = <CHX_DEVICE_WIDTH_X16>; 717 fspm,ch1-dram-density = <CHX_DEVICE_DENSITY_8GB>; 718 fspm,ch1-option = <(CHX_OPTION_RANK_INTERLEAVING | 719 CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>; 720 fspm,ch1-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>; 721 fspm,ch2-rank-enable = <1>; 722 fspm,ch2-device-width = <CHX_DEVICE_WIDTH_X16>; 723 fspm,ch2-dram-density = <CHX_DEVICE_DENSITY_8GB>; 724 fspm,ch2-option = <(CHX_OPTION_RANK_INTERLEAVING | 725 CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>; 726 fspm,ch2-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>; 727 fspm,ch3-rank-enable = <1>; 728 fspm,ch3-device-width = <CHX_DEVICE_WIDTH_X16>; 729 fspm,ch3-dram-density = <CHX_DEVICE_DENSITY_8GB>; 730 fspm,ch3-option = <(CHX_OPTION_RANK_INTERLEAVING | 731 CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>; 732 fspm,ch3-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>; 733 fspm,fspm,skip-cse-rbp = <1>; 734 735 fspm,ch-bit-swizzling = /bits/ 8 < 736 /* LP4_PHYS_CH0A */ 737 738 /* DQA[0:7] pins of LPDDR4 module */ 739 6 7 5 4 3 1 0 2 740 /* DQA[8:15] pins of LPDDR4 module */ 741 12 10 11 13 14 8 9 15 742 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */ 743 16 22 23 20 18 17 19 21 744 /* DQB[7:15] pins of LPDDR4 module with offset of 16 */ 745 30 28 29 25 24 26 27 31 746 747 /* LP4_PHYS_CH0B */ 748 /* DQA[0:7] pins of LPDDR4 module */ 749 7 3 5 2 6 0 1 4 750 /* DQA[8:15] pins of LPDDR4 module */ 751 9 14 12 13 10 11 8 15 752 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */ 753 20 22 23 16 19 17 18 21 754 /* DQB[7:15] pins of LPDDR4 module with offset of 16 */ 755 28 24 26 27 29 30 31 25 756 757 /* LP4_PHYS_CH1A */ 758 759 /* DQA[0:7] pins of LPDDR4 module */ 760 2 1 6 7 5 4 3 0 761 /* DQA[8:15] pins of LPDDR4 module */ 762 11 10 8 9 12 15 13 14 763 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */ 764 17 23 19 16 21 22 20 18 765 /* DQB[7:15] pins of LPDDR4 module with offset of 16 */ 766 31 29 26 25 28 27 24 30 767 768 /* LP4_PHYS_CH1B */ 769 770 /* DQA[0:7] pins of LPDDR4 module */ 771 4 3 7 5 6 1 0 2 772 /* DQA[8:15] pins of LPDDR4 module */ 773 15 9 8 11 14 13 12 10 774 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */ 775 20 23 22 21 18 19 16 17 776 /* DQB[7:15] pins of LPDDR4 module with offset of 16 */ 777 25 28 30 31 26 27 24 29>; 778 779 fspm,dimm0-spd-address = <0>; 780 fspm,dimm1-spd-address = <0>; 781 fspm,skip-cse-rbp = <1>; 782 fspm,enable-s3-heci2 = <0>; 783}; 784 785&fsp_s { 786 u-boot,dm-pre-proper; 787 788 fsps,ish-enable = <0>; 789 fsps,enable-sata = <0>; 790 fsps,i2c6-enable = <I2CX_ENABLE_DISABLED>; 791 fsps,i2c7-enable = <I2CX_ENABLE_DISABLED>; 792 fsps,hsuart3-enable = <HSUARTX_ENABLE_DISABLED>; 793 fsps,spi1-enable = <SPIX_ENABLE_DISABLED>; 794 fsps,spi2-enable = <SPIX_ENABLE_DISABLED>; 795 fsps,sdio-enabled = <0>; 796 797 /* Disable unused clkreq of PCIe root ports */ 798 fsps,pcie-rp-clk-req-number = /bits/ 8 <0 /* wifi/bt */ 799 CLKREQ_DISABLED 800 CLKREQ_DISABLED 801 CLKREQ_DISABLED 802 CLKREQ_DISABLED 803 CLKREQ_DISABLED>; 804 805 /* 806 * GPIO for PERST_0 807 * If the Board has PERST_0 signal, assign the GPIO 808 * If the Board does not have PERST_0, assign GPIO_PRT0_UDEF 809 * 810 * This are not used yet, so comment them out for now. 811 * 812 * prt0-gpio = <GPIO_122>; 813 * 814 * GPIO for SD card detect 815 * sdcard-cd-gpio = <GPIO_177>; 816 */ 817 818 /* 819 * Order is emmc-tx-data-cntl1, emmc-tx-data-cntl2, 820 * emmc-rx-cmd-data-cntl1, emmc-rx-cmd-data-cntl2 821 * 822 * EMMC TX DATA Delay 1 823 * Refer to EDS-Vol2-22.3 824 * [14:8] steps of delay for HS400, each 125ps 825 * [6:0] steps of delay for SDR104/HS200, each 125ps 826 827 /* 828 * EMMC TX DATA Delay 2 829 * Refer to EDS-Vol2-22.3. 830 * [30:24] steps of delay for SDR50, each 125ps 831 * [22:16] steps of delay for DDR50, each 125ps 832 * [14:8] steps of delay for SDR25/HS50, each 125ps 833 * [6:0] steps of delay for SDR12, each 125ps 834 */ 835 836 /* 837 * EMMC RX CMD/DATA Delay 1 838 * Refer to EDS-Vol2-22.3. 839 * [30:24] steps of delay for SDR50, each 125ps 840 * [22:16] steps of delay for DDR50, each 125ps 841 * [14:8] steps of delay for SDR25/HS50, each 125ps 842 * [6:0] steps of delay for SDR12, each 125ps 843 */ 844 845 /* 846 * EMMC RX CMD/DATA Delay 2 847 * Refer to EDS-Vol2-22.3. 848 * [17:16] stands for Rx Clock before Output Buffer 849 * [14:8] steps of delay for Auto Tuning Mode, each 125ps 850 * [6:0] steps of delay for HS200, each 125ps 851 */ 852 /* Enable DPTF */ 853 fsps,dptf-enabled; 854 fsps,emmc-tx-data-cntl1 = <0x0c16>; 855 fsps,emmc-tx-data-cntl2 = <0x28162828>; 856 fsps,emmc-rx-cmd-data-cntl1 = <0x00181717>; 857 fsps,emmc-rx-cmd-data-cntl2 = <0x10008>; 858 859 /* Enable Audio Clock and Power gating */ 860 fsps,hd-audio-clk-gate = <1>; 861 fsps,hd-audio-pwr-gate = <1>; 862 fsps,bios-cfg-lock-down = <1>; 863 864 /* Enable WiFi */ 865 fsps,pcie-root-port-en = [01 00 00 00 00 00]; 866 fsps,pcie-rp-hot-plug = [00 00 00 00 00 00]; 867 868 fsps,skip-mp-init = <1>; 869 fsps,spi-eiss = <0>; 870 fsps,rtc-lock = <0>; 871 872 fsps,port-usb20-per-port-pe-txi-set = [07 07 06 06 07 07 07 01]; 873 fsps,port-usb20-per-port-txi-set = [00 02 00 00 00 00 00 03]; 874 875 fsps,lpss-s0ix-enable = <1>; 876 fsps,usb-otg = <0>; 877 fsps,monitor-mwait-enable = <0>; 878 879 /* 880 * TODO(sjg@chromium.org): Move this to the I2C nodes 881 * Intel Common SoC Config 882 *+-------------------+---------------------------+ 883 *| Field | Value | 884 *+-------------------+---------------------------+ 885 *| I2C0 | Audio | 886 *| I2C2 | TPM | 887 *| I2C3 | Touchscreen | 888 *| I2C4 | Trackpad | 889 *| I2C5 | Digitizer | 890 *+-------------------+---------------------------+ 891 * 892 common_soc_config" = "{ 893 .i2c[0] = { 894 .speed = I2C_SPEED_FAST, 895 .rise-time-ns = 104, 896 .fall-time-ns = 52, 897 }, 898 .i2c[2] = { 899 .early_init = 1, 900 .speed = I2C_SPEED_FAST, 901 .rise-time-ns = 57, 902 .fall-time-ns = 28, 903 }, 904 .i2c[3] = { 905 .speed = I2C_SPEED_FAST, 906 .rise-time-ns = 76, 907 .fall-time-ns = 164, 908 }, 909 .i2c[4] = { 910 .speed = I2C_SPEED_FAST, 911 .rise-time-ns = 114, 912 .fall-time-ns = 164, 913 .data_hold_time_ns = 350, 914 }, 915 .i2c[5] = { 916 .speed = I2C_SPEED_FAST, 917 .rise-time-ns = 152, 918 .fall-time-ns = 30, 919 }, 920 }" 921 */ 922 923 /* Minimum SLP S3 assertion width 28ms */ 924 slp-s3-assertion-width-usecs = <28000>; 925 926 pads = < 927 /* PCIE_WAKE[0:3]_N */ 928 PAD_CFG_GPI_SCI_LOW(GPIO_205, UP_20K, DEEP, EDGE_SINGLE) /* WLAN */ 929 PAD_CFG_GPI(GPIO_206, UP_20K, DEEP) /* Unused */ 930 PAD_CFG_GPI(GPIO_207, UP_20K, DEEP) /* Unused */ 931 PAD_CFG_GPI(GPIO_208, UP_20K, DEEP) /* Unused */ 932 933 /* EMMC interface */ 934 PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1) /* EMMC_CLK */ 935 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_157, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D0 */ 936 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_158, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D1 */ 937 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_159, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D2 */ 938 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_160, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D3 */ 939 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_161, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D4 */ 940 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D5 */ 941 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D6 */ 942 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_164, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D7 */ 943 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_CMD */ 944 PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1) /* EMMC_RCLK */ 945 946 /* SDIO -- unused */ 947 PAD_CFG_GPI(GPIO_166, UP_20K, DEEP) /* SDIO_CLK */ 948 PAD_CFG_GPI(GPIO_167, UP_20K, DEEP) /* SDIO_D0 */ 949 /* Configure SDIO to enable power gating */ 950 PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1) /* SDIO_D1 */ 951 PAD_CFG_GPI(GPIO_169, UP_20K, DEEP) /* SDIO_D2 */ 952 PAD_CFG_GPI(GPIO_170, UP_20K, DEEP) /* SDIO_D3 */ 953 PAD_CFG_GPI(GPIO_171, UP_20K, DEEP) /* SDIO_CMD */ 954 955 /* SDCARD */ 956 /* Pull down clock by 20K */ 957 PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1) /* SDCARD_CLK */ 958 PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1) /* SDCARD_D0 */ 959 PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1) /* SDCARD_D1 */ 960 PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1) /* SDCARD_D2 */ 961 PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1) /* SDCARD_D3 */ 962 /* Card detect is active LOW with external pull up */ 963 PAD_CFG_NF(GPIO_177, NONE, DEEP, NF1) /* SDCARD_CD_N */ 964 PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1) /* SDCARD_CMD */ 965 /* CLK feedback, internal signal, needs 20K pull down */ 966 PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1) /* SDCARD_CLK_FB */ 967 /* No h/w write proect for uSD cards, pull down by 20K */ 968 PAD_CFG_NF(GPIO_186, DN_20K, DEEP, NF1) /* SDCARD_LVL_WP */ 969 /* EN_SD_SOCKET_PWR_L for SD slot power control. Default on */ 970 PAD_CFG_GPO(GPIO_183, 0, DEEP) /* SDIO_PWR_DOWN_N */ 971 972 /* SMBus -- unused */ 973 PAD_CFG_GPI(SMB_ALERTB, UP_20K, DEEP) /* SMB_ALERT _N */ 974 PAD_CFG_GPI(SMB_CLK, UP_20K, DEEP) /* SMB_CLK */ 975 PAD_CFG_GPI(SMB_DATA, UP_20K, DEEP) /* SMB_DATA */ 976 977 /* LPC */ 978 PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1) /* LPC_SERIRQ */ 979 PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1) /* LPC_CLKOUT0 */ 980 PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1) 981 PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1) /* LPC_AD0 */ 982 PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1) /* LPC_AD1 */ 983 PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1) /* LPC_AD2 */ 984 PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1) /* LPC_AD3 */ 985 PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1) /* LPC_CLKRUN_N */ 986 PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */ 987 988 /* I2C0 - Audio */ 989 PAD_CFG_NF(GPIO_124, UP_2K, DEEP, NF1) /* LPSS_I2C0_SDA */ 990 PAD_CFG_NF(GPIO_125, UP_2K, DEEP, NF1) /* LPSS_I2C0_SCL */ 991 992 /* I2C1 - NFC with external pulls */ 993 PAD_CFG_NF(GPIO_126, NONE, DEEP, NF1) /* LPSS_I2C1_SDA */ 994 PAD_CFG_NF(GPIO_127, NONE, DEEP, NF1) /* LPSS_I2C1_SCL */ 995 996 /* I2C2 - TPM */ 997 PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1) /* LPSS_I2C2_SDA */ 998 PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1) /* LPSS_I2C2_SCL */ 999 1000 /* I2C3 - touch */ 1001 PAD_CFG_NF(GPIO_130, UP_2K, DEEP, NF1) /* LPSS_I2C3_SDA */ 1002 PAD_CFG_NF(GPIO_131, UP_2K, DEEP, NF1) /* LPSS_I2C3_SCL */ 1003 1004 /* I2C4 - trackpad */ 1005 /* LPSS_I2C4_SDA */ 1006 PAD_CFG_NF_IOSSTATE(GPIO_132, UP_2K, DEEP, NF1, HIZCRX1) 1007 /* LPSS_I2C4_SCL */ 1008 PAD_CFG_NF_IOSSTATE(GPIO_133, UP_2K, DEEP, NF1, HIZCRX1) 1009 1010 /* I2C5 -- pen with external pulls */ 1011 PAD_CFG_NF(GPIO_134, NONE, DEEP, NF1) /* LPSS_I2C5_SDA */ 1012 PAD_CFG_NF(GPIO_135, NONE, DEEP, NF1) /* LPSS_I2C5_SCL */ 1013 1014 /* I2C6-7 -- unused */ 1015 PAD_CFG_GPI(GPIO_136, UP_20K, DEEP) /* LPSS_I2C6_SDA */ 1016 PAD_CFG_GPI(GPIO_137, UP_20K, DEEP) /* LPSS_I2C6_SCL */ 1017 PAD_CFG_GPI(GPIO_138, UP_20K, DEEP) /* LPSS_I2C7_SDA */ 1018 PAD_CFG_GPI(GPIO_139, UP_20K, DEEP) /* LPSS_I2C7_SCL */ 1019 1020 /* Audio Amp - I2S6 */ 1021 PAD_CFG_NF(GPIO_146, NATIVE, DEEP, NF2) /* ISH_GPIO_0 - I2S6_BCLK */ 1022 PAD_CFG_NF(GPIO_147, NATIVE, DEEP, NF2) /* ISH_GPIO_1 - I2S6_WS_SYNC */ 1023 PAD_CFG_GPI(GPIO_148, UP_20K, DEEP) /* ISH_GPIO_2 - unused */ 1024 PAD_CFG_NF(GPIO_149, NATIVE, DEEP, NF2) /* ISH_GPIO_3 - I2S6_SDO */ 1025 1026 /* NFC Reset */ 1027 PAD_CFG_GPO(GPIO_150, 1, DEEP) /* ISH_GPIO_4 */ 1028 1029 PAD_CFG_GPI(GPIO_151, UP_20K, DEEP) /* ISH_GPIO_5 - unused */ 1030 1031 /* Touch enable */ 1032 PAD_CFG_GPO(GPIO_152, 1, DEEP) /* ISH_GPIO_6 */ 1033 1034 PAD_CFG_GPI(GPIO_153, UP_20K, DEEP) /* ISH_GPIO_7 - unused */ 1035 PAD_CFG_GPI(GPIO_154, UP_20K, DEEP) /* ISH_GPIO_8 - unused */ 1036 PAD_CFG_GPI(GPIO_155, UP_20K, DEEP) /* ISH_GPIO_9 - unused */ 1037 1038 /* PCIE_CLKREQ[0:3]_N */ 1039 PAD_CFG_NF(GPIO_209, NONE, DEEP, NF1) /* WLAN with external pull */ 1040 PAD_CFG_GPI(GPIO_210, UP_20K, DEEP) /* unused */ 1041 PAD_CFG_GPI(GPIO_211, UP_20K, DEEP) /* unused */ 1042 PAD_CFG_GPI(GPIO_212, UP_20K, DEEP) /* unused */ 1043 1044 /* OSC_CLK_OUT_[0:4] -- unused */ 1045 PAD_CFG_GPI(OSC_CLK_OUT_0, UP_20K, DEEP) 1046 PAD_CFG_GPI(OSC_CLK_OUT_1, UP_20K, DEEP) 1047 PAD_CFG_GPI(OSC_CLK_OUT_2, UP_20K, DEEP) 1048 PAD_CFG_GPI(OSC_CLK_OUT_3, UP_20K, DEEP) 1049 PAD_CFG_GPI(OSC_CLK_OUT_4, UP_20K, DEEP) 1050 1051 /* PMU Signals */ 1052 PAD_CFG_GPI(PMU_AC_PRESENT, UP_20K, DEEP) /* PMU_AC_PRESENT - unused */ 1053 PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1) /* PMU_BATLOW_N */ 1054 PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1) /* PMU_PLTRST_N */ 1055 PAD_CFG_NF(PMU_PWRBTN_B, UP_20K, DEEP, NF1) /* PMU_PWRBTN_N */ 1056 PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1) /* PMU_RSTBTN_N */ 1057 PAD_CFG_NF_IOSSTATE(PMU_SLP_S0_B, NONE, DEEP, NF1, IGNORE) /* PMU_SLP_S0_N */ 1058 PAD_CFG_NF(PMU_SLP_S3_B, NONE, DEEP, NF1) /* PMU_SLP_S3_N */ 1059 PAD_CFG_NF(PMU_SLP_S4_B, NONE, DEEP, NF1) /* PMU_SLP_S4_N */ 1060 PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1) /* PMU_SUSCLK */ 1061 PAD_CFG_GPO(PMU_WAKE_B, 1, DEEP) /* EN_PP3300_EMMC */ 1062 PAD_CFG_NF(SUS_STAT_B, NONE, DEEP, NF1) /* SUS_STAT_N */ 1063 PAD_CFG_NF(SUSPWRDNACK, NONE, DEEP, NF1) /* SUSPWRDNACK */ 1064 1065 /* DDI[0:1] SDA and SCL -- unused */ 1066 PAD_CFG_GPI(GPIO_187, UP_20K, DEEP) /* HV_DDI0_DDC_SDA */ 1067 PAD_CFG_GPI(GPIO_188, UP_20K, DEEP) /* HV_DDI0_DDC_SCL */ 1068 PAD_CFG_GPI(GPIO_189, UP_20K, DEEP) /* HV_DDI1_DDC_SDA */ 1069 PAD_CFG_GPI(GPIO_190, UP_20K, DEEP) /* HV_DDI1_DDC_SCL */ 1070 1071 /* MIPI I2C -- unused */ 1072 PAD_CFG_GPI(GPIO_191, UP_20K, DEEP) /* MIPI_I2C_SDA */ 1073 PAD_CFG_GPI(GPIO_192, UP_20K, DEEP) /* MIPI_I2C_SCL */ 1074 1075 /* Panel 0 control */ 1076 PAD_CFG_NF(GPIO_193, NATIVE, DEEP, NF1) /* PNL0_VDDEN */ 1077 PAD_CFG_NF(GPIO_194, NATIVE, DEEP, NF1) /* PNL0_BKLTEN */ 1078 PAD_CFG_NF(GPIO_195, NATIVE, DEEP, NF1) /* PNL0_BKLTCTL */ 1079 1080 /* Panel 1 control -- unused */ 1081 PAD_CFG_NF(GPIO_196, NATIVE, DEEP, NF1) /* PNL1_VDDEN */ 1082 PAD_CFG_NF(GPIO_197, NATIVE, DEEP, NF1) /* PNL1_BKLTEN */ 1083 PAD_CFG_NF(GPIO_198, NATIVE, DEEP, NF1) /* PNL1_BKLTCTL */ 1084 1085 /* Hot plug detect */ 1086 PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF2) /* HV_DDI1_HPD */ 1087 PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2) /* HV_DDI0_HPD */ 1088 1089 /* MDSI signals -- unused */ 1090 PAD_CFG_GPI(GPIO_201, UP_20K, DEEP) /* MDSI_A_TE */ 1091 PAD_CFG_GPI(GPIO_202, UP_20K, DEEP) /* MDSI_A_TE */ 1092 1093 /* USB overcurrent pins */ 1094 PAD_CFG_NF(GPIO_203, UP_20K, DEEP, NF1) /* USB_OC0_N */ 1095 PAD_CFG_NF(GPIO_204, UP_20K, DEEP, NF1) /* USB_OC1_N */ 1096 1097 /* PMC SPI -- almost entirely unused */ 1098 PAD_CFG_GPI(PMC_SPI_FS0, UP_20K, DEEP) 1099 PAD_CFG_NF(PMC_SPI_FS1, UP_20K, DEEP, NF2) /* HV_DDI2_HPD -- EDP HPD */ 1100 PAD_CFG_GPI(PMC_SPI_FS2, UP_20K, DEEP) 1101 PAD_CFG_GPI(PMC_SPI_RXD, UP_20K, DEEP) 1102 PAD_CFG_GPI(PMC_SPI_TXD, UP_20K, DEEP) 1103 PAD_CFG_GPI(PMC_SPI_CLK, UP_20K, DEEP) 1104 1105 /* PMIC Signals Unused signals related to an old PMIC interface */ 1106 PAD_CFG_NF_IOSSTATE(PMIC_RESET_B, NATIVE, DEEP, NF1, IGNORE) /* PMIC_RESET_B */ 1107 PAD_CFG_GPI(GPIO_213, NONE, DEEP) /* unused external pull */ 1108 PAD_CFG_GPI(GPIO_214, UP_20K, DEEP) /* unused */ 1109 PAD_CFG_GPI(GPIO_215, UP_20K, DEEP) /* unused */ 1110 PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1) /* THERMTRIP_N */ 1111 PAD_CFG_GPI(PMIC_STDBY, UP_20K, DEEP) /* unused */ 1112 PAD_CFG_NF(PROCHOT_B, UP_20K, DEEP, NF1) /* PROCHOT_N */ 1113 PAD_CFG_NF(PMIC_I2C_SCL, UP_1K, DEEP, NF1) /* PMIC_I2C_SCL */ 1114 PAD_CFG_NF(PMIC_I2C_SDA, UP_1K, DEEP, NF1) /* PMIC_I2C_SDA */ 1115 1116 /* I2S1 -- largely unused */ 1117 PAD_CFG_GPI(GPIO_74, UP_20K, DEEP) /* I2S1_MCLK */ 1118 PAD_CFG_GPI(GPIO_75, UP_20K, DEEP) /* I2S1_BCLK -- PCH_WP */ 1119 PAD_CFG_GPO(GPIO_76, 0, DEEP) /* I2S1_WS_SYNC -- SPK_PA_EN */ 1120 PAD_CFG_GPI(GPIO_77, UP_20K, DEEP) /* I2S1_SDI */ 1121 PAD_CFG_GPO(GPIO_78, 1, DEEP) /* I2S1_SDO -- EN_PP3300_DX_LTE_SOC */ 1122 1123 /* DMIC or I2S4 */ 1124 /* AVS_DMIC_CLK_A1 */ 1125 PAD_CFG_NF_IOSSTATE(GPIO_79, NATIVE, DEEP, NF1, IGNORE) 1126 PAD_CFG_NF(GPIO_80, NATIVE, DEEP, NF1) /* AVS_DMIC_CLK_B1 */ 1127 PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF1) /* AVS_DMIC_DATA_1 */ 1128 PAD_CFG_GPI(GPIO_82, DN_20K, DEEP) /* unused -- strap */ 1129 PAD_CFG_NF(GPIO_83, NATIVE, DEEP, NF1) /* AVS_DMIC_DATA_2 */ 1130 1131 /* I2S2 -- Headset amp */ 1132 PAD_CFG_NF(GPIO_84, NATIVE, DEEP, NF1) /* AVS_I2S2_MCLK */ 1133 PAD_CFG_NF(GPIO_85, NATIVE, DEEP, NF1) /* AVS_I2S2_BCLK */ 1134 PAD_CFG_NF(GPIO_86, NATIVE, DEEP, NF1) /* AVS_I2S2_SW_SYNC */ 1135 PAD_CFG_NF(GPIO_87, NATIVE, DEEP, NF1) /* AVS_I2S2_SDI */ 1136 PAD_CFG_NF(GPIO_88, NATIVE, DEEP, NF1) /* AVS_I2S2_SDO */ 1137 1138 /* I2S3 -- largely unused */ 1139 PAD_CFG_GPI(GPIO_89, UP_20K, DEEP) /* unused */ 1140 PAD_CFG_GPI(GPIO_90, UP_20K, DEEP) /* GPS_HOST_WAKE */ 1141 PAD_CFG_GPO(GPIO_91, 1, DEEP) /* GPS_EN */ 1142 PAD_CFG_GPI(GPIO_92, DN_20K, DEEP) /* unused -- strap */ 1143 1144 /* Fast SPI */ 1145 PAD_CFG_NF_IOSSTATE(GPIO_97, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_CS0_B */ 1146 PAD_CFG_GPI(GPIO_98, UP_20K, DEEP) /* FST_SPI_CS1_B -- unused */ 1147 PAD_CFG_NF_IOSSTATE(GPIO_99, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_MOSI_IO0 */ 1148 PAD_CFG_NF_IOSSTATE(GPIO_100, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_MISO_IO1 */ 1149 PAD_CFG_GPI(GPIO_101, NONE, DEEP) /* FST_IO2 -- MEM_CONFIG0 */ 1150 PAD_CFG_GPI(GPIO_102, NONE, DEEP) /* FST_IO3 -- MEM_CONFIG1 */ 1151 PAD_CFG_NF_IOSSTATE(GPIO_103, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_CLK */ 1152 PAD_CFG_NF_IOSSTATE(FST_SPI_CLK_FB, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_CLK_FB */ 1153 PAD_CFG_NF_IOSSTATE(GPIO_106, NATIVE, DEEP, NF3, IGNORE) /* FST_SPI_CS2_N */ 1154 1155 /* SIO_SPI_0 - Used for FP */ 1156 PAD_CFG_NF(GPIO_104, NATIVE, DEEP, NF1) /* SIO_SPI_0_CLK */ 1157 PAD_CFG_NF(GPIO_105, NATIVE, DEEP, NF1) /* SIO_SPI_0_FS0 */ 1158 PAD_CFG_NF(GPIO_109, NATIVE, DEEP, NF1) /* SIO_SPI_0_RXD */ 1159 PAD_CFG_NF(GPIO_110, NATIVE, DEEP, NF1) /* SIO_SPI_0_TXD */ 1160 1161 /* SIO_SPI_1 -- largely unused */ 1162 PAD_CFG_GPI(GPIO_111, UP_20K, DEEP) /* SIO_SPI_1_CLK */ 1163 PAD_CFG_GPI(GPIO_112, UP_20K, DEEP) /* SIO_SPI_1_FS0 */ 1164 PAD_CFG_GPI(GPIO_113, UP_20K, DEEP) /* SIO_SPI_1_FS1 */ 1165 /* Headset interrupt */ 1166 PAD_CFG_GPI_APIC_LOW(GPIO_116, NONE, DEEP) /* SIO_SPI_1_RXD */ 1167 PAD_CFG_GPI(GPIO_117, UP_20K, DEEP) /* SIO_SPI_1_TXD */ 1168 1169 /* SIO_SPI_2 -- unused */ 1170 PAD_CFG_GPI(GPIO_118, UP_20K, DEEP) /* SIO_SPI_2_CLK */ 1171 PAD_CFG_GPI(GPIO_119, UP_20K, DEEP) /* SIO_SPI_2_FS0 */ 1172 PAD_CFG_GPI(GPIO_120, UP_20K, DEEP) /* SIO_SPI_2_FS1 */ 1173 PAD_CFG_GPI(GPIO_121, UP_20K, DEEP) /* SIO_SPI_2_FS2 */ 1174 /* WLAN_PE_RST - default to deasserted */ 1175 PAD_CFG_GPO(GPIO_122, 0, DEEP) /* SIO_SPI_2_RXD */ 1176 PAD_CFG_GPI(GPIO_123, UP_20K, DEEP) /* SIO_SPI_2_TXD */ 1177 1178 /* Debug tracing */ 1179 PAD_CFG_GPI(GPIO_0, UP_20K, DEEP) 1180 PAD_CFG_GPI(GPIO_1, UP_20K, DEEP) 1181 PAD_CFG_GPI(GPIO_2, UP_20K, DEEP) 1182 PAD_CFG_GPI_SCI_HIGH(GPIO_3, DN_20K, DEEP, LEVEL) /* FP_INT */ 1183 PAD_CFG_GPI(GPIO_4, UP_20K, DEEP) 1184 PAD_CFG_GPI(GPIO_5, UP_20K, DEEP) 1185 PAD_CFG_GPI(GPIO_6, UP_20K, DEEP) 1186 PAD_CFG_GPI(GPIO_7, UP_20K, DEEP) 1187 PAD_CFG_GPI(GPIO_8, UP_20K, DEEP) 1188 1189 PAD_CFG_GPI_APIC_LOW(GPIO_9, NONE, DEEP) /* dTPM IRQ */ 1190 PAD_CFG_GPI(GPIO_10, DN_20K, DEEP) /* Board phase enforcement */ 1191 PAD_CFG_GPI_SCI_LOW(GPIO_11, NONE, DEEP, EDGE_SINGLE) /* EC SCI */ 1192 PAD_CFG_GPI(GPIO_12, UP_20K, DEEP) /* unused */ 1193 PAD_CFG_GPI_APIC_LOW(GPIO_13, NONE, DEEP) /* PEN_INT_ODL */ 1194 PAD_CFG_GPI_APIC_HIGH(GPIO_14, DN_20K, DEEP) /* FP_INT */ 1195 PAD_CFG_GPI_SCI_LOW(GPIO_15, NONE, DEEP, EDGE_SINGLE) /* TRACKPAD_INT_1V8_ODL */ 1196 PAD_CFG_GPI(GPIO_16, UP_20K, DEEP) /* unused */ 1197 PAD_CFG_GPI(GPIO_17, UP_20K, DEEP) /* 1 vs 4 DMIC config */ 1198 PAD_CFG_GPI_APIC_LOW(GPIO_18, NONE, DEEP) /* Trackpad IRQ */ 1199 PAD_CFG_GPI(GPIO_19, UP_20K, DEEP) /* unused */ 1200 PAD_CFG_GPI_APIC_LOW(GPIO_20, UP_20K, DEEP) /* NFC IRQ */ 1201 PAD_CFG_GPI_APIC_LOW(GPIO_21, NONE, DEEP) /* Touch IRQ */ 1202 PAD_CFG_GPI_SCI_LOW(GPIO_22, NONE, DEEP, EDGE_SINGLE) /* EC wake */ 1203 PAD_CFG_GPI(GPIO_23, UP_20K, DEEP) /* unused */ 1204 PAD_CFG_GPI(GPIO_24, NONE, DEEP) /* PEN_PDCT_ODL */ 1205 PAD_CFG_GPI(GPIO_25, UP_20K, DEEP) /* unused */ 1206 PAD_CFG_GPI(GPIO_26, UP_20K, DEEP) /* unused */ 1207 PAD_CFG_GPI(GPIO_27, UP_20K, DEEP) /* unused */ 1208 PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP) /* TPM IRQ */ 1209 PAD_CFG_GPO(GPIO_29, 1, DEEP) /* FP reset */ 1210 PAD_CFG_GPI_APIC_LOW(GPIO_30, NONE, DEEP) /* KB IRQ */ 1211 PAD_CFG_GPO(GPIO_31, 0, DEEP) /* NFC FW DL */ 1212 PAD_CFG_NF(GPIO_32, NONE, DEEP, NF5) /* SUS_CLK2 */ 1213 PAD_CFG_GPI_APIC_LOW(GPIO_33, NONE, DEEP) /* PMIC IRQ */ 1214 PAD_CFG_GPI(GPIO_34, UP_20K, DEEP) /* unused */ 1215 PAD_CFG_GPO(GPIO_35, 0, DEEP) /* PEN_RESET - active high */ 1216 PAD_CFG_GPO(GPIO_36, 0, DEEP) /* touch reset */ 1217 PAD_CFG_GPI(GPIO_37, UP_20K, DEEP) /* unused */ 1218 1219 /* LPSS_UART[0:2] */ 1220 PAD_CFG_GPI(GPIO_38, NONE, DEEP) /* LPSS_UART0_RXD - MEM_CONFIG2*/ 1221 /* Next 2 are straps */ 1222 PAD_CFG_GPI(GPIO_39, DN_20K, DEEP) /* LPSS_UART0_TXD - unused */ 1223 PAD_CFG_GPI(GPIO_40, DN_20K, DEEP) /* LPSS_UART0_RTS - unused */ 1224 PAD_CFG_GPI(GPIO_41, NONE, DEEP) /* LPSS_UART0_CTS - EC_IN_RW */ 1225 PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1) /* LPSS_UART1_RXD */ 1226 PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1) /* LPSS_UART1_TXD */ 1227 PAD_CFG_GPO(GPIO_44, 1, DEEP) /* GPS_RST_ODL */ 1228 PAD_CFG_GPI(GPIO_45, NONE, DEEP) /* LPSS_UART1_CTS - MEM_CONFIG3 */ 1229 PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1) /* LPSS_UART2_RXD */ 1230 PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, TX1_RX_DCR_X0) /* UART2 TX */ 1231 PAD_CFG_GPI(GPIO_48, UP_20K, DEEP) /* LPSS_UART2_RTS - unused */ 1232 PAD_CFG_GPI_SMI_LOW(GPIO_49, NONE, DEEP, EDGE_SINGLE) /* LPSS_UART2_CTS - EC_SMI_L */ 1233 1234 /* Camera interface -- completely unused */ 1235 PAD_CFG_GPI(GPIO_62, UP_20K, DEEP) /* GP_CAMERASB00 */ 1236 PAD_CFG_GPI(GPIO_63, UP_20K, DEEP) /* GP_CAMERASB01 */ 1237 PAD_CFG_GPI(GPIO_64, UP_20K, DEEP) /* GP_CAMERASB02 */ 1238 PAD_CFG_GPI(GPIO_65, UP_20K, DEEP) /* GP_CAMERASB03 */ 1239 PAD_CFG_GPI(GPIO_66, UP_20K, DEEP) /* GP_CAMERASB04 */ 1240 PAD_CFG_GPI(GPIO_67, UP_20K, DEEP) /* GP_CAMERASB05 */ 1241 PAD_CFG_GPI(GPIO_68, UP_20K, DEEP) /* GP_CAMERASB06 */ 1242 PAD_CFG_GPI(GPIO_69, UP_20K, DEEP) /* GP_CAMERASB07 */ 1243 PAD_CFG_GPI(GPIO_70, UP_20K, DEEP) /* GP_CAMERASB08 */ 1244 PAD_CFG_GPI(GPIO_71, UP_20K, DEEP) /* GP_CAMERASB09 */ 1245 PAD_CFG_GPI(GPIO_72, UP_20K, DEEP) /* GP_CAMERASB10 */ 1246 PAD_CFG_GPI(GPIO_73, UP_20K, DEEP) /* GP_CAMERASB11 */ 1247 >; 1248}; 1249 1250&rtc { 1251 #address-cells = <1>; 1252 #size-cells = <0>; 1253 u-boot,dm-pre-proper; 1254}; 1255