1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2008-2020 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <log.h>
8 #include <asm/io.h>
9 #include <fsl_ddr_sdram.h>
10 #include <asm/processor.h>
11 #include <linux/delay.h>
12
13 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
14 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
15 #endif
16
17 /*
18 * regs has the to-be-set values for DDR controller registers
19 * ctrl_num is the DDR controller number
20 * step: 0 goes through the initialization in one pass
21 * 1 sets registers and returns before enabling controller
22 * 2 resumes from step 1 and continues to initialize
23 * Dividing the initialization to two steps to deassert DDR reset signal
24 * to comply with JEDEC specs for RDIMMs.
25 */
fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t * regs,unsigned int ctrl_num,int step)26 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
27 unsigned int ctrl_num, int step)
28 {
29 unsigned int i, bus_width;
30 struct ccsr_ddr __iomem *ddr;
31 u32 temp_sdram_cfg;
32 u32 total_gb_size_per_controller;
33 int timeout;
34 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
35 int timeout_save;
36 volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR;
37 unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t;
38 int csn = -1;
39 #endif
40 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
41 u32 save1, save2;
42 #endif
43 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) || \
44 (defined(CONFIG_SYS_FSL_ERRATUM_A008378) && \
45 defined(CONFIG_SYS_FSL_DDRC_GEN4)) || \
46 defined(CONFIG_SYS_FSL_ERRATUM_A008109)
47 u32 val32;
48 #endif
49 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
50 unsigned int ddr_freq;
51 #endif
52
53 switch (ctrl_num) {
54 case 0:
55 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
56 break;
57 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
58 case 1:
59 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
60 break;
61 #endif
62 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
63 case 2:
64 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
65 break;
66 #endif
67 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
68 case 3:
69 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
70 break;
71 #endif
72 default:
73 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
74 return;
75 }
76
77 if (step == 2)
78 goto step2;
79
80 if (regs->ddr_eor)
81 out_be32(&ddr->eor, regs->ddr_eor);
82 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
83 debug("Workaround for ERRATUM_DDR111_DDR134\n");
84 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
85 cs_sa = (regs->cs[i].bnds >> 16) & 0xfff;
86 cs_ea = regs->cs[i].bnds & 0xfff;
87 if ((cs_sa <= 0xff) && (cs_ea >= 0xff)) {
88 csn = i;
89 csn_bnds_backup = regs->cs[i].bnds;
90 csn_bnds_t = (unsigned int *) ®s->cs[i].bnds;
91 if (cs_ea > 0xeff)
92 *csn_bnds_t = regs->cs[i].bnds + 0x01000000;
93 else
94 *csn_bnds_t = regs->cs[i].bnds + 0x01000100;
95 debug("Found cs%d_bns (0x%08x) covering 0xff000000, "
96 "change it to 0x%x\n",
97 csn, csn_bnds_backup, regs->cs[i].bnds);
98 break;
99 }
100 }
101 #endif
102 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
103 if (i == 0) {
104 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
105 out_be32(&ddr->cs0_config, regs->cs[i].config);
106 out_be32(&ddr->cs0_config_2, regs->cs[i].config_2);
107
108 } else if (i == 1) {
109 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
110 out_be32(&ddr->cs1_config, regs->cs[i].config);
111 out_be32(&ddr->cs1_config_2, regs->cs[i].config_2);
112
113 } else if (i == 2) {
114 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
115 out_be32(&ddr->cs2_config, regs->cs[i].config);
116 out_be32(&ddr->cs2_config_2, regs->cs[i].config_2);
117
118 } else if (i == 3) {
119 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
120 out_be32(&ddr->cs3_config, regs->cs[i].config);
121 out_be32(&ddr->cs3_config_2, regs->cs[i].config_2);
122 }
123 }
124
125 out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
126 out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
127 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
128 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
129 out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
130 out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
131 out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
132 out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
133 out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
134 out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
135 out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
136 out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
137 out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
138 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
139 out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
140 out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
141 out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
142 out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
143 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
144 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
145 #ifndef CONFIG_SYS_FSL_DDR_EMU
146 /*
147 * Skip these two registers if running on emulator
148 * because emulator doesn't have skew between bytes.
149 */
150
151 if (regs->ddr_wrlvl_cntl_2)
152 out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
153 if (regs->ddr_wrlvl_cntl_3)
154 out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
155 #endif
156
157 out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
158 out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
159 out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
160 out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1);
161 #ifdef CONFIG_DEEP_SLEEP
162 if (is_warm_boot()) {
163 out_be32(&ddr->sdram_cfg_2,
164 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
165 out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
166 out_be32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
167
168 /* DRAM VRef will not be trained */
169 out_be32(&ddr->ddr_cdr2,
170 regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
171 } else
172 #endif
173 {
174 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
175 out_be32(&ddr->init_addr, regs->ddr_init_addr);
176 out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
177 out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
178 }
179 out_be32(&ddr->err_disable, regs->err_disable);
180 out_be32(&ddr->err_int_en, regs->err_int_en);
181 for (i = 0; i < 32; i++) {
182 if (regs->debug[i]) {
183 debug("Write to debug_%d as %08x\n", i+1, regs->debug[i]);
184 out_be32(&ddr->debug[i], regs->debug[i]);
185 }
186 }
187
188 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
189 out_be32(&ddr->debug[12], 0x00000015);
190 out_be32(&ddr->debug[21], 0x24000000);
191 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */
192
193 /*
194 * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
195 * deasserted. Clocks start when any chip select is enabled and clock
196 * control register is set. Because all DDR components are connected to
197 * one reset signal, this needs to be done in two steps. Step 1 is to
198 * get the clocks started. Step 2 resumes after reset signal is
199 * deasserted.
200 */
201 if (step == 1) {
202 udelay(200);
203 return;
204 }
205
206 step2:
207 /* Set, but do not enable the memory */
208 temp_sdram_cfg = regs->ddr_sdram_cfg;
209 temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
210 out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
211 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
212 debug("Workaround for ERRATUM_DDR_A003\n");
213 if (regs->ddr_sdram_rcw_2 & 0x00f00000) {
214 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff);
215 out_be32(&ddr->debug[2], 0x00000400);
216 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff);
217 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff);
218 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb);
219 out_be32(&ddr->mtcr, 0);
220 save1 = in_be32(&ddr->debug[12]);
221 save2 = in_be32(&ddr->debug[21]);
222 out_be32(&ddr->debug[12], 0x00000015);
223 out_be32(&ddr->debug[21], 0x24000000);
224 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff);
225 out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN);
226
227 asm volatile("sync;isync");
228 while (!(in_be32(&ddr->debug[1]) & 0x2))
229 ;
230
231 switch (regs->ddr_sdram_rcw_2 & 0x00f00000) {
232 case 0x00000000:
233 out_be32(&ddr->sdram_md_cntl,
234 MD_CNTL_MD_EN |
235 MD_CNTL_CS_SEL_CS0_CS1 |
236 0x04000000 |
237 MD_CNTL_WRCW |
238 MD_CNTL_MD_VALUE(0x02));
239 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
240 if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
241 break;
242 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
243 ;
244 out_be32(&ddr->sdram_md_cntl,
245 MD_CNTL_MD_EN |
246 MD_CNTL_CS_SEL_CS2_CS3 |
247 0x04000000 |
248 MD_CNTL_WRCW |
249 MD_CNTL_MD_VALUE(0x02));
250 #endif
251 break;
252 case 0x00100000:
253 out_be32(&ddr->sdram_md_cntl,
254 MD_CNTL_MD_EN |
255 MD_CNTL_CS_SEL_CS0_CS1 |
256 0x04000000 |
257 MD_CNTL_WRCW |
258 MD_CNTL_MD_VALUE(0x0a));
259 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
260 if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
261 break;
262 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
263 ;
264 out_be32(&ddr->sdram_md_cntl,
265 MD_CNTL_MD_EN |
266 MD_CNTL_CS_SEL_CS2_CS3 |
267 0x04000000 |
268 MD_CNTL_WRCW |
269 MD_CNTL_MD_VALUE(0x0a));
270 #endif
271 break;
272 case 0x00200000:
273 out_be32(&ddr->sdram_md_cntl,
274 MD_CNTL_MD_EN |
275 MD_CNTL_CS_SEL_CS0_CS1 |
276 0x04000000 |
277 MD_CNTL_WRCW |
278 MD_CNTL_MD_VALUE(0x12));
279 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
280 if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
281 break;
282 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
283 ;
284 out_be32(&ddr->sdram_md_cntl,
285 MD_CNTL_MD_EN |
286 MD_CNTL_CS_SEL_CS2_CS3 |
287 0x04000000 |
288 MD_CNTL_WRCW |
289 MD_CNTL_MD_VALUE(0x12));
290 #endif
291 break;
292 case 0x00300000:
293 out_be32(&ddr->sdram_md_cntl,
294 MD_CNTL_MD_EN |
295 MD_CNTL_CS_SEL_CS0_CS1 |
296 0x04000000 |
297 MD_CNTL_WRCW |
298 MD_CNTL_MD_VALUE(0x1a));
299 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
300 if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
301 break;
302 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
303 ;
304 out_be32(&ddr->sdram_md_cntl,
305 MD_CNTL_MD_EN |
306 MD_CNTL_CS_SEL_CS2_CS3 |
307 0x04000000 |
308 MD_CNTL_WRCW |
309 MD_CNTL_MD_VALUE(0x1a));
310 #endif
311 break;
312 default:
313 out_be32(&ddr->sdram_md_cntl,
314 MD_CNTL_MD_EN |
315 MD_CNTL_CS_SEL_CS0_CS1 |
316 0x04000000 |
317 MD_CNTL_WRCW |
318 MD_CNTL_MD_VALUE(0x02));
319 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
320 if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
321 break;
322 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
323 ;
324 out_be32(&ddr->sdram_md_cntl,
325 MD_CNTL_MD_EN |
326 MD_CNTL_CS_SEL_CS2_CS3 |
327 0x04000000 |
328 MD_CNTL_WRCW |
329 MD_CNTL_MD_VALUE(0x02));
330 #endif
331 printf("Unsupported RC10\n");
332 break;
333 }
334
335 while (in_be32(&ddr->sdram_md_cntl) & 0x80000000)
336 ;
337 udelay(6);
338 out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
339 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
340 out_be32(&ddr->debug[2], 0x0);
341 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
342 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
343 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
344 out_be32(&ddr->debug[12], save1);
345 out_be32(&ddr->debug[21], save2);
346 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
347
348 }
349 #endif
350
351 #if defined(CONFIG_SYS_FSL_ERRATUM_A008378) && defined(CONFIG_SYS_FSL_DDRC_GEN4)
352 /* Erratum applies when accumulated ECC is used, or DBI is enabled */
353 #define IS_ACC_ECC_EN(v) ((v) & 0x4)
354 #define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
355 if (has_erratum_a008378()) {
356 if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) ||
357 IS_DBI(regs->ddr_sdram_cfg_3)) {
358 val32 = ddr_in32(&ddr->debug[28]);
359 val32 |= (0x9 << 20);
360 ddr_out32(&ddr->debug[28], val32);
361 }
362 debug("Applied errata CONFIG_SYS_FSL_ERRATUM_A008378\n");
363 }
364 #endif
365
366 #if defined(CONFIG_SYS_FSL_ERRATUM_A008109)
367 val32 = in_be32(&ddr->sdram_cfg_2) | 0x800; /* DDR_SLOW */
368 out_be32(&ddr->sdram_cfg_2, val32);
369
370 val32 = in_be32(&ddr->debug[18]) | 0x2;
371 out_be32(&ddr->debug[18], val32);
372
373 out_be32(&ddr->debug[28], 0x30000000);
374 debug("Applied errta CONFIG_SYS_FSL_ERRATUM_A008109\n");
375 #endif
376
377 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
378 ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
379 val32 = in_be32(&ddr->debug[28]);
380 val32 &= 0xff0fff00;
381 if (ddr_freq <= 1333)
382 val32 |= 0x0080006a;
383 else if (ddr_freq <= 1600)
384 val32 |= 0x0070006f;
385 else if (ddr_freq <= 1867)
386 val32 |= 0x00700076;
387 else if (ddr_freq <= 2133)
388 val32 |= 0x0060007b;
389
390 out_be32(&ddr->debug[28], val32);
391 debug("Applied errata CONFIG_SYS_FSL_ERRATUM_A009942\n");
392 #endif
393 /*
394 * For 8572 DDR1 erratum - DDR controller may enter illegal state
395 * when operatiing in 32-bit bus mode with 4-beat bursts,
396 * This erratum does not affect DDR3 mode, only for DDR2 mode.
397 */
398 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
399 debug("Workaround for ERRATUM_DDR_115\n");
400 if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
401 && in_be32(&ddr->sdram_cfg) & 0x80000) {
402 /* set DEBUG_1[31] */
403 setbits_be32(&ddr->debug[0], 1);
404 }
405 #endif
406 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
407 debug("Workaround for ERRATUM_DDR111_DDR134\n");
408 /*
409 * This is the combined workaround for DDR111 and DDR134
410 * following the published errata for MPC8572
411 */
412
413 /* 1. Set EEBACR[3] */
414 setbits_be32(&ecm->eebacr, 0x10000000);
415 debug("Setting EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
416
417 /* 2. Set DINIT in SDRAM_CFG_2*/
418 setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT);
419 debug("Setting sdram_cfg_2[D_INIT] to 0x%08x\n",
420 in_be32(&ddr->sdram_cfg_2));
421
422 /* 3. Set DEBUG_3[21] */
423 setbits_be32(&ddr->debug[2], 0x400);
424 debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
425
426 #endif /* part 1 of the workaound */
427
428 /*
429 * 500 painful micro-seconds must elapse between
430 * the DDR clock setup and the DDR config enable.
431 * DDR2 need 200 us, and DDR3 need 500 us from spec,
432 * we choose the max, that is 500 us for all of case.
433 */
434 udelay(500);
435 asm volatile("sync;isync");
436
437 #ifdef CONFIG_DEEP_SLEEP
438 if (is_warm_boot()) {
439 /* enter self-refresh */
440 setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR);
441 /* do board specific memory setup */
442 board_mem_sleep_setup();
443 temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
444 } else
445 #endif
446 temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI);
447
448 /* Let the controller go */
449 out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
450 asm volatile("sync;isync");
451
452 total_gb_size_per_controller = 0;
453 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
454 if (!(regs->cs[i].config & 0x80000000))
455 continue;
456 total_gb_size_per_controller += 1 << (
457 ((regs->cs[i].config >> 14) & 0x3) + 2 +
458 ((regs->cs[i].config >> 8) & 0x7) + 12 +
459 ((regs->cs[i].config >> 0) & 0x7) + 8 +
460 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
461 26); /* minus 26 (count of 64M) */
462 }
463 if (fsl_ddr_get_intl3r() & 0x80000000) /* 3-way interleaving */
464 total_gb_size_per_controller *= 3;
465 else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */
466 total_gb_size_per_controller <<= 1;
467 /*
468 * total memory / bus width = transactions needed
469 * transactions needed / data rate = seconds
470 * to add plenty of buffer, double the time
471 * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
472 * Let's wait for 800ms
473 */
474 bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
475 >> SDRAM_CFG_DBW_SHIFT);
476 timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
477 (get_ddr_freq(ctrl_num) >> 20)) << 1;
478 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
479 timeout_save = timeout;
480 #endif
481 total_gb_size_per_controller >>= 4; /* shift down to gb size */
482 debug("total %d GB\n", total_gb_size_per_controller);
483 debug("Need to wait up to %d * 10ms\n", timeout);
484
485 /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
486 while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
487 (timeout >= 0)) {
488 udelay(10000); /* throttle polling rate */
489 timeout--;
490 }
491
492 if (timeout <= 0)
493 printf("Waiting for D_INIT timeout. Memory may not work.\n");
494
495 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
496 /* continue this workaround */
497
498 /* 4. Clear DEBUG3[21] */
499 clrbits_be32(&ddr->debug[2], 0x400);
500 debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
501
502 /* DDR134 workaround starts */
503 /* A: Clear sdram_cfg_2[odt_cfg] */
504 clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_ODT_CFG_MASK);
505 debug("Clearing SDRAM_CFG2[ODT_CFG] to 0x%08x\n",
506 in_be32(&ddr->sdram_cfg_2));
507
508 /* B: Set DEBUG1[15] */
509 setbits_be32(&ddr->debug[0], 0x10000);
510 debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
511
512 /* C: Set timing_cfg_2[cpo] to 0b11111 */
513 setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK);
514 debug("Setting TMING_CFG_2[CPO] to 0x%08x\n",
515 in_be32(&ddr->timing_cfg_2));
516
517 /* D: Set D6 to 0x9f9f9f9f */
518 out_be32(&ddr->debug[5], 0x9f9f9f9f);
519 debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5]));
520
521 /* E: Set D7 to 0x9f9f9f9f */
522 out_be32(&ddr->debug[6], 0x9f9f9f9f);
523 debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6]));
524
525 /* F: Set D2[20] */
526 setbits_be32(&ddr->debug[1], 0x800);
527 debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1]));
528
529 /* G: Poll on D2[20] until cleared */
530 while (in_be32(&ddr->debug[1]) & 0x800)
531 udelay(10000); /* throttle polling rate */
532
533 /* H: Clear D1[15] */
534 clrbits_be32(&ddr->debug[0], 0x10000);
535 debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
536
537 /* I: Set sdram_cfg_2[odt_cfg] */
538 setbits_be32(&ddr->sdram_cfg_2,
539 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_ODT_CFG_MASK);
540 debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
541
542 /* Continuing with the DDR111 workaround */
543 /* 5. Set D2[21] */
544 setbits_be32(&ddr->debug[1], 0x400);
545 debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1]));
546
547 /* 6. Poll D2[21] until its cleared */
548 while (in_be32(&ddr->debug[1]) & 0x400)
549 udelay(10000); /* throttle polling rate */
550
551 /* 7. Wait for state machine 2nd run, roughly 400ms/GB */
552 debug("Wait for %d * 10ms\n", timeout_save);
553 udelay(timeout_save * 10000);
554
555 /* 8. Set sdram_cfg_2[dinit] if options requires */
556 setbits_be32(&ddr->sdram_cfg_2,
557 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_D_INIT);
558 debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
559
560 /* 9. Poll until dinit is cleared */
561 timeout = timeout_save;
562 debug("Need to wait up to %d * 10ms\n", timeout);
563 while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
564 (timeout >= 0)) {
565 udelay(10000); /* throttle polling rate */
566 timeout--;
567 }
568
569 if (timeout <= 0)
570 printf("Waiting for D_INIT timeout. Memory may not work.\n");
571
572 /* 10. Clear EEBACR[3] */
573 clrbits_be32(&ecm->eebacr, 10000000);
574 debug("Clearing EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
575
576 if (csn != -1) {
577 csn_bnds_t = (unsigned int *) ®s->cs[csn].bnds;
578 *csn_bnds_t = csn_bnds_backup;
579 debug("Change cs%d_bnds back to 0x%08x\n",
580 csn, regs->cs[csn].bnds);
581 setbits_be32(&ddr->sdram_cfg, 0x2); /* MEM_HALT */
582 switch (csn) {
583 case 0:
584 out_be32(&ddr->cs0_bnds, regs->cs[csn].bnds);
585 break;
586 case 1:
587 out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds);
588 break;
589 #if CONFIG_CHIP_SELECTS_PER_CTRL > 2
590 case 2:
591 out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds);
592 break;
593 case 3:
594 out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds);
595 break;
596 #endif
597 }
598 clrbits_be32(&ddr->sdram_cfg, 0x2);
599 }
600 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */
601 #ifdef CONFIG_DEEP_SLEEP
602 if (is_warm_boot())
603 /* exit self-refresh */
604 clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR);
605 #endif
606 }
607