1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
4  */
5 
6 #include <common.h>
7 #include <clk.h>
8 #include <dm.h>
9 #include <malloc.h>
10 #include <asm/global_data.h>
11 #include <dm/device_compat.h>
12 #include <dm/pinctrl.h>
13 #include <errno.h>
14 #include <asm/gpio.h>
15 #include <asm/io.h>
16 #include <linux/bitops.h>
17 #include "../pinctrl/renesas/sh_pfc.h"
18 
19 #define GPIO_IOINTSEL	0x00	/* General IO/Interrupt Switching Register */
20 #define GPIO_INOUTSEL	0x04	/* General Input/Output Switching Register */
21 #define GPIO_OUTDT	0x08	/* General Output Register */
22 #define GPIO_INDT	0x0c	/* General Input Register */
23 #define GPIO_INTDT	0x10	/* Interrupt Display Register */
24 #define GPIO_INTCLR	0x14	/* Interrupt Clear Register */
25 #define GPIO_INTMSK	0x18	/* Interrupt Mask Register */
26 #define GPIO_MSKCLR	0x1c	/* Interrupt Mask Clear Register */
27 #define GPIO_POSNEG	0x20	/* Positive/Negative Logic Select Register */
28 #define GPIO_EDGLEVEL	0x24	/* Edge/level Select Register */
29 #define GPIO_FILONOFF	0x28	/* Chattering Prevention On/Off Register */
30 #define GPIO_BOTHEDGE	0x4c	/* One Edge/Both Edge Select Register */
31 
32 #define RCAR_MAX_GPIO_PER_BANK		32
33 
34 DECLARE_GLOBAL_DATA_PTR;
35 
36 struct rcar_gpio_priv {
37 	void __iomem		*regs;
38 	int			pfc_offset;
39 };
40 
rcar_gpio_get_value(struct udevice * dev,unsigned offset)41 static int rcar_gpio_get_value(struct udevice *dev, unsigned offset)
42 {
43 	struct rcar_gpio_priv *priv = dev_get_priv(dev);
44 	const u32 bit = BIT(offset);
45 
46 	/*
47 	 * Testing on r8a7790 shows that INDT does not show correct pin state
48 	 * when configured as output, so use OUTDT in case of output pins.
49 	 */
50 	if (readl(priv->regs + GPIO_INOUTSEL) & bit)
51 		return !!(readl(priv->regs + GPIO_OUTDT) & bit);
52 	else
53 		return !!(readl(priv->regs + GPIO_INDT) & bit);
54 }
55 
rcar_gpio_set_value(struct udevice * dev,unsigned offset,int value)56 static int rcar_gpio_set_value(struct udevice *dev, unsigned offset,
57 			       int value)
58 {
59 	struct rcar_gpio_priv *priv = dev_get_priv(dev);
60 
61 	if (value)
62 		setbits_le32(priv->regs + GPIO_OUTDT, BIT(offset));
63 	else
64 		clrbits_le32(priv->regs + GPIO_OUTDT, BIT(offset));
65 
66 	return 0;
67 }
68 
rcar_gpio_set_direction(struct udevice * dev,unsigned offset,bool output)69 static void rcar_gpio_set_direction(struct udevice *dev, unsigned offset,
70 				    bool output)
71 {
72 	struct rcar_gpio_priv *priv = dev_get_priv(dev);
73 	void __iomem *regs = priv->regs;
74 
75 	/*
76 	 * follow steps in the GPIO documentation for
77 	 * "Setting General Output Mode" and
78 	 * "Setting General Input Mode"
79 	 */
80 
81 	/* Configure postive logic in POSNEG */
82 	clrbits_le32(regs + GPIO_POSNEG, BIT(offset));
83 
84 	/* Select "General Input/Output Mode" in IOINTSEL */
85 	clrbits_le32(regs + GPIO_IOINTSEL, BIT(offset));
86 
87 	/* Select Input Mode or Output Mode in INOUTSEL */
88 	if (output)
89 		setbits_le32(regs + GPIO_INOUTSEL, BIT(offset));
90 	else
91 		clrbits_le32(regs + GPIO_INOUTSEL, BIT(offset));
92 }
93 
rcar_gpio_direction_input(struct udevice * dev,unsigned offset)94 static int rcar_gpio_direction_input(struct udevice *dev, unsigned offset)
95 {
96 	rcar_gpio_set_direction(dev, offset, false);
97 
98 	return 0;
99 }
100 
rcar_gpio_direction_output(struct udevice * dev,unsigned offset,int value)101 static int rcar_gpio_direction_output(struct udevice *dev, unsigned offset,
102 				      int value)
103 {
104 	/* write GPIO value to output before selecting output mode of pin */
105 	rcar_gpio_set_value(dev, offset, value);
106 	rcar_gpio_set_direction(dev, offset, true);
107 
108 	return 0;
109 }
110 
rcar_gpio_get_function(struct udevice * dev,unsigned offset)111 static int rcar_gpio_get_function(struct udevice *dev, unsigned offset)
112 {
113 	struct rcar_gpio_priv *priv = dev_get_priv(dev);
114 
115 	if (readl(priv->regs + GPIO_INOUTSEL) & BIT(offset))
116 		return GPIOF_OUTPUT;
117 	else
118 		return GPIOF_INPUT;
119 }
120 
rcar_gpio_request(struct udevice * dev,unsigned offset,const char * label)121 static int rcar_gpio_request(struct udevice *dev, unsigned offset,
122 			     const char *label)
123 {
124 	return pinctrl_gpio_request(dev, offset);
125 }
126 
rcar_gpio_free(struct udevice * dev,unsigned offset)127 static int rcar_gpio_free(struct udevice *dev, unsigned offset)
128 {
129 	return pinctrl_gpio_free(dev, offset);
130 }
131 
132 static const struct dm_gpio_ops rcar_gpio_ops = {
133 	.request		= rcar_gpio_request,
134 	.rfree			= rcar_gpio_free,
135 	.direction_input	= rcar_gpio_direction_input,
136 	.direction_output	= rcar_gpio_direction_output,
137 	.get_value		= rcar_gpio_get_value,
138 	.set_value		= rcar_gpio_set_value,
139 	.get_function		= rcar_gpio_get_function,
140 };
141 
rcar_gpio_probe(struct udevice * dev)142 static int rcar_gpio_probe(struct udevice *dev)
143 {
144 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
145 	struct rcar_gpio_priv *priv = dev_get_priv(dev);
146 	struct fdtdec_phandle_args args;
147 	struct clk clk;
148 	int node = dev_of_offset(dev);
149 	int ret;
150 
151 	priv->regs = dev_read_addr_ptr(dev);
152 	uc_priv->bank_name = dev->name;
153 
154 	ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "gpio-ranges",
155 					     NULL, 3, 0, &args);
156 	priv->pfc_offset = ret == 0 ? args.args[1] : -1;
157 	uc_priv->gpio_count = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
158 
159 	ret = clk_get_by_index(dev, 0, &clk);
160 	if (ret < 0) {
161 		dev_err(dev, "Failed to get GPIO bank clock\n");
162 		return ret;
163 	}
164 
165 	ret = clk_enable(&clk);
166 	clk_free(&clk);
167 	if (ret) {
168 		dev_err(dev, "Failed to enable GPIO bank clock\n");
169 		return ret;
170 	}
171 
172 	return 0;
173 }
174 
175 static const struct udevice_id rcar_gpio_ids[] = {
176 	{ .compatible = "renesas,gpio-r8a7795" },
177 	{ .compatible = "renesas,gpio-r8a7796" },
178 	{ .compatible = "renesas,gpio-r8a77965" },
179 	{ .compatible = "renesas,gpio-r8a77970" },
180 	{ .compatible = "renesas,gpio-r8a77990" },
181 	{ .compatible = "renesas,gpio-r8a77995" },
182 	{ .compatible = "renesas,rcar-gen2-gpio" },
183 	{ .compatible = "renesas,rcar-gen3-gpio" },
184 	{ /* sentinel */ }
185 };
186 
187 U_BOOT_DRIVER(rcar_gpio) = {
188 	.name	= "rcar-gpio",
189 	.id	= UCLASS_GPIO,
190 	.of_match = rcar_gpio_ids,
191 	.ops	= &rcar_gpio_ops,
192 	.priv_auto	= sizeof(struct rcar_gpio_priv),
193 	.probe	= rcar_gpio_probe,
194 };
195