1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 3 * Hayden Fraser (Hayden.Fraser@freescale.com) 4 */ 5 6 #ifndef _M5253DEMO_H 7 #define _M5253DEMO_H 8 9 #include <linux/stringify.h> 10 11 #define CONFIG_MCFTMR 12 13 #define CONFIG_MCFUART 14 #define CONFIG_SYS_UART_PORT (0) 15 16 #undef CONFIG_WATCHDOG /* disable watchdog */ 17 18 19 /* Configuration for environment 20 * Environment is embedded in u-boot in the second sector of the flash 21 */ 22 23 #define LDS_BOARD_TEXT \ 24 . = DEFINED(env_offset) ? env_offset : .; \ 25 env/embedded.o(.text*); 26 27 #ifdef CONFIG_IDE 28 /* ATA */ 29 # define CONFIG_IDE_RESET 1 30 # define CONFIG_IDE_PREINIT 1 31 # define CONFIG_ATAPI 32 # undef CONFIG_LBA48 33 34 # define CONFIG_SYS_IDE_MAXBUS 1 35 # define CONFIG_SYS_IDE_MAXDEVICE 2 36 37 # define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800) 38 # define CONFIG_SYS_ATA_IDE0_OFFSET 0 39 40 # define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ 41 # define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ 42 # define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ 43 # define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ 44 #endif 45 46 #define CONFIG_DRIVER_DM9000 47 #ifdef CONFIG_DRIVER_DM9000 48 # define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300) 49 # define DM9000_IO CONFIG_DM9000_BASE 50 # define DM9000_DATA (CONFIG_DM9000_BASE + 4) 51 # undef CONFIG_DM9000_DEBUG 52 # define CONFIG_DM9000_BYTE_SWAPPED 53 54 # define CONFIG_OVERWRITE_ETHADDR_ONCE 55 56 # define CONFIG_EXTRA_ENV_SETTINGS \ 57 "netdev=eth0\0" \ 58 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 59 "loadaddr=10000\0" \ 60 "u-boot=u-boot.bin\0" \ 61 "load=tftp ${loadaddr) ${u-boot}\0" \ 62 "upd=run load; run prog\0" \ 63 "prog=prot off 0xff800000 0xff82ffff;" \ 64 "era 0xff800000 0xff82ffff;" \ 65 "cp.b ${loadaddr} 0xff800000 ${filesize};" \ 66 "save\0" \ 67 "" 68 #endif 69 70 #define CONFIG_HOSTNAME "M5253DEMO" 71 72 /* I2C */ 73 #define CONFIG_SYS_I2C 74 #define CONFIG_SYS_I2C_FSL 75 #define CONFIG_SYS_FSL_I2C_SPEED 80000 76 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 77 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280 78 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 79 #define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C)) 80 #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF) 81 #define CONFIG_SYS_I2C_PINMUX_SET (0) 82 83 #define CONFIG_SYS_LOAD_ADDR 0x00100000 84 85 #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ 86 #define CONFIG_SYS_FAST_CLK 87 #ifdef CONFIG_SYS_FAST_CLK 88 # define CONFIG_SYS_PLLCR 0x1243E054 89 # define CONFIG_SYS_CLK 140000000 90 #else 91 # define CONFIG_SYS_PLLCR 0x135a4140 92 # define CONFIG_SYS_CLK 70000000 93 #endif 94 95 /* 96 * Low Level Configuration Settings 97 * (address mappings, register initial values, etc.) 98 * You should know what you are doing if you make changes here. 99 */ 100 101 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 102 #define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */ 103 104 /* 105 * Definitions for initial stack pointer and data area (in DPRAM) 106 */ 107 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 108 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 109 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 110 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 111 112 /* 113 * Start addresses for the final memory configuration 114 * (Set up by the startup code) 115 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 116 */ 117 #define CONFIG_SYS_SDRAM_BASE 0x00000000 118 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 119 120 #ifdef CONFIG_MONITOR_IS_IN_RAM 121 # define CONFIG_SYS_MONITOR_BASE 0x20000 122 #else 123 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 124 #endif 125 126 #define CONFIG_SYS_MONITOR_LEN 0x40000 127 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 128 #define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) 129 130 /* 131 * For booting Linux, the board info and command line data 132 * have to be in the first 8 MB of memory, since this is 133 * the maximum mapped by the Linux kernel during initialization ?? 134 */ 135 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 136 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 137 138 /* FLASH organization */ 139 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 140 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 141 #define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */ 142 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 143 144 #define FLASH_SST6401B 0x200 145 #define SST_ID_xF6401B 0x236D236D 146 147 #ifdef CONFIG_SYS_FLASH_CFI 148 /* 149 * Unable to use CFI driver, due to incompatible sector erase command by SST. 150 * Amd/Atmel use 0x30 for sector erase, SST use 0x50. 151 * 0x30 is block erase in SST 152 */ 153 # define CONFIG_SYS_FLASH_SIZE 0x800000 154 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 155 # define CONFIG_FLASH_CFI_LEGACY 156 #else 157 # define CONFIG_SYS_SST_SECT 2048 158 # define CONFIG_SYS_SST_SECTSZ 0x1000 159 # define CONFIG_SYS_FLASH_WRITE_TOUT 500 160 #endif 161 162 /* Cache Configuration */ 163 #define CONFIG_SYS_CACHELINE_SIZE 16 164 165 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 166 CONFIG_SYS_INIT_RAM_SIZE - 8) 167 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 168 CONFIG_SYS_INIT_RAM_SIZE - 4) 169 #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) 170 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ 171 CF_ADDRMASK(8) | \ 172 CF_ACR_EN | CF_ACR_SM_ALL) 173 #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ 174 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 175 CF_ACR_EN | CF_ACR_SM_ALL) 176 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ 177 CF_CACR_DBWE) 178 179 /* Port configuration */ 180 #define CONFIG_SYS_FECI2C 0xF0 181 182 #define CONFIG_SYS_CS0_BASE 0xFF800000 183 #define CONFIG_SYS_CS0_MASK 0x007F0021 184 #define CONFIG_SYS_CS0_CTRL 0x00001D80 185 186 #define CONFIG_SYS_CS1_BASE 0xE0000000 187 #define CONFIG_SYS_CS1_MASK 0x00000001 188 #define CONFIG_SYS_CS1_CTRL 0x00003DD8 189 190 /*----------------------------------------------------------------------- 191 * Port configuration 192 */ 193 #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ 194 #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ 195 #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ 196 #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ 197 #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ 198 #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ 199 #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ 200 201 #endif /* _M5253DEMO_H */ 202