1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2019 NXP
4 */
5
6 #include <common.h>
7 #include <init.h>
8 #include <malloc.h>
9 #include <errno.h>
10 #include <fsl_ddr.h>
11 #include <net.h>
12 #include <asm/global_data.h>
13 #include <asm/io.h>
14 #include <hwconfig.h>
15 #include <fdt_support.h>
16 #include <linux/libfdt.h>
17 #include <env_internal.h>
18 #include <asm/arch-fsl-layerscape/soc.h>
19 #include <asm/arch-fsl-layerscape/fsl_icid.h>
20 #include <i2c.h>
21 #include <asm/arch/soc.h>
22 #ifdef CONFIG_FSL_LS_PPA
23 #include <asm/arch/ppa.h>
24 #endif
25 #include <fsl_immap.h>
26 #include <netdev.h>
27
28 #include <fdtdec.h>
29 #include <miiphy.h>
30 #include "../common/qixis.h"
31 #include "../drivers/net/fsl_enetc.h"
32
33 DECLARE_GLOBAL_DATA_PTR;
34
config_board_mux(void)35 int config_board_mux(void)
36 {
37 #ifndef CONFIG_LPUART
38 #if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS)
39 u8 reg;
40
41 reg = QIXIS_READ(brdcfg[13]);
42 /* Field| Function
43 * 7-6 | Controls I2C3 routing (net CFG_MUX_I2C3):
44 * I2C3 | 10= Routes {SCL, SDA} to CAN1 transceiver as {TX, RX}.
45 * 5-4 | Controls I2C4 routing (net CFG_MUX_I2C4):
46 * I2C4 |11= Routes {SCL, SDA} to CAN2 transceiver as {TX, RX}.
47 */
48 reg &= ~(0xf0);
49 reg |= 0xb0;
50 QIXIS_WRITE(brdcfg[13], reg);
51
52 reg = QIXIS_READ(brdcfg[15]);
53 /* Field| Function
54 * 7 | Controls the CAN1 transceiver (net CFG_CAN1_STBY):
55 * CAN1 | 0= CAN #1 transceiver enabled
56 * 6 | Controls the CAN2 transceiver (net CFG_CAN2_STBY):
57 * CAN2 | 0= CAN #2 transceiver enabled
58 */
59 reg &= ~(0xc0);
60 QIXIS_WRITE(brdcfg[15], reg);
61 #endif
62 #endif
63
64 return 0;
65 }
66
67 #ifdef CONFIG_LPUART
get_lpuart_clk(void)68 u32 get_lpuart_clk(void)
69 {
70 return gd->bus_clk / CONFIG_SYS_FSL_LPUART_CLK_DIV;
71 }
72 #endif
73
board_init(void)74 int board_init(void)
75 {
76 #ifdef CONFIG_ENV_IS_NOWHERE
77 gd->env_addr = (ulong)&default_environment[0];
78 #endif
79
80 #ifdef CONFIG_FSL_CAAM
81 sec_init();
82 #endif
83
84 #ifdef CONFIG_FSL_LS_PPA
85 ppa_init();
86 #endif
87
88 #ifndef CONFIG_SYS_EARLY_PCI_INIT
89 pci_init();
90 #endif
91
92 #if defined(CONFIG_TARGET_LS1028ARDB)
93 u8 val = I2C_MUX_CH_DEFAULT;
94
95 #if !CONFIG_IS_ENABLED(DM_I2C)
96 i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1);
97 #else
98 struct udevice *dev;
99
100 if (!i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev))
101 dm_i2c_write(dev, 0x0b, &val, 1);
102 #endif
103 #endif
104
105 #if defined(CONFIG_TARGET_LS1028ARDB)
106 u8 reg;
107
108 reg = QIXIS_READ(brdcfg[4]);
109 /*
110 * Field | Function
111 * 3 | DisplayPort Power Enable (net DP_PWR_EN):
112 * DPPWR | 0= DP_PWR is enabled.
113 */
114 reg &= ~(DP_PWD_EN_DEFAULT_MASK);
115 QIXIS_WRITE(brdcfg[4], reg);
116 #endif
117 return 0;
118 }
119
board_eth_init(struct bd_info * bis)120 int board_eth_init(struct bd_info *bis)
121 {
122 return pci_eth_init(bis);
123 }
124
125 #ifdef CONFIG_MISC_INIT_R
misc_init_r(void)126 int misc_init_r(void)
127 {
128 config_board_mux();
129
130 return 0;
131 }
132 #endif
133
board_early_init_f(void)134 int board_early_init_f(void)
135 {
136 #ifdef CONFIG_LPUART
137 u8 uart;
138 #endif
139
140 #ifdef CONFIG_SYS_I2C_EARLY_INIT
141 i2c_early_init_f();
142 #endif
143
144 fsl_lsch3_early_init_f();
145
146 #ifdef CONFIG_LPUART
147 /*
148 * Field| Function
149 * --------------------------------------------------------------
150 * 7-6 | Controls I2C3 routing (net CFG_MUX_I2C3):
151 * I2C3 | 11= Routes {SCL, SDA} to LPUART1 header as {SOUT, SIN}.
152 * --------------------------------------------------------------
153 * 5-4 | Controls I2C4 routing (net CFG_MUX_I2C4):
154 * I2C4 |11= Routes {SCL, SDA} to LPUART1 header as {CTS_B, RTS_B}.
155 */
156 /* use lpuart0 as system console */
157 uart = QIXIS_READ(brdcfg[13]);
158 uart &= ~CFG_LPUART_MUX_MASK;
159 uart |= CFG_LPUART_EN;
160 QIXIS_WRITE(brdcfg[13], uart);
161 #endif
162
163 return 0;
164 }
165
detail_board_ddr_info(void)166 void detail_board_ddr_info(void)
167 {
168 puts("\nDDR ");
169 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
170 print_ddr_info(0);
171 }
172
esdhc_status_fixup(void * blob,const char * compat)173 int esdhc_status_fixup(void *blob, const char *compat)
174 {
175 void __iomem *dcfg_ccsr = (void __iomem *)DCFG_BASE;
176 char esdhc1_path[] = "/soc/mmc@2140000";
177 char esdhc2_path[] = "/soc/mmc@2150000";
178 char dspi1_path[] = "/soc/spi@2100000";
179 char dspi2_path[] = "/soc/spi@2110000";
180 u32 mux_sdhc1, mux_sdhc2;
181 u32 io = 0;
182
183 /*
184 * The PMUX IO-expander for mux select is used to control
185 * the muxing of various onboard interfaces.
186 */
187
188 io = in_le32(dcfg_ccsr + DCFG_RCWSR12);
189 mux_sdhc1 = (io >> DCFG_RCWSR12_SDHC_SHIFT) & DCFG_RCWSR12_SDHC_MASK;
190
191 /* Disable esdhc1/dspi1 if not selected. */
192 if (mux_sdhc1 != 0)
193 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
194 sizeof("disabled"), 1);
195 if (mux_sdhc1 != 2)
196 do_fixup_by_path(blob, dspi1_path, "status", "disabled",
197 sizeof("disabled"), 1);
198
199 io = in_le32(dcfg_ccsr + DCFG_RCWSR13);
200 mux_sdhc2 = (io >> DCFG_RCWSR13_SDHC_SHIFT) & DCFG_RCWSR13_SDHC_MASK;
201
202 /* Disable esdhc2/dspi2 if not selected. */
203 if (mux_sdhc2 != 0)
204 do_fixup_by_path(blob, esdhc2_path, "status", "disabled",
205 sizeof("disabled"), 1);
206 if (mux_sdhc2 != 2)
207 do_fixup_by_path(blob, dspi2_path, "status", "disabled",
208 sizeof("disabled"), 1);
209
210 return 0;
211 }
212
213 #ifdef CONFIG_OF_BOARD_SETUP
ft_board_setup(void * blob,struct bd_info * bd)214 int ft_board_setup(void *blob, struct bd_info *bd)
215 {
216 u64 base[CONFIG_NR_DRAM_BANKS];
217 u64 size[CONFIG_NR_DRAM_BANKS];
218
219 ft_cpu_setup(blob, bd);
220
221 /* fixup DT for the two GPP DDR banks */
222 base[0] = gd->bd->bi_dram[0].start;
223 size[0] = gd->bd->bi_dram[0].size;
224 base[1] = gd->bd->bi_dram[1].start;
225 size[1] = gd->bd->bi_dram[1].size;
226
227 #ifdef CONFIG_RESV_RAM
228 /* reduce size if reserved memory is within this bank */
229 if (gd->arch.resv_ram >= base[0] &&
230 gd->arch.resv_ram < base[0] + size[0])
231 size[0] = gd->arch.resv_ram - base[0];
232 else if (gd->arch.resv_ram >= base[1] &&
233 gd->arch.resv_ram < base[1] + size[1])
234 size[1] = gd->arch.resv_ram - base[1];
235 #endif
236
237 fdt_fixup_memory_banks(blob, base, size, 2);
238
239 fdt_fixup_icid(blob);
240
241 #ifdef CONFIG_FSL_ENETC
242 fdt_fixup_enetc_mac(blob);
243 #endif
244
245 return 0;
246 }
247 #endif
248
249 #ifdef CONFIG_FSL_QIXIS
checkboard(void)250 int checkboard(void)
251 {
252 #ifdef CONFIG_TFABOOT
253 enum boot_src src = get_boot_src();
254 #endif
255 u8 sw;
256
257 int clock;
258 char *board;
259 char buf[64] = {0};
260 static const char *freq[6] = {"100.00", "125.00", "156.25",
261 "161.13", "322.26", "100.00 SS"};
262
263 cpu_name(buf);
264 /* find the board details */
265 sw = QIXIS_READ(id);
266
267 switch (sw) {
268 case 0x46:
269 board = "QDS";
270 break;
271 case 0x47:
272 board = "RDB";
273 break;
274 case 0x49:
275 board = "HSSI";
276 break;
277 default:
278 board = "unknown";
279 break;
280 }
281
282 sw = QIXIS_READ(arch);
283 printf("Board: %s-%s, Version: %c, boot from ",
284 buf, board, (sw & 0xf) + 'A' - 1);
285
286 sw = QIXIS_READ(brdcfg[0]);
287 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
288
289 #ifdef CONFIG_TFABOOT
290 if (src == BOOT_SOURCE_SD_MMC) {
291 puts("SD\n");
292 } else if (src == BOOT_SOURCE_SD_MMC2) {
293 puts("eMMC\n");
294 } else {
295 #endif
296 #ifdef CONFIG_SD_BOOT
297 puts("SD\n");
298 #elif defined(CONFIG_EMMC_BOOT)
299 puts("eMMC\n");
300 #else
301 switch (sw) {
302 case 0:
303 case 4:
304 printf("NOR\n");
305 break;
306 case 1:
307 printf("NAND\n");
308 break;
309 default:
310 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
311 break;
312 }
313 #endif
314 #ifdef CONFIG_TFABOOT
315 }
316 #endif
317
318 printf("FPGA: v%d (%s)\n", QIXIS_READ(scver), board);
319 puts("SERDES1 Reference : ");
320
321 sw = QIXIS_READ(brdcfg[2]);
322 #ifdef CONFIG_TARGET_LS1028ARDB
323 clock = (sw >> 6) & 3;
324 #else
325 clock = (sw >> 4) & 0xf;
326 #endif
327
328 printf("Clock1 = %sMHz ", freq[clock]);
329 #ifdef CONFIG_TARGET_LS1028ARDB
330 clock = (sw >> 4) & 3;
331 #else
332 clock = sw & 0xf;
333 #endif
334 printf("Clock2 = %sMHz\n", freq[clock]);
335
336 return 0;
337 }
338 #endif
339