1.. SPDX-License-Identifier: GPL-2.0+ 2.. sectionauthor:: Simon Glass <sjg@chromium.org> 3 4Chromebook Samus 5================ 6 7First, you need the following binary blobs: 8 9 * descriptor.bin - Intel flash descriptor 10 * me.bin - Intel Management Engine 11 * mrc.bin - Memory Reference Code, which sets up SDRAM 12 * refcode.elf - Additional Reference code 13 * vga.bin - video ROM, which sets up the display 14 15If you have a samus you can obtain them from your flash, for example, in 16developer mode on the Chromebook (use Ctrl-Alt-F2 to obtain a terminal and 17log in as 'root'):: 18 19 cd /tmp 20 flashrom -w samus.bin 21 scp samus.bin username@ip_address:/path/to/somewhere 22 23If not see the coreboot tree where you can use:: 24 25 bash crosfirmware.sh samus 26 27to get the image. There is also an 'extract_blobs.sh' scripts that you can use 28on the 'coreboot-Google_Samus.*' file to short-circuit some of the below. 29 30Then 'ifdtool -x samus.bin' on your development machine will produce:: 31 32 flashregion_0_flashdescriptor.bin 33 flashregion_1_bios.bin 34 flashregion_2_intel_me.bin 35 36Rename flashregion_0_flashdescriptor.bin to descriptor.bin 37Rename flashregion_2_intel_me.bin to me.bin 38You can ignore flashregion_1_bios.bin - it is not used. 39 40To get the rest, use 'cbfstool samus.bin print':: 41 42 samus.bin: 8192 kB, bootblocksize 2864, romsize 8388608, offset 0x700000 43 alignment: 64 bytes, architecture: x86 44 45============================ ======== =========== ====== 46Name Offset Type Size 47============================ ======== =========== ====== 48cmos_layout.bin 0x700000 cmos_layout 1164 49pci8086,0406.rom 0x7004c0 optionrom 65536 50spd.bin 0x710500 (unknown) 4096 51cpu_microcode_blob.bin 0x711540 microcode 70720 52fallback/romstage 0x722a00 stage 54210 53fallback/ramstage 0x72fe00 stage 96382 54config 0x7476c0 raw 6075 55fallback/vboot 0x748ec0 stage 15980 56fallback/refcode 0x74cd80 stage 75578 57fallback/payload 0x75f500 payload 62878 58u-boot.dtb 0x76eb00 (unknown) 5318 59(empty) 0x770000 null 196504 60mrc.bin 0x79ffc0 (unknown) 222876 61(empty) 0x7d66c0 null 167320 62============================ ======== =========== ====== 63 64You can extract what you need:: 65 66 cbfstool samus.bin extract -n pci8086,0406.rom -f vga.bin 67 cbfstool samus.bin extract -n fallback/refcode -f refcode.rmod 68 cbfstool samus.bin extract -n mrc.bin -f mrc.bin 69 cbfstool samus.bin extract -n fallback/refcode -f refcode.bin -U 70 71Note that the -U flag is only supported by the latest cbfstool. It unpacks 72and decompresses the stage to produce a coreboot rmodule. This is a simple 73representation of an ELF file. You need the patch "Support decoding a stage 74with compression". 75 76Put all 5 files into board/google/chromebook_samus. 77 78Now you can build U-Boot and obtain u-boot.rom:: 79 80 $ make chromebook_samus_defconfig 81 $ make all 82 83If you are using em100, then this command will flash write -Boot:: 84 85 em100 -s -d filename.rom -c W25Q64CV -r 86 87Flash map for samus / broadwell: 88 89 :fffff800: SYS_X86_START16 90 :ffff0000: RESET_SEG_START 91 :fffd8000: TPL_TEXT_BASE 92 :fffa0000: X86_MRC_ADDR 93 :fff90000: VGA_BIOS_ADDR 94 :ffed0000: SYS_TEXT_BASE 95 :ffea0000: X86_REFCODE_ADDR 96 :ffe70000: SPL_TEXT_BASE 97 :ffbf8000: CONFIG_ENV_OFFSET (environemnt offset) 98 :ffbe0000: rw-mrc-cache (Memory-reference-code cache) 99 :ffa00000: <spare> 100 :ff801000: intel-me (address set by descriptor.bin) 101 :ff800000: intel-descriptor 102