1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
4 * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
5 */
6
7 #define LOG_CATEGORY UCLASS_CLK
8
9 #include <common.h>
10 #include <clk-uclass.h>
11 #include <dm.h>
12 #include <log.h>
13 #include <regmap.h>
14 #include <syscon.h>
15 #include <asm/io.h>
16 #include <dm/device_compat.h>
17 #include <dm/root.h>
18 #include <linux/bitops.h>
19
20 #include <dt-bindings/clock/stm32h7-clks.h>
21
22 /* RCC CR specific definitions */
23 #define RCC_CR_HSION BIT(0)
24 #define RCC_CR_HSIRDY BIT(2)
25
26 #define RCC_CR_HSEON BIT(16)
27 #define RCC_CR_HSERDY BIT(17)
28 #define RCC_CR_HSEBYP BIT(18)
29 #define RCC_CR_PLL1ON BIT(24)
30 #define RCC_CR_PLL1RDY BIT(25)
31
32 #define RCC_CR_HSIDIV_MASK GENMASK(4, 3)
33 #define RCC_CR_HSIDIV_SHIFT 3
34
35 #define RCC_CFGR_SW_MASK GENMASK(2, 0)
36 #define RCC_CFGR_SW_HSI 0
37 #define RCC_CFGR_SW_CSI 1
38 #define RCC_CFGR_SW_HSE 2
39 #define RCC_CFGR_SW_PLL1 3
40 #define RCC_CFGR_TIMPRE BIT(15)
41
42 #define RCC_PLLCKSELR_PLLSRC_HSI 0
43 #define RCC_PLLCKSELR_PLLSRC_CSI 1
44 #define RCC_PLLCKSELR_PLLSRC_HSE 2
45 #define RCC_PLLCKSELR_PLLSRC_NO_CLK 3
46
47 #define RCC_PLLCKSELR_PLLSRC_MASK GENMASK(1, 0)
48
49 #define RCC_PLLCKSELR_DIVM1_SHIFT 4
50 #define RCC_PLLCKSELR_DIVM1_MASK GENMASK(9, 4)
51
52 #define RCC_PLL1DIVR_DIVN1_MASK GENMASK(8, 0)
53
54 #define RCC_PLL1DIVR_DIVP1_SHIFT 9
55 #define RCC_PLL1DIVR_DIVP1_MASK GENMASK(15, 9)
56
57 #define RCC_PLL1DIVR_DIVQ1_SHIFT 16
58 #define RCC_PLL1DIVR_DIVQ1_MASK GENMASK(22, 16)
59
60 #define RCC_PLL1DIVR_DIVR1_SHIFT 24
61 #define RCC_PLL1DIVR_DIVR1_MASK GENMASK(30, 24)
62
63 #define RCC_PLL1FRACR_FRACN1_SHIFT 3
64 #define RCC_PLL1FRACR_FRACN1_MASK GENMASK(15, 3)
65
66 #define RCC_PLLCFGR_PLL1RGE_SHIFT 2
67 #define PLL1RGE_1_2_MHZ 0
68 #define PLL1RGE_2_4_MHZ 1
69 #define PLL1RGE_4_8_MHZ 2
70 #define PLL1RGE_8_16_MHZ 3
71 #define RCC_PLLCFGR_DIVP1EN BIT(16)
72 #define RCC_PLLCFGR_DIVQ1EN BIT(17)
73 #define RCC_PLLCFGR_DIVR1EN BIT(18)
74
75 #define RCC_D1CFGR_HPRE_MASK GENMASK(3, 0)
76 #define RCC_D1CFGR_HPRE_DIVIDED BIT(3)
77 #define RCC_D1CFGR_HPRE_DIVIDER GENMASK(2, 0)
78
79 #define RCC_D1CFGR_HPRE_DIV2 8
80
81 #define RCC_D1CFGR_D1PPRE_SHIFT 4
82 #define RCC_D1CFGR_D1PPRE_DIVIDED BIT(6)
83 #define RCC_D1CFGR_D1PPRE_DIVIDER GENMASK(5, 4)
84
85 #define RCC_D1CFGR_D1CPRE_SHIFT 8
86 #define RCC_D1CFGR_D1CPRE_DIVIDER GENMASK(10, 8)
87 #define RCC_D1CFGR_D1CPRE_DIVIDED BIT(11)
88
89 #define RCC_D2CFGR_D2PPRE1_SHIFT 4
90 #define RCC_D2CFGR_D2PPRE1_DIVIDED BIT(6)
91 #define RCC_D2CFGR_D2PPRE1_DIVIDER GENMASK(5, 4)
92
93 #define RCC_D2CFGR_D2PPRE2_SHIFT 8
94 #define RCC_D2CFGR_D2PPRE2_DIVIDED BIT(10)
95 #define RCC_D2CFGR_D2PPRE2_DIVIDER GENMASK(9, 8)
96
97 #define RCC_D3CFGR_D3PPRE_SHIFT 4
98 #define RCC_D3CFGR_D3PPRE_DIVIDED BIT(6)
99 #define RCC_D3CFGR_D3PPRE_DIVIDER GENMASK(5, 4)
100
101 #define RCC_D1CCIPR_FMCSRC_MASK GENMASK(1, 0)
102 #define FMCSRC_HCLKD1 0
103 #define FMCSRC_PLL1_Q_CK 1
104 #define FMCSRC_PLL2_R_CK 2
105 #define FMCSRC_PER_CK 3
106
107 #define RCC_D1CCIPR_QSPISRC_MASK GENMASK(5, 4)
108 #define RCC_D1CCIPR_QSPISRC_SHIFT 4
109 #define QSPISRC_HCLKD1 0
110 #define QSPISRC_PLL1_Q_CK 1
111 #define QSPISRC_PLL2_R_CK 2
112 #define QSPISRC_PER_CK 3
113
114 #define PWR_CR3 0x0c
115 #define PWR_CR3_SCUEN BIT(2)
116 #define PWR_D3CR 0x18
117 #define PWR_D3CR_VOS_MASK GENMASK(15, 14)
118 #define PWR_D3CR_VOS_SHIFT 14
119 #define VOS_SCALE_3 1
120 #define VOS_SCALE_2 2
121 #define VOS_SCALE_1 3
122 #define PWR_D3CR_VOSREADY BIT(13)
123
124 struct stm32_rcc_regs {
125 u32 cr; /* 0x00 Source Control Register */
126 u32 icscr; /* 0x04 Internal Clock Source Calibration Register */
127 u32 crrcr; /* 0x08 Clock Recovery RC Register */
128 u32 reserved1; /* 0x0c reserved */
129 u32 cfgr; /* 0x10 Clock Configuration Register */
130 u32 reserved2; /* 0x14 reserved */
131 u32 d1cfgr; /* 0x18 Domain 1 Clock Configuration Register */
132 u32 d2cfgr; /* 0x1c Domain 2 Clock Configuration Register */
133 u32 d3cfgr; /* 0x20 Domain 3 Clock Configuration Register */
134 u32 reserved3; /* 0x24 reserved */
135 u32 pllckselr; /* 0x28 PLLs Clock Source Selection Register */
136 u32 pllcfgr; /* 0x2c PLLs Configuration Register */
137 u32 pll1divr; /* 0x30 PLL1 Dividers Configuration Register */
138 u32 pll1fracr; /* 0x34 PLL1 Fractional Divider Register */
139 u32 pll2divr; /* 0x38 PLL2 Dividers Configuration Register */
140 u32 pll2fracr; /* 0x3c PLL2 Fractional Divider Register */
141 u32 pll3divr; /* 0x40 PLL3 Dividers Configuration Register */
142 u32 pll3fracr; /* 0x44 PLL3 Fractional Divider Register */
143 u32 reserved4; /* 0x48 reserved */
144 u32 d1ccipr; /* 0x4c Domain 1 Kernel Clock Configuration Register */
145 u32 d2ccip1r; /* 0x50 Domain 2 Kernel Clock Configuration Register */
146 u32 d2ccip2r; /* 0x54 Domain 2 Kernel Clock Configuration Register */
147 u32 d3ccipr; /* 0x58 Domain 3 Kernel Clock Configuration Register */
148 u32 reserved5; /* 0x5c reserved */
149 u32 cier; /* 0x60 Clock Source Interrupt Enable Register */
150 u32 cifr; /* 0x64 Clock Source Interrupt Flag Register */
151 u32 cicr; /* 0x68 Clock Source Interrupt Clear Register */
152 u32 reserved6; /* 0x6c reserved */
153 u32 bdcr; /* 0x70 Backup Domain Control Register */
154 u32 csr; /* 0x74 Clock Control and Status Register */
155 u32 reserved7; /* 0x78 reserved */
156
157 u32 ahb3rstr; /* 0x7c AHB3 Peripheral Reset Register */
158 u32 ahb1rstr; /* 0x80 AHB1 Peripheral Reset Register */
159 u32 ahb2rstr; /* 0x84 AHB2 Peripheral Reset Register */
160 u32 ahb4rstr; /* 0x88 AHB4 Peripheral Reset Register */
161
162 u32 apb3rstr; /* 0x8c APB3 Peripheral Reset Register */
163 u32 apb1lrstr; /* 0x90 APB1 low Peripheral Reset Register */
164 u32 apb1hrstr; /* 0x94 APB1 high Peripheral Reset Register */
165 u32 apb2rstr; /* 0x98 APB2 Clock Register */
166 u32 apb4rstr; /* 0x9c APB4 Clock Register */
167
168 u32 gcr; /* 0xa0 Global Control Register */
169 u32 reserved8; /* 0xa4 reserved */
170 u32 d3amr; /* 0xa8 D3 Autonomous mode Register */
171 u32 reserved9[9];/* 0xac to 0xcc reserved */
172 u32 rsr; /* 0xd0 Reset Status Register */
173 u32 ahb3enr; /* 0xd4 AHB3 Clock Register */
174 u32 ahb1enr; /* 0xd8 AHB1 Clock Register */
175 u32 ahb2enr; /* 0xdc AHB2 Clock Register */
176 u32 ahb4enr; /* 0xe0 AHB4 Clock Register */
177
178 u32 apb3enr; /* 0xe4 APB3 Clock Register */
179 u32 apb1lenr; /* 0xe8 APB1 low Clock Register */
180 u32 apb1henr; /* 0xec APB1 high Clock Register */
181 u32 apb2enr; /* 0xf0 APB2 Clock Register */
182 u32 apb4enr; /* 0xf4 APB4 Clock Register */
183 };
184
185 #define RCC_AHB3ENR offsetof(struct stm32_rcc_regs, ahb3enr)
186 #define RCC_AHB1ENR offsetof(struct stm32_rcc_regs, ahb1enr)
187 #define RCC_AHB2ENR offsetof(struct stm32_rcc_regs, ahb2enr)
188 #define RCC_AHB4ENR offsetof(struct stm32_rcc_regs, ahb4enr)
189 #define RCC_APB3ENR offsetof(struct stm32_rcc_regs, apb3enr)
190 #define RCC_APB1LENR offsetof(struct stm32_rcc_regs, apb1lenr)
191 #define RCC_APB1HENR offsetof(struct stm32_rcc_regs, apb1henr)
192 #define RCC_APB2ENR offsetof(struct stm32_rcc_regs, apb2enr)
193 #define RCC_APB4ENR offsetof(struct stm32_rcc_regs, apb4enr)
194
195 struct clk_cfg {
196 u32 gate_offset;
197 u8 gate_bit_idx;
198 const char *name;
199 };
200
201 /*
202 * the way all these entries are sorted in this array could seem
203 * unlogical, but we are dependant of kernel DT_bindings,
204 * where clocks are separate in 2 banks, peripheral clocks and
205 * kernel clocks.
206 */
207
208 static const struct clk_cfg clk_map[] = {
209 {RCC_AHB3ENR, 31, "d1sram1"}, /* peripheral clocks */
210 {RCC_AHB3ENR, 30, "itcm"},
211 {RCC_AHB3ENR, 29, "dtcm2"},
212 {RCC_AHB3ENR, 28, "dtcm1"},
213 {RCC_AHB3ENR, 8, "flitf"},
214 {RCC_AHB3ENR, 5, "jpgdec"},
215 {RCC_AHB3ENR, 4, "dma2d"},
216 {RCC_AHB3ENR, 0, "mdma"},
217 {RCC_AHB1ENR, 28, "usb2ulpi"},
218 {RCC_AHB1ENR, 17, "eth1rx"},
219 {RCC_AHB1ENR, 16, "eth1tx"},
220 {RCC_AHB1ENR, 15, "eth1mac"},
221 {RCC_AHB1ENR, 14, "art"},
222 {RCC_AHB1ENR, 26, "usb1ulpi"},
223 {RCC_AHB1ENR, 1, "dma2"},
224 {RCC_AHB1ENR, 0, "dma1"},
225 {RCC_AHB2ENR, 31, "d2sram3"},
226 {RCC_AHB2ENR, 30, "d2sram2"},
227 {RCC_AHB2ENR, 29, "d2sram1"},
228 {RCC_AHB2ENR, 5, "hash"},
229 {RCC_AHB2ENR, 4, "crypt"},
230 {RCC_AHB2ENR, 0, "camitf"},
231 {RCC_AHB4ENR, 28, "bkpram"},
232 {RCC_AHB4ENR, 25, "hsem"},
233 {RCC_AHB4ENR, 21, "bdma"},
234 {RCC_AHB4ENR, 19, "crc"},
235 {RCC_AHB4ENR, 10, "gpiok"},
236 {RCC_AHB4ENR, 9, "gpioj"},
237 {RCC_AHB4ENR, 8, "gpioi"},
238 {RCC_AHB4ENR, 7, "gpioh"},
239 {RCC_AHB4ENR, 6, "gpiog"},
240 {RCC_AHB4ENR, 5, "gpiof"},
241 {RCC_AHB4ENR, 4, "gpioe"},
242 {RCC_AHB4ENR, 3, "gpiod"},
243 {RCC_AHB4ENR, 2, "gpioc"},
244 {RCC_AHB4ENR, 1, "gpiob"},
245 {RCC_AHB4ENR, 0, "gpioa"},
246 {RCC_APB3ENR, 6, "wwdg1"},
247 {RCC_APB1LENR, 29, "dac12"},
248 {RCC_APB1LENR, 11, "wwdg2"},
249 {RCC_APB1LENR, 8, "tim14"},
250 {RCC_APB1LENR, 7, "tim13"},
251 {RCC_APB1LENR, 6, "tim12"},
252 {RCC_APB1LENR, 5, "tim7"},
253 {RCC_APB1LENR, 4, "tim6"},
254 {RCC_APB1LENR, 3, "tim5"},
255 {RCC_APB1LENR, 2, "tim4"},
256 {RCC_APB1LENR, 1, "tim3"},
257 {RCC_APB1LENR, 0, "tim2"},
258 {RCC_APB1HENR, 5, "mdios"},
259 {RCC_APB1HENR, 4, "opamp"},
260 {RCC_APB1HENR, 1, "crs"},
261 {RCC_APB2ENR, 18, "tim17"},
262 {RCC_APB2ENR, 17, "tim16"},
263 {RCC_APB2ENR, 16, "tim15"},
264 {RCC_APB2ENR, 1, "tim8"},
265 {RCC_APB2ENR, 0, "tim1"},
266 {RCC_APB4ENR, 26, "tmpsens"},
267 {RCC_APB4ENR, 16, "rtcapb"},
268 {RCC_APB4ENR, 15, "vref"},
269 {RCC_APB4ENR, 14, "comp12"},
270 {RCC_APB4ENR, 1, "syscfg"},
271 {RCC_AHB3ENR, 16, "sdmmc1"}, /* kernel clocks */
272 {RCC_AHB3ENR, 14, "quadspi"},
273 {RCC_AHB3ENR, 12, "fmc"},
274 {RCC_AHB1ENR, 27, "usb2otg"},
275 {RCC_AHB1ENR, 25, "usb1otg"},
276 {RCC_AHB1ENR, 5, "adc12"},
277 {RCC_AHB2ENR, 9, "sdmmc2"},
278 {RCC_AHB2ENR, 6, "rng"},
279 {RCC_AHB4ENR, 24, "adc3"},
280 {RCC_APB3ENR, 4, "dsi"},
281 {RCC_APB3ENR, 3, "ltdc"},
282 {RCC_APB1LENR, 31, "usart8"},
283 {RCC_APB1LENR, 30, "usart7"},
284 {RCC_APB1LENR, 27, "hdmicec"},
285 {RCC_APB1LENR, 23, "i2c3"},
286 {RCC_APB1LENR, 22, "i2c2"},
287 {RCC_APB1LENR, 21, "i2c1"},
288 {RCC_APB1LENR, 20, "uart5"},
289 {RCC_APB1LENR, 19, "uart4"},
290 {RCC_APB1LENR, 18, "usart3"},
291 {RCC_APB1LENR, 17, "usart2"},
292 {RCC_APB1LENR, 16, "spdifrx"},
293 {RCC_APB1LENR, 15, "spi3"},
294 {RCC_APB1LENR, 14, "spi2"},
295 {RCC_APB1LENR, 9, "lptim1"},
296 {RCC_APB1HENR, 8, "fdcan"},
297 {RCC_APB1HENR, 2, "swp"},
298 {RCC_APB2ENR, 29, "hrtim"},
299 {RCC_APB2ENR, 28, "dfsdm1"},
300 {RCC_APB2ENR, 24, "sai3"},
301 {RCC_APB2ENR, 23, "sai2"},
302 {RCC_APB2ENR, 22, "sai1"},
303 {RCC_APB2ENR, 20, "spi5"},
304 {RCC_APB2ENR, 13, "spi4"},
305 {RCC_APB2ENR, 12, "spi1"},
306 {RCC_APB2ENR, 5, "usart6"},
307 {RCC_APB2ENR, 4, "usart1"},
308 {RCC_APB4ENR, 21, "sai4a"},
309 {RCC_APB4ENR, 21, "sai4b"},
310 {RCC_APB4ENR, 12, "lptim5"},
311 {RCC_APB4ENR, 11, "lptim4"},
312 {RCC_APB4ENR, 10, "lptim3"},
313 {RCC_APB4ENR, 9, "lptim2"},
314 {RCC_APB4ENR, 7, "i2c4"},
315 {RCC_APB4ENR, 5, "spi6"},
316 {RCC_APB4ENR, 3, "lpuart1"},
317 };
318
319 struct stm32_clk {
320 struct stm32_rcc_regs *rcc_base;
321 struct regmap *pwr_regmap;
322 };
323
324 struct pll_psc {
325 u8 divm;
326 u16 divn;
327 u8 divp;
328 u8 divq;
329 u8 divr;
330 };
331
332 /*
333 * OSC_HSE = 25 MHz
334 * VCO = 500MHz
335 * pll1_p = 250MHz / pll1_q = 250MHz pll1_r = 250Mhz
336 */
337 struct pll_psc sys_pll_psc = {
338 .divm = 4,
339 .divn = 80,
340 .divp = 2,
341 .divq = 2,
342 .divr = 2,
343 };
344
345 enum apb {
346 APB1,
347 APB2,
348 };
349
configure_clocks(struct udevice * dev)350 int configure_clocks(struct udevice *dev)
351 {
352 struct stm32_clk *priv = dev_get_priv(dev);
353 struct stm32_rcc_regs *regs = priv->rcc_base;
354 uint8_t *pwr_base = (uint8_t *)regmap_get_range(priv->pwr_regmap, 0);
355 uint32_t pllckselr = 0;
356 uint32_t pll1divr = 0;
357 uint32_t pllcfgr = 0;
358
359 /* Switch on HSI */
360 setbits_le32(®s->cr, RCC_CR_HSION);
361 while (!(readl(®s->cr) & RCC_CR_HSIRDY))
362 ;
363
364 /* Reset CFGR, now HSI is the default system clock */
365 writel(0, ®s->cfgr);
366
367 /* Set all kernel domain clock registers to reset value*/
368 writel(0x0, ®s->d1ccipr);
369 writel(0x0, ®s->d2ccip1r);
370 writel(0x0, ®s->d2ccip2r);
371
372 /* Set voltage scaling at scale 1 (1,15 - 1,26 Volts) */
373 clrsetbits_le32(pwr_base + PWR_D3CR, PWR_D3CR_VOS_MASK,
374 VOS_SCALE_1 << PWR_D3CR_VOS_SHIFT);
375 /* Lock supply configuration update */
376 clrbits_le32(pwr_base + PWR_CR3, PWR_CR3_SCUEN);
377 while (!(readl(pwr_base + PWR_D3CR) & PWR_D3CR_VOSREADY))
378 ;
379
380 /* disable HSE to configure it */
381 clrbits_le32(®s->cr, RCC_CR_HSEON);
382 while ((readl(®s->cr) & RCC_CR_HSERDY))
383 ;
384
385 /* clear HSE bypass and set it ON */
386 clrbits_le32(®s->cr, RCC_CR_HSEBYP);
387 /* Switch on HSE */
388 setbits_le32(®s->cr, RCC_CR_HSEON);
389 while (!(readl(®s->cr) & RCC_CR_HSERDY))
390 ;
391
392 /* pll setup, disable it */
393 clrbits_le32(®s->cr, RCC_CR_PLL1ON);
394 while ((readl(®s->cr) & RCC_CR_PLL1RDY))
395 ;
396
397 /* Select HSE as PLL clock source */
398 pllckselr |= RCC_PLLCKSELR_PLLSRC_HSE;
399 pllckselr |= sys_pll_psc.divm << RCC_PLLCKSELR_DIVM1_SHIFT;
400 writel(pllckselr, ®s->pllckselr);
401
402 pll1divr |= (sys_pll_psc.divr - 1) << RCC_PLL1DIVR_DIVR1_SHIFT;
403 pll1divr |= (sys_pll_psc.divq - 1) << RCC_PLL1DIVR_DIVQ1_SHIFT;
404 pll1divr |= (sys_pll_psc.divp - 1) << RCC_PLL1DIVR_DIVP1_SHIFT;
405 pll1divr |= (sys_pll_psc.divn - 1);
406 writel(pll1divr, ®s->pll1divr);
407
408 pllcfgr |= PLL1RGE_4_8_MHZ << RCC_PLLCFGR_PLL1RGE_SHIFT;
409 pllcfgr |= RCC_PLLCFGR_DIVP1EN;
410 pllcfgr |= RCC_PLLCFGR_DIVQ1EN;
411 pllcfgr |= RCC_PLLCFGR_DIVR1EN;
412 writel(pllcfgr, ®s->pllcfgr);
413
414 /* pll setup, enable it */
415 setbits_le32(®s->cr, RCC_CR_PLL1ON);
416
417 /* set HPRE (/2) DI clk --> 125MHz */
418 clrsetbits_le32(®s->d1cfgr, RCC_D1CFGR_HPRE_MASK,
419 RCC_D1CFGR_HPRE_DIV2);
420
421 /* select PLL1 as system clock source (sys_ck)*/
422 clrsetbits_le32(®s->cfgr, RCC_CFGR_SW_MASK, RCC_CFGR_SW_PLL1);
423 while ((readl(®s->cfgr) & RCC_CFGR_SW_MASK) != RCC_CFGR_SW_PLL1)
424 ;
425
426 /* sdram: use pll1_q as fmc_k clk */
427 clrsetbits_le32(®s->d1ccipr, RCC_D1CCIPR_FMCSRC_MASK,
428 FMCSRC_PLL1_Q_CK);
429
430 return 0;
431 }
432
stm32_get_HSI_divider(struct stm32_rcc_regs * regs)433 static u32 stm32_get_HSI_divider(struct stm32_rcc_regs *regs)
434 {
435 u32 divider;
436
437 /* get HSI divider value */
438 divider = readl(®s->cr) & RCC_CR_HSIDIV_MASK;
439 divider = divider >> RCC_CR_HSIDIV_SHIFT;
440
441 return divider;
442 };
443
444 enum pllsrc {
445 HSE,
446 LSE,
447 HSI,
448 CSI,
449 I2S,
450 TIMER,
451 PLLSRC_NB,
452 };
453
454 static const char * const pllsrc_name[PLLSRC_NB] = {
455 [HSE] = "clk-hse",
456 [LSE] = "clk-lse",
457 [HSI] = "clk-hsi",
458 [CSI] = "clk-csi",
459 [I2S] = "clk-i2s",
460 [TIMER] = "timer-clk"
461 };
462
stm32_get_rate(struct stm32_rcc_regs * regs,enum pllsrc pllsrc)463 static ulong stm32_get_rate(struct stm32_rcc_regs *regs, enum pllsrc pllsrc)
464 {
465 struct clk clk;
466 struct udevice *fixed_clock_dev = NULL;
467 u32 divider;
468 int ret;
469 const char *name = pllsrc_name[pllsrc];
470
471 log_debug("pllsrc name %s\n", name);
472
473 clk.id = 0;
474 ret = uclass_get_device_by_name(UCLASS_CLK, name, &fixed_clock_dev);
475 if (ret) {
476 log_err("Can't find clk %s (%d)", name, ret);
477 return 0;
478 }
479
480 ret = clk_request(fixed_clock_dev, &clk);
481 if (ret) {
482 log_err("Can't request %s clk (%d)", name, ret);
483 return 0;
484 }
485
486 divider = 0;
487 if (pllsrc == HSI)
488 divider = stm32_get_HSI_divider(regs);
489
490 log_debug("divider %d rate %ld\n", divider, clk_get_rate(&clk));
491
492 return clk_get_rate(&clk) >> divider;
493 };
494
495 enum pll1_output {
496 PLL1_P_CK,
497 PLL1_Q_CK,
498 PLL1_R_CK,
499 };
500
stm32_get_PLL1_rate(struct stm32_rcc_regs * regs,enum pll1_output output)501 static u32 stm32_get_PLL1_rate(struct stm32_rcc_regs *regs,
502 enum pll1_output output)
503 {
504 ulong pllsrc = 0;
505 u32 divm1, divn1, divp1, divq1, divr1, fracn1;
506 ulong vco, rate;
507
508 /* get the PLLSRC */
509 switch (readl(®s->pllckselr) & RCC_PLLCKSELR_PLLSRC_MASK) {
510 case RCC_PLLCKSELR_PLLSRC_HSI:
511 pllsrc = stm32_get_rate(regs, HSI);
512 break;
513 case RCC_PLLCKSELR_PLLSRC_CSI:
514 pllsrc = stm32_get_rate(regs, CSI);
515 break;
516 case RCC_PLLCKSELR_PLLSRC_HSE:
517 pllsrc = stm32_get_rate(regs, HSE);
518 break;
519 case RCC_PLLCKSELR_PLLSRC_NO_CLK:
520 /* shouldn't happen */
521 log_err("wrong value for RCC_PLLCKSELR register\n");
522 pllsrc = 0;
523 break;
524 }
525
526 /* pllsrc = 0 ? no need to go ahead */
527 if (!pllsrc)
528 return pllsrc;
529
530 /* get divm1, divp1, divn1 and divr1 */
531 divm1 = readl(®s->pllckselr) & RCC_PLLCKSELR_DIVM1_MASK;
532 divm1 = divm1 >> RCC_PLLCKSELR_DIVM1_SHIFT;
533
534 divn1 = (readl(®s->pll1divr) & RCC_PLL1DIVR_DIVN1_MASK) + 1;
535
536 divp1 = readl(®s->pll1divr) & RCC_PLL1DIVR_DIVP1_MASK;
537 divp1 = (divp1 >> RCC_PLL1DIVR_DIVP1_SHIFT) + 1;
538
539 divq1 = readl(®s->pll1divr) & RCC_PLL1DIVR_DIVQ1_MASK;
540 divq1 = (divq1 >> RCC_PLL1DIVR_DIVQ1_SHIFT) + 1;
541
542 divr1 = readl(®s->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK;
543 divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1;
544
545 fracn1 = readl(®s->pll1fracr) & RCC_PLL1DIVR_DIVR1_MASK;
546 fracn1 = fracn1 & RCC_PLL1DIVR_DIVR1_SHIFT;
547
548 vco = (pllsrc / divm1) * divn1;
549 rate = (pllsrc * fracn1) / (divm1 * 8192);
550
551 log_debug("divm1 = %d divn1 = %d divp1 = %d divq1 = %d divr1 = %d\n",
552 divm1, divn1, divp1, divq1, divr1);
553 log_debug("fracn1 = %d vco = %ld rate = %ld\n",
554 fracn1, vco, rate);
555
556 switch (output) {
557 case PLL1_P_CK:
558 return (vco + rate) / divp1;
559 break;
560 case PLL1_Q_CK:
561 return (vco + rate) / divq1;
562 break;
563
564 case PLL1_R_CK:
565 return (vco + rate) / divr1;
566 break;
567 }
568
569 return -EINVAL;
570 }
571
stm32_get_apb_psc(struct stm32_rcc_regs * regs,enum apb apb)572 static u32 stm32_get_apb_psc(struct stm32_rcc_regs *regs, enum apb apb)
573 {
574 u16 prescaler_table[8] = {2, 4, 8, 16, 64, 128, 256, 512};
575 u32 d2cfgr = readl(®s->d2cfgr);
576
577 if (apb == APB1) {
578 if (d2cfgr & RCC_D2CFGR_D2PPRE1_DIVIDED)
579 /* get D2 domain APB1 prescaler */
580 return prescaler_table[
581 ((d2cfgr & RCC_D2CFGR_D2PPRE1_DIVIDER)
582 >> RCC_D2CFGR_D2PPRE1_SHIFT)];
583 } else { /* APB2 */
584 if (d2cfgr & RCC_D2CFGR_D2PPRE2_DIVIDED)
585 /* get D2 domain APB2 prescaler */
586 return prescaler_table[
587 ((d2cfgr & RCC_D2CFGR_D2PPRE2_DIVIDER)
588 >> RCC_D2CFGR_D2PPRE2_SHIFT)];
589 }
590
591 return 1;
592 };
593
stm32_get_timer_rate(struct stm32_clk * priv,u32 sysclk,enum apb apb)594 static u32 stm32_get_timer_rate(struct stm32_clk *priv, u32 sysclk,
595 enum apb apb)
596 {
597 struct stm32_rcc_regs *regs = priv->rcc_base;
598 u32 psc = stm32_get_apb_psc(regs, apb);
599
600 if (readl(®s->cfgr) & RCC_CFGR_TIMPRE)
601 /*
602 * if APB prescaler is configured to a
603 * division factor of 1, 2 or 4
604 */
605 switch (psc) {
606 case 1:
607 case 2:
608 case 4:
609 return sysclk;
610 case 8:
611 return sysclk / 2;
612 case 16:
613 return sysclk / 4;
614 default:
615 log_err("unexpected prescaler value (%d)\n", psc);
616 return 0;
617 }
618 else
619 switch (psc) {
620 case 1:
621 return sysclk;
622 case 2:
623 case 4:
624 case 8:
625 case 16:
626 return sysclk / psc;
627 default:
628 log_err("unexpected prescaler value (%d)\n", psc);
629 return 0;
630 }
631 };
632
stm32_clk_get_rate(struct clk * clk)633 static ulong stm32_clk_get_rate(struct clk *clk)
634 {
635 struct stm32_clk *priv = dev_get_priv(clk->dev);
636 struct stm32_rcc_regs *regs = priv->rcc_base;
637 ulong sysclk = 0;
638 u32 gate_offset;
639 u32 d1cfgr, d3cfgr;
640 /* prescaler table lookups for clock computation */
641 u16 prescaler_table[8] = {2, 4, 8, 16, 64, 128, 256, 512};
642 u8 source, idx;
643
644 /*
645 * get system clock (sys_ck) source
646 * can be HSI_CK, CSI_CK, HSE_CK or pll1_p_ck
647 */
648 source = readl(®s->cfgr) & RCC_CFGR_SW_MASK;
649 switch (source) {
650 case RCC_CFGR_SW_PLL1:
651 sysclk = stm32_get_PLL1_rate(regs, PLL1_P_CK);
652 break;
653 case RCC_CFGR_SW_HSE:
654 sysclk = stm32_get_rate(regs, HSE);
655 break;
656
657 case RCC_CFGR_SW_CSI:
658 sysclk = stm32_get_rate(regs, CSI);
659 break;
660
661 case RCC_CFGR_SW_HSI:
662 sysclk = stm32_get_rate(regs, HSI);
663 break;
664 }
665
666 /* sysclk = 0 ? no need to go ahead */
667 if (!sysclk)
668 return sysclk;
669
670 dev_dbg(clk->dev, "system clock: source = %d freq = %ld\n",
671 source, sysclk);
672
673 d1cfgr = readl(®s->d1cfgr);
674
675 if (d1cfgr & RCC_D1CFGR_D1CPRE_DIVIDED) {
676 /* get D1 domain Core prescaler */
677 idx = (d1cfgr & RCC_D1CFGR_D1CPRE_DIVIDER) >>
678 RCC_D1CFGR_D1CPRE_SHIFT;
679 sysclk = sysclk / prescaler_table[idx];
680 }
681
682 if (d1cfgr & RCC_D1CFGR_HPRE_DIVIDED) {
683 /* get D1 domain AHB prescaler */
684 idx = d1cfgr & RCC_D1CFGR_HPRE_DIVIDER;
685 sysclk = sysclk / prescaler_table[idx];
686 }
687
688 gate_offset = clk_map[clk->id].gate_offset;
689
690 dev_dbg(clk->dev, "clk->id=%ld gate_offset=0x%x sysclk=%ld\n",
691 clk->id, gate_offset, sysclk);
692
693 switch (gate_offset) {
694 case RCC_AHB3ENR:
695 case RCC_AHB1ENR:
696 case RCC_AHB2ENR:
697 case RCC_AHB4ENR:
698 return sysclk;
699 break;
700
701 case RCC_APB3ENR:
702 if (d1cfgr & RCC_D1CFGR_D1PPRE_DIVIDED) {
703 /* get D1 domain APB3 prescaler */
704 idx = (d1cfgr & RCC_D1CFGR_D1PPRE_DIVIDER) >>
705 RCC_D1CFGR_D1PPRE_SHIFT;
706 sysclk = sysclk / prescaler_table[idx];
707 }
708
709 dev_dbg(clk->dev, "system clock: freq after APB3 prescaler = %ld\n",
710 sysclk);
711
712 return sysclk;
713 break;
714
715 case RCC_APB4ENR:
716 d3cfgr = readl(®s->d3cfgr);
717 if (d3cfgr & RCC_D3CFGR_D3PPRE_DIVIDED) {
718 /* get D3 domain APB4 prescaler */
719 idx = (d3cfgr & RCC_D3CFGR_D3PPRE_DIVIDER) >>
720 RCC_D3CFGR_D3PPRE_SHIFT;
721 sysclk = sysclk / prescaler_table[idx];
722 }
723
724 dev_dbg(clk->dev,
725 "system clock: freq after APB4 prescaler = %ld\n",
726 sysclk);
727
728 return sysclk;
729 break;
730
731 case RCC_APB1LENR:
732 case RCC_APB1HENR:
733 /* special case for GPT timers */
734 switch (clk->id) {
735 case TIM14_CK:
736 case TIM13_CK:
737 case TIM12_CK:
738 case TIM7_CK:
739 case TIM6_CK:
740 case TIM5_CK:
741 case TIM4_CK:
742 case TIM3_CK:
743 case TIM2_CK:
744 return stm32_get_timer_rate(priv, sysclk, APB1);
745 }
746
747 dev_dbg(clk->dev,
748 "system clock: freq after APB1 prescaler = %ld\n",
749 sysclk);
750
751 return (sysclk / stm32_get_apb_psc(regs, APB1));
752 break;
753
754 case RCC_APB2ENR:
755 /* special case for timers */
756 switch (clk->id) {
757 case TIM17_CK:
758 case TIM16_CK:
759 case TIM15_CK:
760 case TIM8_CK:
761 case TIM1_CK:
762 return stm32_get_timer_rate(priv, sysclk, APB2);
763 }
764
765 dev_dbg(clk->dev,
766 "system clock: freq after APB2 prescaler = %ld\n",
767 sysclk);
768
769 return (sysclk / stm32_get_apb_psc(regs, APB2));
770
771 break;
772
773 default:
774 dev_err(clk->dev, "unexpected gate_offset value (0x%x)\n",
775 gate_offset);
776 return -EINVAL;
777 break;
778 }
779 }
780
stm32_clk_enable(struct clk * clk)781 static int stm32_clk_enable(struct clk *clk)
782 {
783 struct stm32_clk *priv = dev_get_priv(clk->dev);
784 struct stm32_rcc_regs *regs = priv->rcc_base;
785 u32 gate_offset;
786 u32 gate_bit_index;
787 unsigned long clk_id = clk->id;
788
789 gate_offset = clk_map[clk_id].gate_offset;
790 gate_bit_index = clk_map[clk_id].gate_bit_idx;
791
792 dev_dbg(clk->dev, "clkid=%ld gate offset=0x%x bit_index=%d name=%s\n",
793 clk->id, gate_offset, gate_bit_index,
794 clk_map[clk_id].name);
795
796 setbits_le32(®s->cr + (gate_offset / 4), BIT(gate_bit_index));
797
798 return 0;
799 }
800
stm32_clk_probe(struct udevice * dev)801 static int stm32_clk_probe(struct udevice *dev)
802 {
803 struct stm32_clk *priv = dev_get_priv(dev);
804 struct udevice *syscon;
805 fdt_addr_t addr;
806 int err;
807
808 addr = dev_read_addr(dev);
809 if (addr == FDT_ADDR_T_NONE)
810 return -EINVAL;
811
812 priv->rcc_base = (struct stm32_rcc_regs *)addr;
813
814 /* get corresponding syscon phandle */
815 err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
816 "st,syscfg", &syscon);
817
818 if (err) {
819 dev_err(dev, "unable to find syscon device\n");
820 return err;
821 }
822
823 priv->pwr_regmap = syscon_get_regmap(syscon);
824 if (!priv->pwr_regmap) {
825 dev_err(dev, "unable to find regmap\n");
826 return -ENODEV;
827 }
828
829 configure_clocks(dev);
830
831 return 0;
832 }
833
stm32_clk_of_xlate(struct clk * clk,struct ofnode_phandle_args * args)834 static int stm32_clk_of_xlate(struct clk *clk,
835 struct ofnode_phandle_args *args)
836 {
837 if (args->args_count != 1) {
838 dev_dbg(clk->dev, "Invaild args_count: %d\n", args->args_count);
839 return -EINVAL;
840 }
841
842 if (args->args_count) {
843 clk->id = args->args[0];
844 /*
845 * this computation convert DT clock index which is used to
846 * point into 2 separate clock arrays (peripheral and kernel
847 * clocks bank) (see include/dt-bindings/clock/stm32h7-clks.h)
848 * into index to point into only one array where peripheral
849 * and kernel clocks are consecutive
850 */
851 if (clk->id >= KERN_BANK) {
852 clk->id -= KERN_BANK;
853 clk->id += LAST_PERIF_BANK - PERIF_BANK + 1;
854 } else {
855 clk->id -= PERIF_BANK;
856 }
857 } else {
858 clk->id = 0;
859 }
860
861 dev_dbg(clk->dev, "clk->id %ld\n", clk->id);
862
863 return 0;
864 }
865
866 static struct clk_ops stm32_clk_ops = {
867 .of_xlate = stm32_clk_of_xlate,
868 .enable = stm32_clk_enable,
869 .get_rate = stm32_clk_get_rate,
870 };
871
872 U_BOOT_DRIVER(stm32h7_clk) = {
873 .name = "stm32h7_rcc_clock",
874 .id = UCLASS_CLK,
875 .ops = &stm32_clk_ops,
876 .probe = stm32_clk_probe,
877 .priv_auto = sizeof(struct stm32_clk),
878 .flags = DM_FLAG_PRE_RELOC,
879 };
880