1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * spi driver for rockchip
4 *
5 * (C) 2019 Theobroma Systems Design und Consulting GmbH
6 *
7 * (C) Copyright 2015 Google, Inc
8 *
9 * (C) Copyright 2008-2013 Rockchip Electronics
10 * Peter, Software Engineering, <superpeter.cai@gmail.com>.
11 */
12
13 #include <common.h>
14 #include <clk.h>
15 #include <dm.h>
16 #include <dt-structs.h>
17 #include <errno.h>
18 #include <log.h>
19 #include <spi.h>
20 #include <time.h>
21 #include <linux/delay.h>
22 #include <linux/errno.h>
23 #include <asm/io.h>
24 #include <asm/arch-rockchip/clock.h>
25 #include <asm/arch-rockchip/periph.h>
26 #include <dm/pinctrl.h>
27 #include "rk_spi.h"
28
29 /* Change to 1 to output registers at the start of each transaction */
30 #define DEBUG_RK_SPI 0
31
32 /*
33 * ctrlr1 is 16-bits, so we should support lengths of 0xffff + 1. However,
34 * the controller seems to hang when given 0x10000, so stick with this for now.
35 */
36 #define ROCKCHIP_SPI_MAX_TRANLEN 0xffff
37
38 struct rockchip_spi_params {
39 /* RXFIFO overruns and TXFIFO underruns stop the master clock */
40 bool master_manages_fifo;
41 };
42
43 struct rockchip_spi_plat {
44 #if CONFIG_IS_ENABLED(OF_PLATDATA)
45 struct dtd_rockchip_rk3288_spi of_plat;
46 #endif
47 s32 frequency; /* Default clock frequency, -1 for none */
48 fdt_addr_t base;
49 uint deactivate_delay_us; /* Delay to wait after deactivate */
50 uint activate_delay_us; /* Delay to wait after activate */
51 };
52
53 struct rockchip_spi_priv {
54 struct rockchip_spi *regs;
55 struct clk clk;
56 unsigned int max_freq;
57 unsigned int mode;
58 ulong last_transaction_us; /* Time of last transaction end */
59 unsigned int speed_hz;
60 unsigned int last_speed_hz;
61 uint input_rate;
62 };
63
64 #define SPI_FIFO_DEPTH 32
65
rkspi_dump_regs(struct rockchip_spi * regs)66 static void rkspi_dump_regs(struct rockchip_spi *regs)
67 {
68 debug("ctrl0: \t\t0x%08x\n", readl(®s->ctrlr0));
69 debug("ctrl1: \t\t0x%08x\n", readl(®s->ctrlr1));
70 debug("ssienr: \t\t0x%08x\n", readl(®s->enr));
71 debug("ser: \t\t0x%08x\n", readl(®s->ser));
72 debug("baudr: \t\t0x%08x\n", readl(®s->baudr));
73 debug("txftlr: \t\t0x%08x\n", readl(®s->txftlr));
74 debug("rxftlr: \t\t0x%08x\n", readl(®s->rxftlr));
75 debug("txflr: \t\t0x%08x\n", readl(®s->txflr));
76 debug("rxflr: \t\t0x%08x\n", readl(®s->rxflr));
77 debug("sr: \t\t0x%08x\n", readl(®s->sr));
78 debug("imr: \t\t0x%08x\n", readl(®s->imr));
79 debug("isr: \t\t0x%08x\n", readl(®s->isr));
80 debug("dmacr: \t\t0x%08x\n", readl(®s->dmacr));
81 debug("dmatdlr: \t0x%08x\n", readl(®s->dmatdlr));
82 debug("dmardlr: \t0x%08x\n", readl(®s->dmardlr));
83 }
84
rkspi_enable_chip(struct rockchip_spi * regs,bool enable)85 static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable)
86 {
87 writel(enable ? 1 : 0, ®s->enr);
88 }
89
rkspi_set_clk(struct rockchip_spi_priv * priv,uint speed)90 static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
91 {
92 /*
93 * We should try not to exceed the speed requested by the caller:
94 * when selecting a divider, we need to make sure we round up.
95 */
96 uint clk_div = DIV_ROUND_UP(priv->input_rate, speed);
97
98 /* The baudrate register (BAUDR) is defined as a 32bit register where
99 * the upper 16bit are reserved and having 'Fsclk_out' in the lower
100 * 16bits with 'Fsclk_out' defined as follows:
101 *
102 * Fsclk_out = Fspi_clk/ SCKDV
103 * Where SCKDV is any even value between 2 and 65534.
104 */
105 if (clk_div > 0xfffe) {
106 clk_div = 0xfffe;
107 debug("%s: can't divide down to %d Hz (actual will be %d Hz)\n",
108 __func__, speed, priv->input_rate / clk_div);
109 }
110
111 /* Round up to the next even 16bit number */
112 clk_div = (clk_div + 1) & 0xfffe;
113
114 debug("spi speed %u, div %u\n", speed, clk_div);
115
116 clrsetbits_le32(&priv->regs->baudr, 0xffff, clk_div);
117 priv->last_speed_hz = speed;
118 }
119
rkspi_wait_till_not_busy(struct rockchip_spi * regs)120 static int rkspi_wait_till_not_busy(struct rockchip_spi *regs)
121 {
122 unsigned long start;
123
124 start = get_timer(0);
125 while (readl(®s->sr) & SR_BUSY) {
126 if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) {
127 debug("RK SPI: Status keeps busy for 1000us after a read/write!\n");
128 return -ETIMEDOUT;
129 }
130 }
131
132 return 0;
133 }
134
spi_cs_activate(struct udevice * dev,uint cs)135 static void spi_cs_activate(struct udevice *dev, uint cs)
136 {
137 struct udevice *bus = dev->parent;
138 struct rockchip_spi_plat *plat = dev_get_plat(bus);
139 struct rockchip_spi_priv *priv = dev_get_priv(bus);
140 struct rockchip_spi *regs = priv->regs;
141
142 /* If it's too soon to do another transaction, wait */
143 if (plat->deactivate_delay_us && priv->last_transaction_us) {
144 ulong delay_us; /* The delay completed so far */
145 delay_us = timer_get_us() - priv->last_transaction_us;
146 if (delay_us < plat->deactivate_delay_us) {
147 ulong additional_delay_us =
148 plat->deactivate_delay_us - delay_us;
149 debug("%s: delaying by %ld us\n",
150 __func__, additional_delay_us);
151 udelay(additional_delay_us);
152 }
153 }
154
155 debug("activate cs%u\n", cs);
156 writel(1 << cs, ®s->ser);
157 if (plat->activate_delay_us)
158 udelay(plat->activate_delay_us);
159 }
160
spi_cs_deactivate(struct udevice * dev,uint cs)161 static void spi_cs_deactivate(struct udevice *dev, uint cs)
162 {
163 struct udevice *bus = dev->parent;
164 struct rockchip_spi_plat *plat = dev_get_plat(bus);
165 struct rockchip_spi_priv *priv = dev_get_priv(bus);
166 struct rockchip_spi *regs = priv->regs;
167
168 debug("deactivate cs%u\n", cs);
169 writel(0, ®s->ser);
170
171 /* Remember time of this transaction so we can honour the bus delay */
172 if (plat->deactivate_delay_us)
173 priv->last_transaction_us = timer_get_us();
174 }
175
176 #if CONFIG_IS_ENABLED(OF_PLATDATA)
conv_of_plat(struct udevice * dev)177 static int conv_of_plat(struct udevice *dev)
178 {
179 struct rockchip_spi_plat *plat = dev_get_plat(dev);
180 struct dtd_rockchip_rk3288_spi *dtplat = &plat->of_plat;
181 struct rockchip_spi_priv *priv = dev_get_priv(dev);
182 int ret;
183
184 plat->base = dtplat->reg[0];
185 plat->frequency = 20000000;
186 ret = clk_get_by_driver_info(dev, dtplat->clocks, &priv->clk);
187 if (ret < 0)
188 return ret;
189
190 return 0;
191 }
192 #endif
193
rockchip_spi_of_to_plat(struct udevice * bus)194 static int rockchip_spi_of_to_plat(struct udevice *bus)
195 {
196 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
197 struct rockchip_spi_plat *plat = dev_get_plat(bus);
198 struct rockchip_spi_priv *priv = dev_get_priv(bus);
199 int ret;
200
201 plat->base = dev_read_addr(bus);
202
203 ret = clk_get_by_index(bus, 0, &priv->clk);
204 if (ret < 0) {
205 debug("%s: Could not get clock for %s: %d\n", __func__,
206 bus->name, ret);
207 return ret;
208 }
209
210 plat->frequency =
211 dev_read_u32_default(bus, "spi-max-frequency", 50000000);
212 plat->deactivate_delay_us =
213 dev_read_u32_default(bus, "spi-deactivate-delay", 0);
214 plat->activate_delay_us =
215 dev_read_u32_default(bus, "spi-activate-delay", 0);
216
217 debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
218 __func__, (uint)plat->base, plat->frequency,
219 plat->deactivate_delay_us);
220 #endif
221
222 return 0;
223 }
224
rockchip_spi_calc_modclk(ulong max_freq)225 static int rockchip_spi_calc_modclk(ulong max_freq)
226 {
227 /*
228 * While this is not strictly correct for the RK3368, as the
229 * GPLL will be 576MHz, things will still work, as the
230 * clk_set_rate(...) implementation in our clock-driver will
231 * chose the next closest rate not exceeding what we request
232 * based on the output of this function.
233 */
234
235 unsigned div;
236 const unsigned long gpll_hz = 594000000UL;
237
238 /*
239 * We need to find an input clock that provides at least twice
240 * the maximum frequency and can be generated from the assumed
241 * speed of GPLL (594MHz) using an integer divider.
242 *
243 * To give us more achievable bitrates at higher speeds (these
244 * are generated by dividing by an even 16-bit integer from
245 * this frequency), we try to have an input frequency of at
246 * least 4x our max_freq.
247 */
248
249 div = DIV_ROUND_UP(gpll_hz, max_freq * 4);
250 return gpll_hz / div;
251 }
252
rockchip_spi_probe(struct udevice * bus)253 static int rockchip_spi_probe(struct udevice *bus)
254 {
255 struct rockchip_spi_plat *plat = dev_get_plat(bus);
256 struct rockchip_spi_priv *priv = dev_get_priv(bus);
257 int ret;
258
259 debug("%s: probe\n", __func__);
260 #if CONFIG_IS_ENABLED(OF_PLATDATA)
261 ret = conv_of_plat(bus);
262 if (ret)
263 return ret;
264 #endif
265 priv->regs = (struct rockchip_spi *)plat->base;
266
267 priv->last_transaction_us = timer_get_us();
268 priv->max_freq = plat->frequency;
269
270 /* Clamp the value from the DTS against any hardware limits */
271 if (priv->max_freq > ROCKCHIP_SPI_MAX_RATE)
272 priv->max_freq = ROCKCHIP_SPI_MAX_RATE;
273
274 /* Find a module-input clock that fits with the max_freq setting */
275 ret = clk_set_rate(&priv->clk,
276 rockchip_spi_calc_modclk(priv->max_freq));
277 if (ret < 0) {
278 debug("%s: Failed to set clock: %d\n", __func__, ret);
279 return ret;
280 }
281 priv->input_rate = ret;
282 debug("%s: rate = %u\n", __func__, priv->input_rate);
283
284 return 0;
285 }
286
rockchip_spi_claim_bus(struct udevice * dev)287 static int rockchip_spi_claim_bus(struct udevice *dev)
288 {
289 struct udevice *bus = dev->parent;
290 struct rockchip_spi_priv *priv = dev_get_priv(bus);
291 struct rockchip_spi *regs = priv->regs;
292 uint ctrlr0;
293
294 /* Disable the SPI hardware */
295 rkspi_enable_chip(regs, false);
296
297 if (priv->speed_hz != priv->last_speed_hz)
298 rkspi_set_clk(priv, priv->speed_hz);
299
300 /* Operation Mode */
301 ctrlr0 = OMOD_MASTER << OMOD_SHIFT;
302
303 /* Data Frame Size */
304 ctrlr0 |= DFS_8BIT << DFS_SHIFT;
305
306 /* set SPI mode 0..3 */
307 if (priv->mode & SPI_CPOL)
308 ctrlr0 |= SCOL_HIGH << SCOL_SHIFT;
309 if (priv->mode & SPI_CPHA)
310 ctrlr0 |= SCPH_TOGSTA << SCPH_SHIFT;
311
312 /* Chip Select Mode */
313 ctrlr0 |= CSM_KEEP << CSM_SHIFT;
314
315 /* SSN to Sclk_out delay */
316 ctrlr0 |= SSN_DELAY_ONE << SSN_DELAY_SHIFT;
317
318 /* Serial Endian Mode */
319 ctrlr0 |= SEM_LITTLE << SEM_SHIFT;
320
321 /* First Bit Mode */
322 ctrlr0 |= FBM_MSB << FBM_SHIFT;
323
324 /* Byte and Halfword Transform */
325 ctrlr0 |= HALF_WORD_OFF << HALF_WORD_TX_SHIFT;
326
327 /* Rxd Sample Delay */
328 ctrlr0 |= 0 << RXDSD_SHIFT;
329
330 /* Frame Format */
331 ctrlr0 |= FRF_SPI << FRF_SHIFT;
332
333 /* Tx and Rx mode */
334 ctrlr0 |= TMOD_TR << TMOD_SHIFT;
335
336 writel(ctrlr0, ®s->ctrlr0);
337
338 return 0;
339 }
340
rockchip_spi_release_bus(struct udevice * dev)341 static int rockchip_spi_release_bus(struct udevice *dev)
342 {
343 struct udevice *bus = dev->parent;
344 struct rockchip_spi_priv *priv = dev_get_priv(bus);
345
346 rkspi_enable_chip(priv->regs, false);
347
348 return 0;
349 }
350
rockchip_spi_16bit_reader(struct udevice * dev,u8 ** din,int * len)351 static inline int rockchip_spi_16bit_reader(struct udevice *dev,
352 u8 **din, int *len)
353 {
354 struct udevice *bus = dev->parent;
355 const struct rockchip_spi_params * const data =
356 (void *)dev_get_driver_data(bus);
357 struct rockchip_spi_priv *priv = dev_get_priv(bus);
358 struct rockchip_spi *regs = priv->regs;
359 const u32 saved_ctrlr0 = readl(®s->ctrlr0);
360 #if defined(DEBUG)
361 u32 statistics_rxlevels[33] = { };
362 #endif
363 u32 frames = *len / 2;
364 u8 *in = (u8 *)(*din);
365 u32 max_chunk_size = SPI_FIFO_DEPTH;
366
367 if (!frames)
368 return 0;
369
370 /*
371 * If we know that the hardware will manage RXFIFO overruns
372 * (i.e. stop the SPI clock until there's space in the FIFO),
373 * we the allow largest possible chunk size that can be
374 * represented in CTRLR1.
375 */
376 if (data && data->master_manages_fifo)
377 max_chunk_size = ROCKCHIP_SPI_MAX_TRANLEN;
378
379 // rockchip_spi_configure(dev, mode, size)
380 rkspi_enable_chip(regs, false);
381 clrsetbits_le32(®s->ctrlr0,
382 TMOD_MASK << TMOD_SHIFT,
383 TMOD_RO << TMOD_SHIFT);
384 /* 16bit data frame size */
385 clrsetbits_le32(®s->ctrlr0, DFS_MASK, DFS_16BIT);
386
387 /* Update caller's context */
388 const u32 bytes_to_process = 2 * frames;
389 *din += bytes_to_process;
390 *len -= bytes_to_process;
391
392 /* Process our frames */
393 while (frames) {
394 u32 chunk_size = min(frames, max_chunk_size);
395
396 frames -= chunk_size;
397
398 writew(chunk_size - 1, ®s->ctrlr1);
399 rkspi_enable_chip(regs, true);
400
401 do {
402 u32 rx_level = readw(®s->rxflr);
403 #if defined(DEBUG)
404 statistics_rxlevels[rx_level]++;
405 #endif
406 chunk_size -= rx_level;
407 while (rx_level--) {
408 u16 val = readw(regs->rxdr);
409 *in++ = val & 0xff;
410 *in++ = val >> 8;
411 }
412 } while (chunk_size);
413
414 rkspi_enable_chip(regs, false);
415 }
416
417 #if defined(DEBUG)
418 debug("%s: observed rx_level during processing:\n", __func__);
419 for (int i = 0; i <= 32; ++i)
420 if (statistics_rxlevels[i])
421 debug("\t%2d: %d\n", i, statistics_rxlevels[i]);
422 #endif
423 /* Restore the original transfer setup and return error-free. */
424 writel(saved_ctrlr0, ®s->ctrlr0);
425 return 0;
426 }
427
rockchip_spi_xfer(struct udevice * dev,unsigned int bitlen,const void * dout,void * din,unsigned long flags)428 static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
429 const void *dout, void *din, unsigned long flags)
430 {
431 struct udevice *bus = dev->parent;
432 struct rockchip_spi_priv *priv = dev_get_priv(bus);
433 struct rockchip_spi *regs = priv->regs;
434 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
435 int len = bitlen >> 3;
436 const u8 *out = dout;
437 u8 *in = din;
438 int toread, towrite;
439 int ret = 0;
440
441 debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
442 len, flags);
443 if (DEBUG_RK_SPI)
444 rkspi_dump_regs(regs);
445
446 /* Assert CS before transfer */
447 if (flags & SPI_XFER_BEGIN)
448 spi_cs_activate(dev, slave_plat->cs);
449
450 /*
451 * To ensure fast loading of firmware images (e.g. full U-Boot
452 * stage, ATF, Linux kernel) from SPI flash, we optimise the
453 * case of read-only transfers by using the full 16bits of each
454 * FIFO element.
455 */
456 if (!out)
457 ret = rockchip_spi_16bit_reader(dev, &in, &len);
458
459 /* This is the original 8bit reader/writer code */
460 while (len > 0) {
461 int todo = min(len, ROCKCHIP_SPI_MAX_TRANLEN);
462
463 rkspi_enable_chip(regs, false);
464 writel(todo - 1, ®s->ctrlr1);
465 rkspi_enable_chip(regs, true);
466
467 toread = todo;
468 towrite = todo;
469 while (toread || towrite) {
470 u32 status = readl(®s->sr);
471
472 if (towrite && !(status & SR_TF_FULL)) {
473 writel(out ? *out++ : 0, regs->txdr);
474 towrite--;
475 }
476 if (toread && !(status & SR_RF_EMPT)) {
477 u32 byte = readl(regs->rxdr);
478
479 if (in)
480 *in++ = byte;
481 toread--;
482 }
483 }
484
485 /*
486 * In case that there's a transmit-component, we need to wait
487 * until the control goes idle before we can disable the SPI
488 * control logic (as this will implictly flush the FIFOs).
489 */
490 if (out) {
491 ret = rkspi_wait_till_not_busy(regs);
492 if (ret)
493 break;
494 }
495
496 len -= todo;
497 }
498
499 /* Deassert CS after transfer */
500 if (flags & SPI_XFER_END)
501 spi_cs_deactivate(dev, slave_plat->cs);
502
503 rkspi_enable_chip(regs, false);
504
505 return ret;
506 }
507
rockchip_spi_set_speed(struct udevice * bus,uint speed)508 static int rockchip_spi_set_speed(struct udevice *bus, uint speed)
509 {
510 struct rockchip_spi_priv *priv = dev_get_priv(bus);
511
512 /* Clamp to the maximum frequency specified in the DTS */
513 if (speed > priv->max_freq)
514 speed = priv->max_freq;
515
516 priv->speed_hz = speed;
517
518 return 0;
519 }
520
rockchip_spi_set_mode(struct udevice * bus,uint mode)521 static int rockchip_spi_set_mode(struct udevice *bus, uint mode)
522 {
523 struct rockchip_spi_priv *priv = dev_get_priv(bus);
524
525 priv->mode = mode;
526
527 return 0;
528 }
529
530 static const struct dm_spi_ops rockchip_spi_ops = {
531 .claim_bus = rockchip_spi_claim_bus,
532 .release_bus = rockchip_spi_release_bus,
533 .xfer = rockchip_spi_xfer,
534 .set_speed = rockchip_spi_set_speed,
535 .set_mode = rockchip_spi_set_mode,
536 /*
537 * cs_info is not needed, since we require all chip selects to be
538 * in the device tree explicitly
539 */
540 };
541
542 const struct rockchip_spi_params rk3399_spi_params = {
543 .master_manages_fifo = true,
544 };
545
546 static const struct udevice_id rockchip_spi_ids[] = {
547 { .compatible = "rockchip,rk3066-spi" },
548 { .compatible = "rockchip,rk3288-spi" },
549 { .compatible = "rockchip,rk3328-spi" },
550 { .compatible = "rockchip,rk3368-spi",
551 .data = (ulong)&rk3399_spi_params },
552 { .compatible = "rockchip,rk3399-spi",
553 .data = (ulong)&rk3399_spi_params },
554 { }
555 };
556
557 U_BOOT_DRIVER(rockchip_rk3288_spi) = {
558 .name = "rockchip_rk3288_spi",
559 .id = UCLASS_SPI,
560 .of_match = rockchip_spi_ids,
561 .ops = &rockchip_spi_ops,
562 .of_to_plat = rockchip_spi_of_to_plat,
563 .plat_auto = sizeof(struct rockchip_spi_plat),
564 .priv_auto = sizeof(struct rockchip_spi_priv),
565 .probe = rockchip_spi_probe,
566 };
567
568 DM_DRIVER_ALIAS(rockchip_rk3288_spi, rockchip_rk3368_spi)
569