1 /* 2 * NS16550 Serial Port 3 * originally from linux source (arch/powerpc/boot/ns16550.h) 4 * 5 * Cleanup and unification 6 * (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH 7 * 8 * modified slightly to 9 * have addresses as offsets from CONFIG_SYS_ISA_BASE 10 * added a few more definitions 11 * added prototypes for ns16550.c 12 * reduced no of com ports to 2 13 * modifications (c) Rob Taylor, Flying Pig Systems. 2000. 14 * 15 * added support for port on 64-bit bus 16 * by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems 17 */ 18 19 /* 20 * Note that the following macro magic uses the fact that the compiler 21 * will not allocate storage for arrays of size 0 22 */ 23 24 #ifndef __ns16550_h 25 #define __ns16550_h 26 27 #include <linux/types.h> 28 29 #ifdef CONFIG_DM_SERIAL 30 /* 31 * For driver model we always use one byte per register, and sort out the 32 * differences in the driver 33 */ 34 #define CONFIG_SYS_NS16550_REG_SIZE (-1) 35 #endif 36 37 #ifdef CONFIG_NS16550_DYNAMIC 38 #define UART_REG(x) unsigned char x 39 #else 40 #if !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE == 0) 41 #error "Please define NS16550 registers size." 42 #elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_DM_SERIAL) 43 #define UART_REG(x) u32 x 44 #elif (CONFIG_SYS_NS16550_REG_SIZE > 0) 45 #define UART_REG(x) \ 46 unsigned char prepad_##x[CONFIG_SYS_NS16550_REG_SIZE - 1]; \ 47 unsigned char x; 48 #elif (CONFIG_SYS_NS16550_REG_SIZE < 0) 49 #define UART_REG(x) \ 50 unsigned char x; \ 51 unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1]; 52 #endif 53 #endif /* CONFIG_NS16550_DYNAMIC */ 54 55 enum ns16550_flags { 56 NS16550_FLAG_IO = 1 << 0, /* Use I/O access (else mem-mapped) */ 57 NS16550_FLAG_ENDIAN = 1 << 1, /* Use out_le/be_32() */ 58 NS16550_FLAG_BE = 1 << 2, /* Big-endian access (else little) */ 59 }; 60 61 /** 62 * struct ns16550_plat - information about a NS16550 port 63 * 64 * @base: Base register address 65 * @reg_width: IO accesses size of registers (in bytes, 1 or 4) 66 * @reg_shift: Shift size of registers (0=byte, 1=16bit, 2=32bit...) 67 * @reg_offset: Offset to start of registers (normally 0) 68 * @clock: UART base clock speed in Hz 69 * @fcr: Offset of FCR register (normally UART_FCR_DEFVAL) 70 * @flags: A few flags (enum ns16550_flags) 71 * @bdf: PCI slot/function (pci_dev_t) 72 */ 73 struct ns16550_plat { 74 unsigned long base; 75 int reg_width; 76 int reg_shift; 77 int reg_offset; 78 int clock; 79 u32 fcr; 80 int flags; 81 #if defined(CONFIG_PCI) && defined(CONFIG_SPL) 82 int bdf; 83 #endif 84 }; 85 86 struct udevice; 87 88 struct ns16550 { 89 UART_REG(rbr); /* 0 */ 90 UART_REG(ier); /* 1 */ 91 UART_REG(fcr); /* 2 */ 92 UART_REG(lcr); /* 3 */ 93 UART_REG(mcr); /* 4 */ 94 UART_REG(lsr); /* 5 */ 95 UART_REG(msr); /* 6 */ 96 UART_REG(spr); /* 7 */ 97 #ifdef CONFIG_SOC_DA8XX 98 UART_REG(reg8); /* 8 */ 99 UART_REG(reg9); /* 9 */ 100 UART_REG(revid1); /* A */ 101 UART_REG(revid2); /* B */ 102 UART_REG(pwr_mgmt); /* C */ 103 UART_REG(mdr1); /* D */ 104 #else 105 UART_REG(mdr1); /* 8 */ 106 UART_REG(reg9); /* 9 */ 107 UART_REG(regA); /* A */ 108 UART_REG(regB); /* B */ 109 UART_REG(regC); /* C */ 110 UART_REG(regD); /* D */ 111 UART_REG(regE); /* E */ 112 UART_REG(uasr); /* F */ 113 UART_REG(scr); /* 10*/ 114 UART_REG(ssr); /* 11*/ 115 #endif 116 #ifdef CONFIG_DM_SERIAL 117 struct ns16550_plat *plat; 118 #endif 119 }; 120 121 #define thr rbr 122 #define iir fcr 123 #define dll rbr 124 #define dlm ier 125 126 /* 127 * These are the definitions for the FIFO Control Register 128 */ 129 #define UART_FCR_FIFO_EN 0x01 /* Fifo enable */ 130 #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ 131 #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ 132 #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ 133 #define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ 134 #define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ 135 #define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ 136 #define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ 137 #define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ 138 139 #define UART_FCR_RXSR 0x02 /* Receiver soft reset */ 140 #define UART_FCR_TXSR 0x04 /* Transmitter soft reset */ 141 142 /* Ingenic JZ47xx specific UART-enable bit. */ 143 #define UART_FCR_UME 0x10 144 145 /* Clear & enable FIFOs */ 146 #define UART_FCR_DEFVAL (UART_FCR_FIFO_EN | \ 147 UART_FCR_RXSR | \ 148 UART_FCR_TXSR) 149 150 /* 151 * These are the definitions for the Modem Control Register 152 */ 153 #define UART_MCR_DTR 0x01 /* DTR */ 154 #define UART_MCR_RTS 0x02 /* RTS */ 155 #define UART_MCR_OUT1 0x04 /* Out 1 */ 156 #define UART_MCR_OUT2 0x08 /* Out 2 */ 157 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ 158 #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */ 159 160 #define UART_MCR_DMA_EN 0x04 161 #define UART_MCR_TX_DFR 0x08 162 163 /* 164 * These are the definitions for the Line Control Register 165 * 166 * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting 167 * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. 168 */ 169 #define UART_LCR_WLS_MSK 0x03 /* character length select mask */ 170 #define UART_LCR_WLS_5 0x00 /* 5 bit character length */ 171 #define UART_LCR_WLS_6 0x01 /* 6 bit character length */ 172 #define UART_LCR_WLS_7 0x02 /* 7 bit character length */ 173 #define UART_LCR_WLS_8 0x03 /* 8 bit character length */ 174 #define UART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */ 175 #define UART_LCR_PEN 0x08 /* Parity eneble */ 176 #define UART_LCR_EPS 0x10 /* Even Parity Select */ 177 #define UART_LCR_STKP 0x20 /* Stick Parity */ 178 #define UART_LCR_SBRK 0x40 /* Set Break */ 179 #define UART_LCR_BKSE 0x80 /* Bank select enable */ 180 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ 181 182 /* 183 * These are the definitions for the Line Status Register 184 */ 185 #define UART_LSR_DR 0x01 /* Data ready */ 186 #define UART_LSR_OE 0x02 /* Overrun */ 187 #define UART_LSR_PE 0x04 /* Parity error */ 188 #define UART_LSR_FE 0x08 /* Framing error */ 189 #define UART_LSR_BI 0x10 /* Break */ 190 #define UART_LSR_THRE 0x20 /* Xmit holding register empty */ 191 #define UART_LSR_TEMT 0x40 /* Xmitter empty */ 192 #define UART_LSR_ERR 0x80 /* Error */ 193 194 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ 195 #define UART_MSR_RI 0x40 /* Ring Indicator */ 196 #define UART_MSR_DSR 0x20 /* Data Set Ready */ 197 #define UART_MSR_CTS 0x10 /* Clear to Send */ 198 #define UART_MSR_DDCD 0x08 /* Delta DCD */ 199 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ 200 #define UART_MSR_DDSR 0x02 /* Delta DSR */ 201 #define UART_MSR_DCTS 0x01 /* Delta CTS */ 202 203 /* 204 * These are the definitions for the Interrupt Identification Register 205 */ 206 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ 207 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ 208 209 #define UART_IIR_MSI 0x00 /* Modem status interrupt */ 210 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ 211 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ 212 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ 213 214 /* 215 * These are the definitions for the Interrupt Enable Register 216 */ 217 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ 218 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ 219 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ 220 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ 221 222 /* useful defaults for LCR */ 223 #define UART_LCR_8N1 0x03 224 225 void ns16550_init(struct ns16550 *com_port, int baud_divisor); 226 void ns16550_putc(struct ns16550 *com_port, char c); 227 char ns16550_getc(struct ns16550 *com_port); 228 int ns16550_tstc(struct ns16550 *com_port); 229 void ns16550_reinit(struct ns16550 *com_port, int baud_divisor); 230 231 /** 232 * ns16550_calc_divisor() - calculate the divisor given clock and baud rate 233 * 234 * Given the UART input clock and required baudrate, calculate the divisor 235 * that should be used. 236 * 237 * @port: UART port 238 * @clock: UART input clock speed in Hz 239 * @baudrate: Required baud rate 240 * @return baud rate divisor that should be used 241 */ 242 int ns16550_calc_divisor(struct ns16550 *port, int clock, int baudrate); 243 244 /** 245 * ns16550_serial_of_to_plat() - convert DT to platform data 246 * 247 * Decode a device tree node for an ns16550 device. This includes the 248 * register base address and register shift properties. The caller must set 249 * up the clock frequency. 250 * 251 * @dev: dev to decode platform data for 252 * @return: 0 if OK, -EINVAL on error 253 */ 254 int ns16550_serial_of_to_plat(struct udevice *dev); 255 256 /** 257 * ns16550_serial_probe() - probe a serial port 258 * 259 * This sets up the serial port ready for use, except for the baud rate 260 * @return 0, or -ve on error 261 */ 262 int ns16550_serial_probe(struct udevice *dev); 263 264 /** 265 * struct ns16550_serial_ops - ns16550 serial operations 266 * 267 * These should be used by the client driver for the driver's 'ops' member 268 */ 269 extern const struct dm_serial_ops ns16550_serial_ops; 270 271 #endif /* __ns16550_h */ 272