1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2020 Marvell International Ltd.
4 *
5 */
6
7/*
8 * Device Tree file for Marvell Armada AP806/AP807.
9 */
10
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12
13/dts-v1/;
14
15/ {
16	compatible = "marvell,armada-ap806";
17	#address-cells = <2>;
18	#size-cells = <2>;
19
20	aliases {
21		serial0 = &uart0;
22		serial1 = &uart1;
23	};
24
25	psci {
26		compatible = "arm,psci-0.2";
27		method = "smc";
28	};
29
30	reserved-memory {
31		#address-cells = <2>;
32		#size-cells = <2>;
33		ranges;
34
35		psci-area@4000000 {
36			reg = <0x0 0x4000000 0x0 0x200000>;
37			no-map;
38		};
39	};
40
41	AP_NAME {
42		#address-cells = <2>;
43		#size-cells = <2>;
44		compatible = "simple-bus";
45		interrupt-parent = <&gic>;
46		ranges;
47
48		config-space {
49			#address-cells = <1>;
50			#size-cells = <1>;
51			compatible = "simple-bus";
52			ranges = <0x0 0x0 0xf0000000 0x1000000>;
53
54			gic: interrupt-controller@210000 {
55				compatible = "arm,gic-400";
56				#interrupt-cells = <3>;
57				#address-cells = <1>;
58				#size-cells = <1>;
59				ranges;
60				interrupt-controller;
61				interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
62				reg = <0x210000 0x10000>,
63				      <0x220000 0x20000>,
64				      <0x240000 0x20000>,
65				      <0x260000 0x20000>;
66
67				gic_v2m0: v2m@280000 {
68					compatible = "arm,gic-v2m-frame";
69					msi-controller;
70					reg = <0x280000 0x1000>;
71					arm,msi-base-spi = <160>;
72					arm,msi-num-spis = <32>;
73				};
74				gic_v2m1: v2m@290000 {
75					compatible = "arm,gic-v2m-frame";
76					msi-controller;
77					reg = <0x290000 0x1000>;
78					arm,msi-base-spi = <192>;
79					arm,msi-num-spis = <32>;
80				};
81				gic_v2m2: v2m@2a0000 {
82					compatible = "arm,gic-v2m-frame";
83					msi-controller;
84					reg = <0x2a0000 0x1000>;
85					arm,msi-base-spi = <224>;
86					arm,msi-num-spis = <32>;
87				};
88				gic_v2m3: v2m@2b0000 {
89					compatible = "arm,gic-v2m-frame";
90					msi-controller;
91					reg = <0x2b0000 0x1000>;
92					arm,msi-base-spi = <256>;
93					arm,msi-num-spis = <32>;
94				};
95			};
96
97			timer {
98				compatible = "arm,armv8-timer";
99				interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
100					     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
101					     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
102					     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
103			};
104
105			odmi: odmi@300000 {
106				compatible = "marvell,odmi-controller";
107				interrupt-controller;
108				msi-controller;
109				marvell,odmi-frames = <4>;
110				reg = <0x300000 0x4000>,
111				      <0x304000 0x4000>,
112				      <0x308000 0x4000>,
113				      <0x30C000 0x4000>;
114				marvell,spi-base = <128>, <136>, <144>, <152>;
115			};
116
117			ap_pinctl: ap-pinctl@6F4000 {
118				compatible = "marvell,ap806-pinctrl";
119				bank-name ="apn-806";
120				reg = <0x6F4000 0x10>;
121				pin-count = <20>;
122				max-func = <3>;
123
124				ap_i2c0_pins: i2c-pins-0 {
125					marvell,pins = < 4 5 >;
126					marvell,function = <3>;
127				};
128				ap_emmc_pins: emmc-pins-0 {
129					marvell,pins = < 0 1 2 3 4 5 6 7
130							 8 9 10 12 >;
131					marvell,function = <1>;
132				};
133			};
134
135			ap_gpio0: gpio@6F5040 {
136				compatible = "marvell,orion-gpio";
137				reg = <0x6F5040 0x40>;
138				ngpios = <20>;
139				gpio-controller;
140				#gpio-cells = <2>;
141			};
142
143			ap_spi0: spi@510600 {
144				compatible = "marvell,armada-380-spi";
145				reg = <0x510600 0x50>;
146				#address-cells = <1>;
147				#size-cells = <0>;
148				cell-index = <0>;
149				interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
150				clocks = <&ap_syscon 3>;
151				status = "disabled";
152			};
153
154			ap_i2c0: i2c@511000 {
155				compatible = "marvell,mv78230-i2c";
156				reg = <0x511000 0x20>;
157				#address-cells = <1>;
158				#size-cells = <0>;
159				interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
160				timeout-ms = <1000>;
161				clocks = <&ap_syscon 3>;
162				status = "disabled";
163			};
164
165			uart0: serial@512000 {
166				compatible = "snps,dw-apb-uart";
167				reg = <0x512000 0x100>;
168				reg-shift = <2>;
169				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
170				reg-io-width = <1>;
171				clocks = <&ap_syscon 3>;
172				status = "disabled";
173				clock-frequency = <200000000>;
174			};
175
176			uart1: serial@512100 {
177				compatible = "snps,dw-apb-uart";
178				reg = <0x512100 0x100>;
179				reg-shift = <2>;
180				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
181				reg-io-width = <1>;
182				clocks = <&ap_syscon 3>;
183				status = "disabled";
184
185			};
186
187			watchdog: watchdog@610000 {
188				compatible = "arm,sbsa-gwdt";
189				reg = <0x610000 0x1000>, <0x600000 0x1000>;
190			};
191
192			ap_sdhci0: sdhci@6e0000 {
193				compatible = "marvell,armada-8k-sdhci";
194				reg = <0x6e0000 0x300>;
195				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
196				dma-coherent;
197				status = "disabled";
198			};
199
200			ap_syscon: system-controller@6f4000 {
201				compatible = "marvell,ap806-system-controller",
202					     "syscon";
203				#clock-cells = <1>;
204				clock-output-names = "ap-cpu-cluster-0",
205						     "ap-cpu-cluster-1",
206						     "ap-fixed", "ap-mss";
207				reg = <0x6f4000 0x1000>;
208			};
209		};
210	};
211};
212