1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2018 NXP 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include "fsl-imx8-ca35.dtsi" 8#include <dt-bindings/soc/imx_rsrc.h> 9#include <dt-bindings/soc/imx8_pd.h> 10#include <dt-bindings/clock/imx8qxp-clock.h> 11#include <dt-bindings/input/input.h> 12#include <dt-bindings/pinctrl/pads-imx8qxp.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/thermal/thermal.h> 15 16/ { 17 model = "Freescale i.MX8DX"; 18 compatible = "fsl,imx8dx", "fsl,imx8qxp"; 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 ethernet0 = &fec1; 25 ethernet1 = &fec2; 26 serial0 = &lpuart0; 27 mmc0 = &usdhc1; 28 mmc1 = &usdhc2; 29 mmc2 = &usdhc3; 30 i2c0 = &i2c0; 31 i2c1 = &i2c1; 32 i2c2 = &i2c2; 33 i2c3 = &i2c3; 34 gpio0 = &gpio0; 35 gpio1 = &gpio1; 36 gpio2 = &gpio2; 37 gpio3 = &gpio3; 38 gpio4 = &gpio4; 39 gpio5 = &gpio5; 40 gpio6 = &gpio6; 41 gpio7 = &gpio7; 42 }; 43 44 memory@80000000 { 45 device_type = "memory"; 46 reg = <0x00000000 0x80000000 0 0x40000000>; 47 /* DRAM space - 1, size : 1 GB DRAM */ 48 }; 49 50 reserved-memory { 51 #address-cells = <2>; 52 #size-cells = <2>; 53 ranges; 54 55 /* 56 * reserved-memory layout 57 * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 58 * Shouldn't be used at A core and Linux side. 59 * 60 */ 61 decoder_boot: decoder_boot@0x84000000 { 62 no-map; 63 reg = <0 0x84000000 0 0x2000000>; 64 }; 65 encoder_boot: encoder_boot@0x86000000 { 66 no-map; 67 reg = <0 0x86000000 0 0x2000000>; 68 }; 69 rpmsg_reserved: rpmsg@0x90000000 { 70 no-map; 71 reg = <0 0x90000000 0 0x400000>; 72 }; 73 decoder_rpc: decoder_rpc@0x90400000 { 74 no-map; 75 reg = <0 0x90400000 0 0x1000000>; 76 }; 77 encoder_rpc: encoder_rpc@0x91400000 { 78 no-map; 79 reg = <0 0x91400000 0 0x1000000>; 80 }; 81 dsp_reserved: dsp@0x92400000 { 82 no-map; 83 reg = <0 0x92400000 0 0x2000000>; 84 }; 85 decoder_str: str@0x94400000 { 86 no-map; 87 reg = <0 0x94400000 0 0x1800000>; 88 }; 89 /* global autoconfigured region for contiguous allocations */ 90 linux,cma { 91 compatible = "shared-dma-pool"; 92 reusable; 93 size = <0 0x28000000>; 94 alloc-ranges = <0 0x96000000 0 0x28000000>; 95 linux,cma-default; 96 }; 97 }; 98 99 gic: interrupt-controller@51a00000 { 100 compatible = "arm,gic-v3"; 101 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ 102 <0x0 0x51b00000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ 103 #interrupt-cells = <3>; 104 interrupt-controller; 105 interrupts = <GIC_PPI 9 106 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 107 interrupt-parent = <&gic>; 108 }; 109 110 mu: mu@5d1c0000 { 111 compatible = "fsl,imx8-mu"; 112 reg = <0x0 0x5d1c0000 0x0 0x10000>; 113 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 114 interrupt-parent = <&gic>; 115 status = "okay"; 116 117 clk: clk { 118 compatible = "fsl,imx8qxp-clk"; 119 #clock-cells = <1>; 120 }; 121 122 iomuxc: iomuxc { 123 compatible = "fsl,imx8qxp-iomuxc"; 124 }; 125 }; 126 127 imx8qx-pm { 128 compatible = "simple-bus"; 129 #address-cells = <1>; 130 #size-cells = <0>; 131 132 pd_lsio: PD_LSIO { 133 compatible = "nxp,imx8-pd"; 134 reg = <SC_R_NONE>; 135 #power-domain-cells = <0>; 136 #address-cells = <1>; 137 #size-cells = <0>; 138 139 pd_lsio_gpio0: PD_LSIO_GPIO_0 { 140 reg = <SC_R_GPIO_0>; 141 #power-domain-cells = <0>; 142 power-domains = <&pd_lsio>; 143 }; 144 pd_lsio_gpio1: PD_LSIO_GPIO_1 { 145 reg = <SC_R_GPIO_1>; 146 #power-domain-cells = <0>; 147 power-domains = <&pd_lsio>; 148 }; 149 pd_lsio_gpio2: PD_LSIO_GPIO_2 { 150 reg = <SC_R_GPIO_2>; 151 #power-domain-cells = <0>; 152 power-domains = <&pd_lsio>; 153 }; 154 pd_lsio_gpio3: PD_LSIO_GPIO_3 { 155 reg = <SC_R_GPIO_3>; 156 #power-domain-cells = <0>; 157 power-domains = <&pd_lsio>; 158 }; 159 pd_lsio_gpio4: PD_LSIO_GPIO_4 { 160 reg = <SC_R_GPIO_4>; 161 #power-domain-cells = <0>; 162 power-domains = <&pd_lsio>; 163 }; 164 pd_lsio_gpio5: PD_LSIO_GPIO_5{ 165 reg = <SC_R_GPIO_5>; 166 #power-domain-cells = <0>; 167 power-domains = <&pd_lsio>; 168 }; 169 pd_lsio_gpio6: PD_LSIO_GPIO_6 { 170 reg = <SC_R_GPIO_6>; 171 #power-domain-cells = <0>; 172 power-domains = <&pd_lsio>; 173 }; 174 pd_lsio_gpio7: PD_LSIO_GPIO_7 { 175 reg = <SC_R_GPIO_7>; 176 #power-domain-cells = <0>; 177 power-domains = <&pd_lsio>; 178 }; 179 }; 180 181 pd_conn: PD_CONN { 182 compatible = "nxp,imx8-pd"; 183 reg = <SC_R_NONE>; 184 #power-domain-cells = <0>; 185 #address-cells = <1>; 186 #size-cells = <0>; 187 188 pd_conn_sdch0: PD_CONN_SDHC_0 { 189 reg = <SC_R_SDHC_0>; 190 #power-domain-cells = <0>; 191 power-domains = <&pd_conn>; 192 }; 193 pd_conn_sdch1: PD_CONN_SDHC_1 { 194 reg = <SC_R_SDHC_1>; 195 #power-domain-cells = <0>; 196 power-domains = <&pd_conn>; 197 }; 198 pd_conn_sdch2: PD_CONN_SDHC_2 { 199 reg = <SC_R_SDHC_2>; 200 #power-domain-cells = <0>; 201 power-domains = <&pd_conn>; 202 }; 203 pd_conn_enet0: PD_CONN_ENET_0 { 204 reg = <SC_R_ENET_0>; 205 #power-domain-cells = <0>; 206 power-domains = <&pd_conn>; 207 }; 208 pd_conn_enet1: PD_CONN_ENET_1 { 209 reg = <SC_R_ENET_1>; 210 #power-domain-cells = <0>; 211 power-domains = <&pd_conn>; 212 }; 213 }; 214 215 pd_dma: PD_DMA { 216 compatible = "nxp,imx8-pd"; 217 reg = <SC_R_NONE>; 218 #power-domain-cells = <0>; 219 #address-cells = <1>; 220 #size-cells = <0>; 221 222 pd_dma_lpi2c0: PD_DMA_I2C_0 { 223 reg = <SC_R_I2C_0>; 224 #power-domain-cells = <0>; 225 power-domains = <&pd_dma>; 226 }; 227 pd_dma_lpi2c1: PD_DMA_I2C_1 { 228 reg = <SC_R_I2C_1>; 229 #power-domain-cells = <0>; 230 power-domains = <&pd_dma>; 231 }; 232 pd_dma_lpi2c2:PD_DMA_I2C_2 { 233 reg = <SC_R_I2C_2>; 234 #power-domain-cells = <0>; 235 power-domains = <&pd_dma>; 236 }; 237 pd_dma_lpi2c3: PD_DMA_I2C_3 { 238 reg = <SC_R_I2C_3>; 239 #power-domain-cells = <0>; 240 power-domains = <&pd_dma>; 241 }; 242 pd_dma_lpuart0: PD_DMA_UART0 { 243 reg = <SC_R_UART_0>; 244 #power-domain-cells = <0>; 245 power-domains = <&pd_dma>; 246 wakeup-irq = <225>; 247 }; 248 pd_dma_lpuart1: PD_DMA_UART1 { 249 reg = <SC_R_UART_1>; 250 #power-domain-cells = <0>; 251 power-domains = <&pd_dma>; 252 }; 253 pd_dma_lpuart2: PD_DMA_UART2 { 254 reg = <SC_R_UART_2>; 255 #power-domain-cells = <0>; 256 power-domains = <&pd_dma>; 257 }; 258 pd_dma_lpuart3: PD_DMA_UART3 { 259 reg = <SC_R_UART_3>; 260 #power-domain-cells = <0>; 261 power-domains = <&pd_dma>; 262 }; 263 }; 264 }; 265 266 i2c0: i2c@5a800000 { 267 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 268 reg = <0x0 0x5a800000 0x0 0x4000>; 269 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 270 interrupt-parent = <&gic>; 271 clocks = <&clk IMX8QXP_I2C0_CLK>, 272 <&clk IMX8QXP_I2C0_IPG_CLK>; 273 clock-names = "per", "ipg"; 274 assigned-clocks = <&clk IMX8QXP_I2C0_CLK>; 275 assigned-clock-rates = <24000000>; 276 power-domains = <&pd_dma_lpi2c0>; 277 #address-cells = <1>; 278 #size-cells = <0>; 279 status = "disabled"; 280 }; 281 282 i2c1: i2c@5a810000 { 283 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 284 reg = <0x0 0x5a810000 0x0 0x4000>; 285 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 286 interrupt-parent = <&gic>; 287 clocks = <&clk IMX8QXP_I2C1_CLK>, 288 <&clk IMX8QXP_I2C1_IPG_CLK>; 289 clock-names = "per", "ipg"; 290 assigned-clocks = <&clk IMX8QXP_I2C1_CLK>; 291 assigned-clock-rates = <24000000>; 292 power-domains = <&pd_dma_lpi2c1>; 293 #address-cells = <1>; 294 #size-cells = <0>; 295 status = "disabled"; 296 }; 297 298 i2c2: i2c@5a820000 { 299 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 300 reg = <0x0 0x5a820000 0x0 0x4000>; 301 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 302 interrupt-parent = <&gic>; 303 clocks = <&clk IMX8QXP_I2C2_CLK>, 304 <&clk IMX8QXP_I2C2_IPG_CLK>; 305 clock-names = "per", "ipg"; 306 assigned-clocks = <&clk IMX8QXP_I2C2_CLK>; 307 assigned-clock-rates = <24000000>; 308 power-domains = <&pd_dma_lpi2c2>; 309 #address-cells = <1>; 310 #size-cells = <0>; 311 status = "disabled"; 312 }; 313 314 i2c3: i2c@5a830000 { 315 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 316 reg = <0x0 0x5a830000 0x0 0x4000>; 317 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 318 interrupt-parent = <&gic>; 319 clocks = <&clk IMX8QXP_I2C3_CLK>, 320 <&clk IMX8QXP_I2C3_IPG_CLK>; 321 clock-names = "per", "ipg"; 322 assigned-clocks = <&clk IMX8QXP_I2C3_CLK>; 323 assigned-clock-rates = <24000000>; 324 power-domains = <&pd_dma_lpi2c3>; 325 #address-cells = <1>; 326 #size-cells = <0>; 327 status = "disabled"; 328 }; 329 330 gpio0: gpio@5d080000 { 331 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 332 reg = <0x0 0x5d080000 0x0 0x10000>; 333 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 334 gpio-controller; 335 #gpio-cells = <2>; 336 power-domains = <&pd_lsio_gpio0>; 337 interrupt-controller; 338 #interrupt-cells = <2>; 339 }; 340 341 gpio1: gpio@5d090000 { 342 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 343 reg = <0x0 0x5d090000 0x0 0x10000>; 344 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 345 gpio-controller; 346 #gpio-cells = <2>; 347 power-domains = <&pd_lsio_gpio1>; 348 interrupt-controller; 349 #interrupt-cells = <2>; 350 }; 351 352 gpio2: gpio@5d0a0000 { 353 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 354 reg = <0x0 0x5d0a0000 0x0 0x10000>; 355 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 356 gpio-controller; 357 #gpio-cells = <2>; 358 power-domains = <&pd_lsio_gpio2>; 359 interrupt-controller; 360 #interrupt-cells = <2>; 361 }; 362 363 gpio3: gpio@5d0b0000 { 364 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 365 reg = <0x0 0x5d0b0000 0x0 0x10000>; 366 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 367 gpio-controller; 368 #gpio-cells = <2>; 369 power-domains = <&pd_lsio_gpio3>; 370 interrupt-controller; 371 #interrupt-cells = <2>; 372 }; 373 374 gpio4: gpio@5d0c0000 { 375 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 376 reg = <0x0 0x5d0c0000 0x0 0x10000>; 377 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 378 gpio-controller; 379 #gpio-cells = <2>; 380 power-domains = <&pd_lsio_gpio4>; 381 interrupt-controller; 382 #interrupt-cells = <2>; 383 }; 384 385 gpio5: gpio@5d0d0000 { 386 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 387 reg = <0x0 0x5d0d0000 0x0 0x10000>; 388 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 389 gpio-controller; 390 #gpio-cells = <2>; 391 power-domains = <&pd_lsio_gpio5>; 392 interrupt-controller; 393 #interrupt-cells = <2>; 394 }; 395 396 gpio6: gpio@5d0e0000 { 397 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 398 reg = <0x0 0x5d0e0000 0x0 0x10000>; 399 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 400 gpio-controller; 401 #gpio-cells = <2>; 402 power-domains = <&pd_lsio_gpio6>; 403 interrupt-controller; 404 #interrupt-cells = <2>; 405 }; 406 407 gpio7: gpio@5d0f0000 { 408 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 409 reg = <0x0 0x5d0f0000 0x0 0x10000>; 410 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 411 gpio-controller; 412 #gpio-cells = <2>; 413 power-domains = <&pd_lsio_gpio7>; 414 interrupt-controller; 415 #interrupt-cells = <2>; 416 }; 417 418 lpuart0: serial@5a060000 { 419 compatible = "fsl,imx8qm-lpuart"; 420 reg = <0x0 0x5a060000 0x0 0x1000>; 421 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 422 clocks = <&clk IMX8QXP_UART0_CLK>, 423 <&clk IMX8QXP_UART0_IPG_CLK>; 424 clock-names = "per", "ipg"; 425 assigned-clocks = <&clk IMX8QXP_UART0_CLK>; 426 assigned-clock-rates = <80000000>; 427 power-domains = <&pd_dma_lpuart0>; 428 status = "disabled"; 429 }; 430 431 lpuart1: serial@5a070000 { 432 compatible = "fsl,imx8qm-lpuart"; 433 reg = <0x0 0x5a070000 0x0 0x1000>; 434 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 435 clocks = <&clk IMX8QXP_UART1_CLK>, 436 <&clk IMX8QXP_UART1_IPG_CLK>; 437 clock-names = "per", "ipg"; 438 assigned-clocks = <&clk IMX8QXP_UART1_CLK>; 439 assigned-clock-rates = <80000000>; 440 power-domains = <&pd_dma_lpuart1>; 441 status = "disabled"; 442 }; 443 444 lpuart2: serial@5a080000 { 445 compatible = "fsl,imx8qm-lpuart"; 446 reg = <0x0 0x5a080000 0x0 0x1000>; 447 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 448 clocks = <&clk IMX8QXP_UART2_CLK>, 449 <&clk IMX8QXP_UART2_IPG_CLK>; 450 clock-names = "per", "ipg"; 451 assigned-clocks = <&clk IMX8QXP_UART2_CLK>; 452 assigned-clock-rates = <80000000>; 453 power-domains = <&pd_dma_lpuart2>; 454 status = "disabled"; 455 }; 456 457 lpuart3: serial@5a090000 { 458 compatible = "fsl,imx8qm-lpuart"; 459 reg = <0x0 0x5a090000 0x0 0x1000>; 460 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 461 clocks = <&clk IMX8QXP_UART3_CLK>, 462 <&clk IMX8QXP_UART3_IPG_CLK>; 463 clock-names = "per", "ipg"; 464 assigned-clocks = <&clk IMX8QXP_UART3_CLK>; 465 assigned-clock-rates = <80000000>; 466 power-domains = <&pd_dma_lpuart3>; 467 status = "disabled"; 468 }; 469 470 usdhc1: usdhc@5b010000 { 471 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; 472 interrupt-parent = <&gic>; 473 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 474 reg = <0x0 0x5b010000 0x0 0x10000>; 475 clocks = <&clk IMX8QXP_SDHC0_IPG_CLK>, 476 <&clk IMX8QXP_SDHC0_CLK>, 477 <&clk IMX8QXP_CLK_DUMMY>; 478 clock-names = "ipg", "per", "ahb"; 479 assigned-clocks = <&clk IMX8QXP_SDHC0_SEL>, <&clk IMX8QXP_SDHC0_DIV>; 480 assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>; 481 assigned-clock-rates = <0>, <400000000>; 482 power-domains = <&pd_conn_sdch0>; 483 fsl,tuning-start-tap = <20>; 484 fsl,tuning-step= <2>; 485 status = "disabled"; 486 }; 487 488 usdhc2: usdhc@5b020000 { 489 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; 490 interrupt-parent = <&gic>; 491 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 492 reg = <0x0 0x5b020000 0x0 0x10000>; 493 clocks = <&clk IMX8QXP_SDHC1_IPG_CLK>, 494 <&clk IMX8QXP_SDHC1_CLK>, 495 <&clk IMX8QXP_CLK_DUMMY>; 496 clock-names = "ipg", "per", "ahb"; 497 assigned-clocks = <&clk IMX8QXP_SDHC1_SEL>, <&clk IMX8QXP_SDHC1_DIV>; 498 assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>; 499 assigned-clock-rates = <0>, <200000000>; 500 power-domains = <&pd_conn_sdch1>; 501 fsl,tuning-start-tap = <20>; 502 fsl,tuning-step= <2>; 503 status = "disabled"; 504 }; 505 506 usdhc3: usdhc@5b030000 { 507 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; 508 interrupt-parent = <&gic>; 509 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 510 reg = <0x0 0x5b030000 0x0 0x10000>; 511 clocks = <&clk IMX8QXP_SDHC2_IPG_CLK>, 512 <&clk IMX8QXP_SDHC2_CLK>, 513 <&clk IMX8QXP_CLK_DUMMY>; 514 clock-names = "ipg", "per", "ahb"; 515 assigned-clocks = <&clk IMX8QXP_SDHC2_SEL>, <&clk IMX8QXP_SDHC2_DIV>; 516 assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>; 517 assigned-clock-rates = <0>, <200000000>; 518 power-domains = <&pd_conn_sdch2>; 519 status = "disabled"; 520 }; 521 522 fec1: ethernet@5b040000 { 523 compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec"; 524 reg = <0x0 0x5b040000 0x0 0x10000>; 525 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 529 clocks = <&clk IMX8QXP_ENET0_IPG_CLK>, <&clk IMX8QXP_ENET0_AHB_CLK>, 530 <&clk IMX8QXP_ENET0_RGMII_TX_CLK>, <&clk IMX8QXP_ENET0_PTP_CLK>; 531 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 532 assigned-clocks = <&clk IMX8QXP_ENET0_REF_DIV>, <&clk IMX8QXP_ENET0_PTP_CLK>; 533 assigned-clock-rates = <125000000>, <125000000>; 534 fsl,num-tx-queues=<3>; 535 fsl,num-rx-queues=<3>; 536 power-domains = <&pd_conn_enet0>; 537 status = "disabled"; 538 }; 539 540 fec2: ethernet@5b050000 { 541 compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec"; 542 reg = <0x0 0x5b050000 0x0 0x10000>; 543 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 547 clocks = <&clk IMX8QXP_ENET1_IPG_CLK>, <&clk IMX8QXP_ENET1_AHB_CLK>, 548 <&clk IMX8QXP_ENET1_RGMII_TX_CLK>, <&clk IMX8QXP_ENET1_PTP_CLK>; 549 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 550 assigned-clocks = <&clk IMX8QXP_ENET1_REF_DIV>, <&clk IMX8QXP_ENET1_PTP_CLK>; 551 assigned-clock-rates = <125000000>, <125000000>; 552 fsl,num-tx-queues=<3>; 553 fsl,num-rx-queues=<3>; 554 power-domains = <&pd_conn_enet1>; 555 status = "disabled"; 556 }; 557 558 tsens: thermal-sensor { 559 compatible = "nxp,imx8qxp-sc-tsens"; 560 /* number of the temp sensor on the chip */ 561 tsens-num = <2>; 562 #thermal-sensor-cells = <1>; 563 }; 564 565 thermal_zones: thermal-zones { 566 /* cpu thermal */ 567 cpu-thermal0 { 568 polling-delay-passive = <250>; 569 polling-delay = <2000>; 570 /*the slope and offset of the temp sensor */ 571 thermal-sensors = <&tsens 0>; 572 trips { 573 cpu_alert0: trip0 { 574 temperature = <107000>; 575 hysteresis = <2000>; 576 type = "passive"; 577 }; 578 cpu_crit0: trip1 { 579 temperature = <127000>; 580 hysteresis = <2000>; 581 type = "critical"; 582 }; 583 }; 584 cooling-maps { 585 map0 { 586 trip = <&cpu_alert0>; 587 cooling-device = 588 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 589 }; 590 }; 591 }; 592 593 drc-thermal0 { 594 polling-delay-passive = <250>; 595 polling-delay = <2000>; 596 thermal-sensors = <&tsens 1>; 597 status = "disabled"; 598 trips { 599 drc_alert0: trip0 { 600 temperature = <107000>; 601 hysteresis = <2000>; 602 type = "passive"; 603 }; 604 drc_crit0: trip1 { 605 temperature = <127000>; 606 hysteresis = <2000>; 607 type = "critical"; 608 }; 609 }; 610 }; 611 }; 612}; 613 614&A35_0 { 615 clocks = <&clk IMX8QXP_A35_DIV>; 616}; 617 618/delete-node/ &A35_2; 619/delete-node/ &A35_3; 620