1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2017-2019 Intel Corporation <www.intel.com> 4 * All rights reserved. 5 */ 6 7 #include <asm/cache.h> 8 #include <altera.h> 9 #include <image.h> 10 #include <linux/bitops.h> 11 12 #ifndef _FPGA_MANAGER_ARRIA10_H_ 13 #define _FPGA_MANAGER_ARRIA10_H_ 14 15 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK BIT(0) 16 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK BIT(1) 17 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK BIT(2) 18 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK BIT(3) 19 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK BIT(4) 20 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_OE_SET_MSK BIT(5) 21 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK BIT(6) 22 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK BIT(7) 23 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_SET_MSK BIT(8) 24 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_READY_SET_MSK BIT(9) 25 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_SET_MSK BIT(10) 26 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_SET_MSK BIT(11) 27 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK BIT(12) 28 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_SET_MSK BIT(13) 29 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK BIT(16) 30 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK BIT(17) 31 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK BIT(18) 32 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD (\ 33 ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK |\ 34 ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK |\ 35 ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK) 36 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOEMPTY_SET_MSK BIT(24) 37 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOFULL_SET_MSK BIT(25) 38 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_JTAGM_SET_MSK BIT(28) 39 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EMR_SET_MSK BIT(29) 40 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB 16 41 42 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK BIT(0) 43 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK BIT(1) 44 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK BIT(2) 45 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK BIT(8) 46 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK BIT(16) 47 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK BIT(24) 48 49 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK BIT(0) 50 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK BIT(16) 51 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK BIT(24) 52 53 #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK BIT(0) 54 #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK BIT(8) 55 #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK 0x00030000 56 #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK BIT(24) 57 #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16 58 59 #define FPGA_SOCFPGA_A10_RBF_UNENCRYPTED 0xa65c 60 #define FPGA_SOCFPGA_A10_RBF_ENCRYPTED 0xa65d 61 #define FPGA_SOCFPGA_A10_RBF_PERIPH 0x0001 62 #define FPGA_SOCFPGA_A10_RBF_CORE 0x8001 63 #ifndef __ASSEMBLY__ 64 65 struct socfpga_fpga_manager { 66 u32 _pad_0x0_0x7[2]; 67 u32 dclkcnt; 68 u32 dclkstat; 69 u32 gpo; 70 u32 gpi; 71 u32 misci; 72 u32 _pad_0x1c_0x2f[5]; 73 u32 emr_data0; 74 u32 emr_data1; 75 u32 emr_data2; 76 u32 emr_data3; 77 u32 emr_data4; 78 u32 emr_data5; 79 u32 emr_valid; 80 u32 emr_en; 81 u32 jtag_config; 82 u32 jtag_status; 83 u32 jtag_kick; 84 u32 _pad_0x5c_0x5f; 85 u32 jtag_data_w; 86 u32 jtag_data_r; 87 u32 _pad_0x68_0x6f[2]; 88 u32 imgcfg_ctrl_00; 89 u32 imgcfg_ctrl_01; 90 u32 imgcfg_ctrl_02; 91 u32 _pad_0x7c_0x7f; 92 u32 imgcfg_stat; 93 u32 intr_masked_status; 94 u32 intr_mask; 95 u32 intr_polarity; 96 u32 dma_config; 97 u32 imgcfg_fifo_status; 98 }; 99 100 enum rbf_type { 101 unknown, 102 periph_section, 103 core_section 104 }; 105 106 enum rbf_security { 107 invalid, 108 unencrypted, 109 encrypted 110 }; 111 112 struct rbf_info { 113 enum rbf_type section; 114 enum rbf_security security; 115 }; 116 117 struct fpga_loadfs_info { 118 fpga_fs_info *fpga_fsinfo; 119 u32 remaining; 120 u32 offset; 121 struct rbf_info rbfinfo; 122 }; 123 124 /* Functions */ 125 int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size); 126 int fpgamgr_program_finish(void); 127 int is_fpgamgr_user_mode(void); 128 int fpgamgr_wait_early_user_mode(void); 129 const char *get_fpga_filename(void); 130 int is_fpgamgr_early_user_mode(void); 131 int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize, 132 u32 offset); 133 void fpgamgr_program(const void *buf, size_t bsize, u32 offset); 134 #endif /* __ASSEMBLY__ */ 135 136 #endif /* _FPGA_MANAGER_ARRIA10_H_ */ 137