1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
4  */
5 
6 #include <common.h>
7 #include <asm-offsets.h>
8 #include <clock_legacy.h>
9 #include <mpc83xx.h>
10 #include <time.h>
11 #include <asm/global_data.h>
12 
13 #include "lblaw/lblaw.h"
14 #include "elbc/elbc.h"
15 
16 DECLARE_GLOBAL_DATA_PTR;
17 
18 /*
19  * Breathe some life into the CPU...
20  *
21  * Set up the memory map,
22  * initialize a bunch of registers,
23  * initialize the UPM's
24  */
cpu_init_f(volatile immap_t * im)25 void cpu_init_f (volatile immap_t * im)
26 {
27 	/* Pointer is writable since we allocated a register for it */
28 	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
29 
30 	/* global data region was cleared in start.S */
31 
32 	/* system performance tweaking */
33 
34 #ifndef CONFIG_ACR_PIPE_DEP_UNSET
35 	/* Arbiter pipeline depth */
36 	im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
37 			  CONFIG_ACR_PIPE_DEP;
38 #endif
39 
40 #ifndef CONFIG_ACR_RPTCNT_UNSET
41 	/* Arbiter repeat count */
42 	im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) |
43 			  CONFIG_ACR_RPTCNT;
44 #endif
45 
46 #ifdef CONFIG_SYS_SPCR_OPT
47 	/* Optimize transactions between CSB and other devices */
48 	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) |
49 			   (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT);
50 #endif
51 
52 	/* Enable Time Base & Decrementer (so we will have udelay()) */
53 	im->sysconf.spcr |= SPCR_TBEN;
54 
55 	/* DDR control driver register */
56 #ifdef CONFIG_SYS_DDRCDR
57 	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR;
58 #endif
59 	/* Output buffer impedance register */
60 #ifdef CONFIG_SYS_OBIR
61 	im->sysconf.obir = CONFIG_SYS_OBIR;
62 #endif
63 
64 	/*
65 	 * Memory Controller:
66 	 */
67 
68 	/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
69 	 * addresses - these have to be modified later when FLASH size
70 	 * has been determined
71 	 */
72 
73 #if defined(CONFIG_SYS_NAND_BR_PRELIM)  \
74 	&& defined(CONFIG_SYS_NAND_OR_PRELIM) \
75 	&& defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \
76 	&& defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM)
77 	set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
78 	set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
79 	im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM;
80 	im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM;
81 #else
82 #error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined
83 #endif
84 }
85 
86 /*
87  * Get timebase clock frequency (like cpu_clk in Hz)
88  */
get_tbclk(void)89 unsigned long get_tbclk(void)
90 {
91 	return (gd->bus_clk + 3L) / 4L;
92 }
93 
puts(const char * str)94 void puts(const char *str)
95 {
96 	while (*str)
97 		putc(*str++);
98 }
99 
get_bus_freq(ulong dummy)100 ulong get_bus_freq(ulong dummy)
101 {
102 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
103 	u8 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
104 
105 	return CONFIG_SYS_CLK_FREQ * spmf;
106 }
107