1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> 4 */ 5 6/dts-v1/; 7 8#include <asm/arch-braswell/fsp/fsp_configs.h> 9#include <dt-bindings/interrupt-router/intel-irq.h> 10 11/include/ "skeleton.dtsi" 12/include/ "serial.dtsi" 13/include/ "reset.dtsi" 14/include/ "rtc.dtsi" 15/include/ "tsc_timer.dtsi" 16 17#include "smbios.dtsi" 18 19/ { 20 model = "Intel Cherry Hill"; 21 compatible = "intel,cherryhill", "intel,braswell"; 22 23 aliases { 24 serial0 = &serial; 25 spi0 = &spi; 26 }; 27 28 config { 29 silent_console = <0>; 30 }; 31 32 chosen { 33 stdout-path = "/serial"; 34 }; 35 36 cpus { 37 #address-cells = <1>; 38 #size-cells = <0>; 39 40 cpu@0 { 41 device_type = "cpu"; 42 compatible = "cpu-x86"; 43 reg = <0>; 44 intel,apic-id = <0>; 45 }; 46 47 cpu@1 { 48 device_type = "cpu"; 49 compatible = "cpu-x86"; 50 reg = <1>; 51 intel,apic-id = <2>; 52 }; 53 54 cpu@2 { 55 device_type = "cpu"; 56 compatible = "cpu-x86"; 57 reg = <2>; 58 intel,apic-id = <4>; 59 }; 60 61 cpu@3 { 62 device_type = "cpu"; 63 compatible = "cpu-x86"; 64 reg = <3>; 65 intel,apic-id = <6>; 66 }; 67 }; 68 69 pci { 70 compatible = "pci-x86"; 71 #address-cells = <3>; 72 #size-cells = <2>; 73 u-boot,dm-pre-reloc; 74 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000 75 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 76 0x01000000 0x0 0x2000 0x2000 0 0xe000>; 77 78 pch@1f,0 { 79 reg = <0x0000f800 0 0 0 0>; 80 compatible = "intel,pch9"; 81 82 irq-router { 83 compatible = "intel,irq-router"; 84 intel,pirq-config = "ibase"; 85 intel,ibase-offset = <0x50>; 86 intel,pirq-link = <8 8>; 87 intel,pirq-mask = <0xdee0>; 88 intel,pirq-routing = < 89 /* Braswell PCI devices */ 90 PCI_BDF(0, 2, 0) INTA PIRQA 91 PCI_BDF(0, 3, 0) INTA PIRQA 92 PCI_BDF(0, 11, 0) INTA PIRQA 93 PCI_BDF(0, 16, 0) INTA PIRQA 94 PCI_BDF(0, 17, 0) INTA PIRQA 95 PCI_BDF(0, 18, 0) INTA PIRQA 96 PCI_BDF(0, 19, 0) INTA PIRQA 97 PCI_BDF(0, 20, 0) INTA PIRQA 98 PCI_BDF(0, 21, 0) INTA PIRQA 99 PCI_BDF(0, 24, 0) INTA PIRQA 100 PCI_BDF(0, 24, 1) INTC PIRQC 101 PCI_BDF(0, 24, 2) INTD PIRQD 102 PCI_BDF(0, 24, 3) INTB PIRQB 103 PCI_BDF(0, 24, 4) INTA PIRQA 104 PCI_BDF(0, 24, 5) INTC PIRQC 105 PCI_BDF(0, 24, 6) INTD PIRQD 106 PCI_BDF(0, 24, 7) INTB PIRQB 107 PCI_BDF(0, 26, 0) INTA PIRQA 108 PCI_BDF(0, 27, 0) INTA PIRQA 109 PCI_BDF(0, 28, 0) INTA PIRQA 110 PCI_BDF(0, 28, 1) INTB PIRQB 111 PCI_BDF(0, 28, 2) INTC PIRQC 112 PCI_BDF(0, 28, 3) INTD PIRQD 113 PCI_BDF(0, 30, 0) INTA PIRQA 114 PCI_BDF(0, 30, 3) INTA PIRQA 115 PCI_BDF(0, 30, 4) INTA PIRQA 116 PCI_BDF(0, 31, 0) INTB PIRQB 117 PCI_BDF(0, 31, 3) INTB PIRQB 118 119 /* 120 * PCIe root ports downstream 121 * interrupts 122 */ 123 PCI_BDF(1, 0, 0) INTA PIRQA 124 PCI_BDF(1, 0, 0) INTB PIRQB 125 PCI_BDF(1, 0, 0) INTC PIRQC 126 PCI_BDF(1, 0, 0) INTD PIRQD 127 PCI_BDF(2, 0, 0) INTA PIRQB 128 PCI_BDF(2, 0, 0) INTB PIRQC 129 PCI_BDF(2, 0, 0) INTC PIRQD 130 PCI_BDF(2, 0, 0) INTD PIRQA 131 PCI_BDF(3, 0, 0) INTA PIRQC 132 PCI_BDF(3, 0, 0) INTB PIRQD 133 PCI_BDF(3, 0, 0) INTC PIRQA 134 PCI_BDF(3, 0, 0) INTD PIRQB 135 PCI_BDF(4, 0, 0) INTA PIRQD 136 PCI_BDF(4, 0, 0) INTB PIRQA 137 PCI_BDF(4, 0, 0) INTC PIRQB 138 PCI_BDF(4, 0, 0) INTD PIRQC 139 >; 140 }; 141 142 spi: spi { 143 #address-cells = <1>; 144 #size-cells = <0>; 145 compatible = "intel,ich9-spi"; 146 intel,spi-lock-down; 147 148 spi-flash@0 { 149 #address-cells = <1>; 150 #size-cells = <1>; 151 reg = <0>; 152 compatible = "macronix,mx25u6435f", "jedec,spi-nor"; 153 memory-map = <0xff800000 0x00800000>; 154 rw-mrc-cache { 155 label = "rw-mrc-cache"; 156 reg = <0x005e0000 0x00010000>; 157 }; 158 }; 159 }; 160 }; 161 }; 162 163 fsp { 164 compatible = "intel,braswell-fsp"; 165 fsp,memory-upd { 166 compatible = "intel,braswell-fsp-memory"; 167 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_4MB>; 168 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>; 169 fsp,mrc-init-spd-addr1 = <0xa0>; 170 fsp,mrc-init-spd-addr2 = <0xa2>; 171 fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_32MB>; 172 fsp,aperture-size = <APERTURE_SIZE_256MB>; 173 fsp,gtt-size = <GTT_SIZE_1MB>; 174 fsp,enable-dvfs; 175 fsp,memory-type = <DRAM_TYPE_DDR3>; 176 }; 177 fsp,silicon-upd { 178 compatible = "intel,braswell-fsp-silicon"; 179 fsp,sdcard-mode = <SDCARD_MODE_PCI>; 180 fsp,enable-hsuart1; 181 fsp,enable-sata; 182 fsp,enable-xhci; 183 fsp,lpe-mode = <LPE_MODE_PCI>; 184 fsp,enable-dma0; 185 fsp,enable-dma1; 186 fsp,enable-i2c0; 187 fsp,enable-i2c1; 188 fsp,enable-i2c2; 189 fsp,enable-i2c3; 190 fsp,enable-i2c4; 191 fsp,enable-i2c5; 192 fsp,enable-i2c6; 193 fsp,emmc-mode = <EMMC_MODE_PCI>; 194 fsp,sata-speed = <SATA_SPEED_GEN3>; 195 fsp,pmic-i2c-bus = <0>; 196 fsp,enable-isp; 197 fsp,isp-pci-dev-config = <ISP_PCI_DEV_CONFIG_2>; 198 fsp,pnp-settings = <PNP_SETTING_POWER_AND_PERF>; 199 fsp,sd-detect-chk; 200 }; 201 }; 202 203 microcode { 204 update@0 { 205#include "microcode/m01406c2220.dtsi" 206 }; 207 update@1 { 208#include "microcode/m01406c3363.dtsi" 209 }; 210 update@2 { 211#include "microcode/m01406c440a.dtsi" 212 }; 213 }; 214 215}; 216