README
1Overview
2--------
3The LS2080A Development System (QDS) is a high-performance computing,
4evaluation, and development platform that supports the QorIQ LS2080A
5and LS2088A Layerscape Architecture processor. The LS2080AQDS provides
6validation and SW development platform for the Freescale LS2080A, LS2088A
7processor series, with a complete debugging environment.
8
9LS2080A, LS2088A SoC Overview
10--------------------
11Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A,
12LS2088A SoC overview.
13
14 LS2080AQDS board Overview
15 -----------------------
16 - SERDES Connections, 16 lanes supporting:
17 - PCI Express - 3.0
18 - SGMII, SGMII 2.5
19 - QSGMII
20 - SATA 3.0
21 - XAUI
22 - XFI
23 - DDR Controller
24 - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four
25 chip-selects and two DIMM connectors. Support is up to 2133MT/s.
26 - One port of 40-bits (8-bits ECC) DDR4 which supports four chip-selects
27 and two DIMM connectors. Support is up to 1600MT/s.
28 -IFC/Local Bus
29 - IFC rev. 2.0 implementation supporting Little Endian connection scheme.
30 - One in-socket 128 MB NOR flash 16-bit data bus
31 - One 512 MB NAND flash with ECC support
32 - IFC Test Port
33 - PromJet Port
34 - FPGA connection
35 - USB 3.0
36 - Two high speed USB 3.0 ports
37 - First USB 3.0 port configured as Host with Type-A connector
38 - Second USB 3.0 port configured as OTG with micro-AB connector
39 - SDHC: PCIe x1 Right Angle connector for supporting following cards
40 - 1/4-/8-bit SD/MMC Legacy CARD supporting 3.3V devices only
41 - 1-/4-/8-bit SD/MMC Card supporting 1.8V devices only
42 - 4-bit eMMC Card Rev 4.4 (1.8V only)
43 - 8-bit eMMC Card Rev 4.5 (1.8V only)
44 - SD Card Rev 2.0 and Rev 3.0
45 - DSPI: 3 high-speed flash Memory for storage
46 - 16 MB high-speed flash Memory for boot code and storage (up to 108MHz)
47 - 8 MB high-speed flash Memory (up to 104 MHz)
48 - 512 MB low-speed flash Memory (up to 40 MHz)
49 - QSPI: via NAND/QSPI Card
50 - 4 I2C controllers
51 - Two SATA onboard connectors
52 - UART
53 - Two 4-pin (HW control) or four 2-pin (SW control) serial ports at up to 115.2 Kbit/s
54 - Two DB9 D-Type connectors supporting one Serial port each
55 - ARM JTAG support
56
57Memory map from core's view
58----------------------------
590x00_0000_0000 .. 0x00_000F_FFFF Boot Rom
600x00_0100_0000 .. 0x00_0FFF_FFFF CCSR
610x00_1800_0000 .. 0x00_181F_FFFF OCRAM
620x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1
630x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1
640x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2
650x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2
66
67Other addresses are either reserved, or not used directly by U-Boot.
68This list should be updated when more addresses are used.
69
70IFC region map from core's view
71-------------------------------
72During boot i.e. IFC Region #1:-
73 0x30000000 - 0x37ffffff : 128MB : NOR flash
74 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
75 0x3C000000 - 0x40000000 : 64MB : FPGA etc
76
77After relocate to DDR i.e. IFC Region #2:-
78 0x5_1000_0000..0x5_1fff_ffff Memory Hole
79 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
80 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
81 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
82 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
83
84Booting Options
85---------------
86a) Promjet Boot
87b) NOR boot
88c) NAND boot
89d) SD boot
90e) QSPI boot
91
92Memory map for NOR boot
93-------------------------
94Image Flash Offset
95RCW+PBI 0x00000000
96Boot firmware (U-Boot) 0x00100000
97Boot firmware Environment 0x00300000
98PPA firmware 0x00400000
99Secure Headers 0x00600000
100DPAA2 MC 0x00A00000
101DPAA2 DPL 0x00D00000
102DPAA2 DPC 0x00E00000
103Kernel.itb 0x01000000
104
105Memory map for SD boot
106-------------------------
107Image Flash Offset SD Card
108 Start Block No.
109RCW+PBI 0x00000000 0x00008
110Boot firmware (U-Boot) 0x00100000 0x00800
111Boot firmware Environment 0x00300000 0x01800
112PPA firmware 0x00400000 0x02000
113DPAA2 MC 0x00A00000 0x05000
114DPAA2 DPL 0x00D00000 0x06800
115DPAA2 DPC 0x00E00000 0x07000
116Kernel.itb 0x01000000 0x08000
117
118Environment Variables
119---------------------
120- mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined
121 the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
122
123- mcmemsize: MC DRAM block size. If this variable is not defined
124 the value CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
125
126Booting Linux flavors which do not support 48-bit VA (< Linux 3.18)
127-------------------------------------------------------------------
128One needs to use appropriate bootargs to boot Linux flavors which do
129not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown
130below:
131
132=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram
133 earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m
134 hugepages=16 mem=2048M'
135
136
137X-QSGMII-16PORT riser card
138----------------------------
139The X-QSGMII-16PORT is a 4xQSGMII/8xSGMII riser card with eighth SerDes
140interfaces implemented in PCIe form factor board.
141It supports following:
142 - Card can operate with up to 4 QSGMII lane simultaneously
143 - Card can operate with up to 8 SGMII lane simultaneously
144
145Supported card configuration
146 - CSEL : ON ON ON ON
147 - MSEL1 : ON ON ON ON OFF OFF OFF OFF
148 - MSEL2 : OFF OFF OFF OFF ON ON ON ON
149
150To enable this card: modify hwconfig to add "xqsgmii" variable.
151
152Supported PHY addresses during SGMII:
153#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
154#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
155#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
156#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
157#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
158#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
159#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
160#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
161
162Mapping DPMACx to PHY during SGMII
163DPMAC1 -> PHY1-P0
164DPMAC2 -> PHY2-P0
165DPMAC3 -> PHY3-P0
166DPMAC4 -> PHY4-P0
167DPMAC5 -> PHY3-P2
168DPMAC6 -> PHY1-P2
169DPMAC7 -> PHY4-P1
170DPMAC8 -> PHY2-P2
171DPMAC9 -> PHY1-P0
172DPMAC10 -> PHY2-P0
173DPMAC11 -> PHY3-P0
174DPMAC12 -> PHY4-P0
175DPMAC13 -> PHY3-P2
176DPMAC14 -> PHY1-P2
177DPMAC15 -> PHY4-P1
178DPMAC16 -> PHY2-P2
179
180
181Supported PHY address during QSGMII
182#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
183#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
184#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
185#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
186#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
187#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
188#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
189#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
190#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
191#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
192#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
193#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
194#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
195#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
196#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
197#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
198
199Mapping DPMACx to PHY during QSGMII
200DPMAC1 -> PHY1-P3
201DPMAC2 -> PHY1-P2
202DPMAC3 -> PHY1-P1
203DPMAC4 -> PHY1-P0
204DPMAC5 -> PHY2-P3
205DPMAC6 -> PHY2-P2
206DPMAC7 -> PHY2-P1
207DPMAC8 -> PHY2-P0
208DPMAC9 -> PHY3-P0
209DPMAC10 -> PHY3-P1
210DPMAC11 -> PHY3-P2
211DPMAC12 -> PHY3-P3
212DPMAC13 -> PHY4-P0
213DPMAC14 -> PHY4-P1
214DPMAC15 -> PHY4-P2
215DPMAC16 -> PHY4-P3
216
217