1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2009 4 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 5 */ 6 7 #ifndef _SYS_PROTO_H_ 8 #define _SYS_PROTO_H_ 9 10 #include <asm/io.h> 11 #include <asm/mach-imx/regs-common.h> 12 #include <asm/mach-imx/module_fuse.h> 13 #include <linux/bitops.h> 14 #include "../arch-imx/cpu.h" 15 16 struct bd_info; 17 18 #define soc_rev() (get_cpu_rev() & 0xFF) 19 #define is_soc_rev(rev) (soc_rev() == rev) 20 21 /* returns MXC_CPU_ value */ 22 #define cpu_type(rev) (((rev) >> 12) & 0x1ff) 23 #define soc_type(rev) (((rev) >> 12) & 0xf0) 24 /* both macros return/take MXC_CPU_ constants */ 25 #define get_cpu_type() (cpu_type(get_cpu_rev())) 26 #define get_soc_type() (soc_type(get_cpu_rev())) 27 #define is_cpu_type(cpu) (get_cpu_type() == cpu) 28 #define is_soc_type(soc) (get_soc_type() == soc) 29 30 #define is_mx6() (is_soc_type(MXC_SOC_MX6)) 31 #define is_mx7() (is_soc_type(MXC_SOC_MX7)) 32 #define is_imx8m() (is_soc_type(MXC_SOC_IMX8M)) 33 #define is_imx8() (is_soc_type(MXC_SOC_IMX8)) 34 #define is_imxrt() (is_soc_type(MXC_SOC_IMXRT)) 35 36 #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)) 37 #define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) 38 #define is_mx6sdl() (is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6DL)) 39 #define is_mx6dl() (is_cpu_type(MXC_CPU_MX6DL)) 40 #define is_mx6sx() (is_cpu_type(MXC_CPU_MX6SX)) 41 #define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL)) 42 #define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO)) 43 #define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL)) 44 #define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL) || is_cpu_type(MXC_CPU_MX6ULZ)) 45 #define is_mx6ulz() (is_cpu_type(MXC_CPU_MX6ULZ)) 46 #define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL)) 47 48 #define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP)) 49 50 #define is_imx8mq() (is_cpu_type(MXC_CPU_IMX8MQ) || is_cpu_type(MXC_CPU_IMX8MD) || is_cpu_type(MXC_CPU_IMX8MQL)) 51 #define is_imx8md() (is_cpu_type(MXC_CPU_IMX8MD)) 52 #define is_imx8mql() (is_cpu_type(MXC_CPU_IMX8MQL)) 53 #define is_imx8qm() (is_cpu_type(MXC_CPU_IMX8QM)) 54 #define is_imx8mm() (is_cpu_type(MXC_CPU_IMX8MM) || is_cpu_type(MXC_CPU_IMX8MML) ||\ 55 is_cpu_type(MXC_CPU_IMX8MMD) || is_cpu_type(MXC_CPU_IMX8MMDL) || \ 56 is_cpu_type(MXC_CPU_IMX8MMS) || is_cpu_type(MXC_CPU_IMX8MMSL)) 57 #define is_imx8mml() (is_cpu_type(MXC_CPU_IMX8MML)) 58 #define is_imx8mmd() (is_cpu_type(MXC_CPU_IMX8MMD)) 59 #define is_imx8mmdl() (is_cpu_type(MXC_CPU_IMX8MMDL)) 60 #define is_imx8mms() (is_cpu_type(MXC_CPU_IMX8MMS)) 61 #define is_imx8mmsl() (is_cpu_type(MXC_CPU_IMX8MMSL)) 62 #define is_imx8mn() (is_cpu_type(MXC_CPU_IMX8MN) || is_cpu_type(MXC_CPU_IMX8MND) || \ 63 is_cpu_type(MXC_CPU_IMX8MNS) || is_cpu_type(MXC_CPU_IMX8MNL) || \ 64 is_cpu_type(MXC_CPU_IMX8MNDL) || is_cpu_type(MXC_CPU_IMX8MNSL) || \ 65 is_cpu_type(MXC_CPU_IMX8MNUD) || is_cpu_type(MXC_CPU_IMX8MNUS) || is_cpu_type(MXC_CPU_IMX8MNUQ)) 66 #define is_imx8mnd() (is_cpu_type(MXC_CPU_IMX8MND)) 67 #define is_imx8mns() (is_cpu_type(MXC_CPU_IMX8MNS)) 68 #define is_imx8mnl() (is_cpu_type(MXC_CPU_IMX8MNL)) 69 #define is_imx8mndl() (is_cpu_type(MXC_CPU_IMX8MNDL)) 70 #define is_imx8mnsl() (is_cpu_type(MXC_CPU_IMX8MNSL)) 71 #define is_imx8mnuq() (is_cpu_type(MXC_CPU_IMX8MNUQ)) 72 #define is_imx8mnud() (is_cpu_type(MXC_CPU_IMX8MNUD)) 73 #define is_imx8mnus() (is_cpu_type(MXC_CPU_IMX8MNUS)) 74 #define is_imx8mp() (is_cpu_type(MXC_CPU_IMX8MP) || is_cpu_type(MXC_CPU_IMX8MPD) || \ 75 is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP6)) 76 #define is_imx8mpd() (is_cpu_type(MXC_CPU_IMX8MPD)) 77 #define is_imx8mpl() (is_cpu_type(MXC_CPU_IMX8MPL)) 78 #define is_imx8mp6() (is_cpu_type(MXC_CPU_IMX8MP6)) 79 80 #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP)) 81 82 #define is_imxrt1020() (is_cpu_type(MXC_CPU_IMXRT1020)) 83 #define is_imxrt1050() (is_cpu_type(MXC_CPU_IMXRT1050)) 84 85 #ifdef CONFIG_MX6 86 #define IMX6_SRC_GPR10_BMODE BIT(28) 87 #define IMX6_SRC_GPR10_PERSIST_SECONDARY_BOOT BIT(30) 88 89 #define IMX6_BMODE_MASK GENMASK(7, 0) 90 #define IMX6_BMODE_SHIFT 4 91 #define IMX6_BMODE_EMI_MASK BIT(3) 92 #define IMX6_BMODE_EMI_SHIFT 3 93 #define IMX6_BMODE_SERIAL_ROM_MASK GENMASK(26, 24) 94 #define IMX6_BMODE_SERIAL_ROM_SHIFT 24 95 96 enum imx6_bmode_serial_rom { 97 IMX6_BMODE_ECSPI1, 98 IMX6_BMODE_ECSPI2, 99 IMX6_BMODE_ECSPI3, 100 IMX6_BMODE_ECSPI4, 101 IMX6_BMODE_ECSPI5, 102 IMX6_BMODE_I2C1, 103 IMX6_BMODE_I2C2, 104 IMX6_BMODE_I2C3, 105 }; 106 107 enum imx6_bmode_emi { 108 IMX6_BMODE_NOR, 109 IMX6_BMODE_ONENAND, 110 }; 111 112 enum imx6_bmode { 113 IMX6_BMODE_EMI, 114 #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) 115 IMX6_BMODE_QSPI, 116 IMX6_BMODE_RESERVED, 117 #else 118 IMX6_BMODE_RESERVED, 119 IMX6_BMODE_SATA, 120 #endif 121 IMX6_BMODE_SERIAL_ROM, 122 IMX6_BMODE_SD, 123 IMX6_BMODE_ESD, 124 IMX6_BMODE_MMC, 125 IMX6_BMODE_EMMC, 126 IMX6_BMODE_NAND_MIN, 127 IMX6_BMODE_NAND_MAX = 0xf, 128 }; 129 130 u32 imx6_src_get_boot_mode(void); 131 void gpr_init(void); 132 133 #endif /* CONFIG_MX6 */ 134 135 #ifdef CONFIG_MX7 136 #define IMX7_SRC_GPR10_BMODE BIT(28) 137 #define IMX7_SRC_GPR10_PERSIST_SECONDARY_BOOT BIT(30) 138 #endif 139 140 /* address translation table */ 141 struct rproc_att { 142 u32 da; /* device address (From Cortex M4 view) */ 143 u32 sa; /* system bus address */ 144 u32 size; /* size of reg range */ 145 }; 146 147 #ifdef CONFIG_IMX8M 148 struct rom_api { 149 u16 ver; 150 u16 tag; 151 u32 reserved1; 152 u32 (*download_image)(u8 *dest, u32 offset, u32 size, u32 xor); 153 u32 (*query_boot_infor)(u32 info_type, u32 *info, u32 xor); 154 }; 155 156 enum boot_dev_type_e { 157 BT_DEV_TYPE_SD = 1, 158 BT_DEV_TYPE_MMC = 2, 159 BT_DEV_TYPE_NAND = 3, 160 BT_DEV_TYPE_FLEXSPINOR = 4, 161 162 BT_DEV_TYPE_USB = 0xE, 163 BT_DEV_TYPE_MEM_DEV = 0xF, 164 165 BT_DEV_TYPE_INVALID = 0xFF 166 }; 167 168 #define QUERY_ROM_VER 1 169 #define QUERY_BT_DEV 2 170 #define QUERY_PAGE_SZ 3 171 #define QUERY_IVT_OFF 4 172 #define QUERY_BT_STAGE 5 173 #define QUERY_IMG_OFF 6 174 175 #define ROM_API_OKAY 0xF0 176 177 extern struct rom_api *g_rom_api; 178 #endif 179 180 u32 get_nr_cpus(void); 181 u32 get_cpu_rev(void); 182 u32 get_cpu_speed_grade_hz(void); 183 u32 get_cpu_temp_grade(int *minc, int *maxc); 184 const char *get_imx_type(u32 imxtype); 185 u32 imx_ddr_size(void); 186 void sdelay(unsigned long); 187 void set_chipselect_size(int const); 188 189 void init_aips(void); 190 void init_src(void); 191 void init_snvs(void); 192 void imx_wdog_disable_powerdown(void); 193 194 void board_mem_get_layout(u64 *phys_sdram_1_start, 195 u64 *phys_sdram_1_size, 196 u64 *phys_sdram_2_start, 197 u64 *phys_sdram_2_size); 198 199 int arch_auxiliary_core_check_up(u32 core_id); 200 201 int board_mmc_get_env_dev(int devno); 202 203 int nxp_board_rev(void); 204 char nxp_board_rev_string(void); 205 206 /* 207 * Initializes on-chip ethernet controllers. 208 * to override, implement board_eth_init() 209 */ 210 int fecmxc_initialize(struct bd_info *bis); 211 u32 get_ahb_clk(void); 212 u32 get_periph_clk(void); 213 214 void lcdif_power_down(void); 215 216 int mxs_reset_block(struct mxs_register_32 *reg); 217 int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout); 218 int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout); 219 220 unsigned long call_imx_sip(unsigned long id, unsigned long reg0, 221 unsigned long reg1, unsigned long reg2, 222 unsigned long reg3); 223 unsigned long call_imx_sip_ret2(unsigned long id, unsigned long reg0, 224 unsigned long *reg1, unsigned long reg2, 225 unsigned long reg3); 226 227 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); 228 #endif 229