1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * P2020 Silicon/SoC Device Tree Source (post include)
4 *
5 * Copyright 2013 Freescale Semiconductor Inc.
6 * Copyright 2019 NXP
7 */
8
9&soc {
10	#address-cells = <1>;
11	#size-cells = <1>;
12	device_type = "soc";
13	compatible = "fsl,p2020-immr", "simple-bus";
14	bus-frequency = <0x0>;
15
16	usb@22000 {
17		compatible = "fsl-usb2-dr";
18		reg = <0x22000 0x1000>;
19		phy_type = "ulpi";
20	};
21
22	mpic: pic@40000 {
23		interrupt-controller;
24		#address-cells = <0>;
25		#interrupt-cells = <4>;
26		reg = <0x40000 0x40000>;
27		compatible = "fsl,mpic";
28		device_type = "open-pic";
29		big-endian;
30		single-cpu-affinity;
31		last-interrupt-source = <255>;
32	};
33
34	esdhc: esdhc@2e000 {
35		compatible = "fsl,esdhc";
36		reg = <0x2e000 0x1000>;
37		/* Filled in by U-Boot */
38		clock-frequency = <0>;
39	};
40
41	espi0: spi@7000 {
42		compatible = "fsl,mpc8536-espi";
43		#address-cells = <1>;
44		#size-cells = <0>;
45		reg = <0x7000 0x1000>;
46		fsl,espi-num-chipselects = <4>;
47		status = "disabled";
48	};
49
50/include/ "pq3-i2c-0.dtsi"
51/include/ "pq3-i2c-1.dtsi"
52
53/include/ "pq3-etsec1-0.dtsi"
54/include/ "pq3-etsec1-1.dtsi"
55/include/ "pq3-etsec1-2.dtsi"
56};
57
58/* PCIe controller base address 0x8000 */
59&pci2 {
60	compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
61	law_trgt_if = <0>;
62	#address-cells = <3>;
63	#size-cells = <2>;
64	device_type = "pci";
65	bus-range = <0x0 0xff>;
66};
67
68/* PCIe controller base address 0x9000 */
69&pci1 {
70	compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
71	law_trgt_if = <1>;
72	#address-cells = <3>;
73	#size-cells = <2>;
74	device_type = "pci";
75	bus-range = <0x0 0xff>;
76};
77
78/* PCIe controller base address 0xa000 */
79&pci0 {
80	compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
81	law_trgt_if = <2>;
82	#address-cells = <3>;
83	#size-cells = <2>;
84	device_type = "pci";
85	bus-range = <0x0 0xff>;
86};
87