1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2014 Soeren Moch <smoch@web.de>
4  */
5 
6 #include <init.h>
7 #include <asm/arch/clock.h>
8 #include <asm/arch/imx-regs.h>
9 #include <asm/arch/iomux.h>
10 #include <asm/arch/mx6-pins.h>
11 #include <asm/global_data.h>
12 #include <linux/errno.h>
13 #include <asm/gpio.h>
14 #include <asm/mach-imx/iomux-v3.h>
15 #include <asm/mach-imx/boot_mode.h>
16 #include <asm/mach-imx/video.h>
17 #include <mmc.h>
18 #include <fsl_esdhc_imx.h>
19 #include <asm/arch/mxc_hdmi.h>
20 #include <asm/arch/crm_regs.h>
21 #include <asm/io.h>
22 #include <asm/arch/sys_proto.h>
23 DECLARE_GLOBAL_DATA_PTR;
24 
25 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
26 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
27 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
28 
29 static iomux_v3_cfg_t const uart1_pads[] = {
30 	MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
31 	MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
32 };
33 
34 static iomux_v3_cfg_t const uart2_pads[] = {
35 	MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
36 	MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
37 };
38 
dram_init(void)39 int dram_init(void)
40 {
41 	gd->ram_size = 2048ul * 1024 * 1024;
42 	return 0;
43 }
44 
setup_iomux_uart(void)45 static void setup_iomux_uart(void)
46 {
47 	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
48 	imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
49 }
50 
51 #ifdef CONFIG_FSL_ESDHC_IMX
52 /* set environment device to boot device when booting from SD */
board_mmc_get_env_dev(int devno)53 int board_mmc_get_env_dev(int devno)
54 {
55 	return devno - 1;
56 }
57 
board_mmc_get_env_part(int devno)58 int board_mmc_get_env_part(int devno)
59 {
60 	return (devno == 3) ? 1 : 0; /* part 0 for SD2 / SD3, part 1 for eMMC */
61 }
62 #endif /* CONFIG_FSL_ESDHC_IMX */
63 
64 #ifdef CONFIG_VIDEO_IPUV3
do_enable_hdmi(struct display_info_t const * dev)65 static void do_enable_hdmi(struct display_info_t const *dev)
66 {
67 	imx_enable_hdmi_phy();
68 }
69 
70 struct display_info_t const displays[] = {{
71 	.bus	= -1,
72 	.addr	= 0,
73 	.pixfmt	= IPU_PIX_FMT_RGB24,
74 	.detect	= detect_hdmi,
75 	.enable	= do_enable_hdmi,
76 	.mode	= {
77 		.name           = "HDMI",
78 		/* 1024x768@60Hz (VESA)*/
79 		.refresh        = 60,
80 		.xres           = 1024,
81 		.yres           = 768,
82 		.pixclock       = 15384,
83 		.left_margin    = 160,
84 		.right_margin   = 24,
85 		.upper_margin   = 29,
86 		.lower_margin   = 3,
87 		.hsync_len      = 136,
88 		.vsync_len      = 6,
89 		.sync           = FB_SYNC_EXT,
90 		.vmode          = FB_VMODE_NONINTERLACED
91 } } };
92 size_t display_count = ARRAY_SIZE(displays);
93 
setup_display(void)94 static void setup_display(void)
95 {
96 	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
97 	int reg;
98 	s32 timeout = 100000;
99 
100 	enable_ipu_clock();
101 	imx_setup_hdmi();
102 
103 	/* set video pll to 455MHz (24MHz * (37+11/12) / 2) */
104 	reg = readl(&ccm->analog_pll_video);
105 	reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
106 	writel(reg, &ccm->analog_pll_video);
107 
108 	reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
109 	reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37);
110 	reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
111 	reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1);
112 	writel(reg, &ccm->analog_pll_video);
113 
114 	writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
115 	writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
116 
117 	reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
118 	writel(reg, &ccm->analog_pll_video);
119 
120 	while (timeout--)
121 		if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
122 			break;
123 	if (timeout < 0)
124 		printf("Warning: video pll lock timeout!\n");
125 
126 	reg = readl(&ccm->analog_pll_video);
127 	reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
128 	reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
129 	writel(reg, &ccm->analog_pll_video);
130 
131 	/* gate ipu1_di0_clk */
132 	reg = readl(&ccm->CCGR3);
133 	reg &= ~MXC_CCM_CCGR3_LDB_DI0_MASK;
134 	writel(reg, &ccm->CCGR3);
135 
136 	/* select video_pll clock / 7  for ipu1_di0_clk -> 65MHz pixclock */
137 	reg = readl(&ccm->chsccdr);
138 	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
139 		 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
140 		 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
141 	reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) |
142 	       (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
143 	       (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
144 	writel(reg, &ccm->chsccdr);
145 
146 	/* enable ipu1_di0_clk */
147 	reg = readl(&ccm->CCGR3);
148 	reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
149 	writel(reg, &ccm->CCGR3);
150 }
151 #endif /* CONFIG_VIDEO_IPUV3 */
152 
board_early_init_f(void)153 int board_early_init_f(void)
154 {
155 	setup_iomux_uart();
156 	return 0;
157 }
158 
159 #ifdef CONFIG_CMD_BMODE
160 static const struct boot_mode board_boot_modes[] = {
161 	/* 4 bit bus width */
162 	{"sd2",	 MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
163 	{"sd3",	 MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
164 	/* 8 bit bus width */
165 	{"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
166 	{NULL,	 0},
167 };
168 #endif
169 
board_init(void)170 int board_init(void)
171 {
172 	/* address of boot parameters */
173 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
174 
175 #ifdef CONFIG_VIDEO_IPUV3
176 	setup_display();
177 #endif
178 #ifdef CONFIG_CMD_BMODE
179 	add_board_boot_modes(board_boot_modes);
180 #endif
181 	return 0;
182 }
183