1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2017-2019 Intel Corporation <www.intel.com> 4 */ 5 6 #ifndef _SDRAM_SOC64_H_ 7 #define _SDRAM_SOC64_H_ 8 9 #include <common.h> 10 #include <linux/sizes.h> 11 12 struct altera_sdram_priv { 13 struct ram_info info; 14 struct reset_ctl_bulk resets; 15 }; 16 17 struct altera_sdram_plat { 18 void __iomem *hmc; 19 void __iomem *ddr_sch; 20 void __iomem *iomhc; 21 }; 22 23 /* ECC HMC registers */ 24 #define DDRIOCTRL 0x8 25 #define DDRCALSTAT 0xc 26 #define DRAMADDRWIDTH 0xe0 27 #define ECCCTRL1 0x100 28 #define ECCCTRL2 0x104 29 #define ERRINTEN 0x110 30 #define ERRINTENS 0x114 31 #define INTMODE 0x11c 32 #define INTSTAT 0x120 33 #define AUTOWB_CORRADDR 0x138 34 #define ECC_REG2WRECCDATABUS 0x144 35 #define ECC_DIAGON 0x150 36 #define ECC_DECSTAT 0x154 37 #define HPSINTFCSEL 0x210 38 #define RSTHANDSHAKECTRL 0x214 39 #define RSTHANDSHAKESTAT 0x218 40 41 #define DDR_HMC_DDRIOCTRL_IOSIZE_MSK 0x00000003 42 #define DDR_HMC_DDRCALSTAT_CAL_MSK BIT(0) 43 #define DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK BIT(16) 44 #define DDR_HMC_ECCCTL_CNT_RST_SET_MSK BIT(8) 45 #define DDR_HMC_ECCCTL_ECC_EN_SET_MSK BIT(0) 46 #define DDR_HMC_ECCCTL2_RMW_EN_SET_MSK BIT(8) 47 #define DDR_HMC_ECCCTL2_AWB_EN_SET_MSK BIT(0) 48 #define DDR_HMC_ECC_DIAGON_ECCDIAGON_EN_SET_MSK BIT(16) 49 #define DDR_HMC_ECC_DIAGON_WRDIAGON_EN_SET_MSK BIT(0) 50 #define DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK BIT(0) 51 #define DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK BIT(1) 52 #define DDR_HMC_INTSTAT_SERRPENA_SET_MSK BIT(0) 53 #define DDR_HMC_INTSTAT_DERRPENA_SET_MSK BIT(1) 54 #define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK BIT(16) 55 #define DDR_HMC_INTMODE_INTMODE_SET_MSK BIT(0) 56 #define DDR_HMC_RSTHANDSHAKE_MASK 0x000000ff 57 #define DDR_HMC_CORE2SEQ_INT_REQ 0xF 58 #define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3) 59 #define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f 60 61 #define DDR_HMC_ERRINTEN_INTMASK \ 62 (DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK | \ 63 DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK) 64 65 /* HMC MMR IO48 registers */ 66 #define CTRLCFG0 0x28 67 #define CTRLCFG1 0x2c 68 #define CTRLCFG3 0x34 69 #define DRAMTIMING0 0x50 70 #define CALTIMING0 0x7c 71 #define CALTIMING1 0x80 72 #define CALTIMING2 0x84 73 #define CALTIMING3 0x88 74 #define CALTIMING4 0x8c 75 #define CALTIMING9 0xa0 76 #define DRAMADDRW 0xa8 77 #define DRAMSTS 0xec 78 #define NIOSRESERVED0 0x110 79 #define NIOSRESERVED1 0x114 80 #define NIOSRESERVED2 0x118 81 82 #define DRAMADDRW_CFG_COL_ADDR_WIDTH(x) \ 83 (((x) >> 0) & 0x1F) 84 #define DRAMADDRW_CFG_ROW_ADDR_WIDTH(x) \ 85 (((x) >> 5) & 0x1F) 86 #define DRAMADDRW_CFG_BANK_ADDR_WIDTH(x) \ 87 (((x) >> 10) & 0xF) 88 #define DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(x) \ 89 (((x) >> 14) & 0x3) 90 #define DRAMADDRW_CFG_CS_ADDR_WIDTH(x) \ 91 (((x) >> 16) & 0x7) 92 93 #define CTRLCFG0_CFG_MEMTYPE(x) \ 94 (((x) >> 0) & 0xF) 95 #define CTRLCFG0_CFG_DIMM_TYPE(x) \ 96 (((x) >> 4) & 0x7) 97 #define CTRLCFG0_CFG_AC_POS(x) \ 98 (((x) >> 7) & 0x3) 99 #define CTRLCFG0_CFG_CTRL_BURST_LEN(x) \ 100 (((x) >> 9) & 0x1F) 101 102 #define CTRLCFG1_CFG_DBC3_BURST_LEN(x) \ 103 (((x) >> 0) & 0x1F) 104 #define CTRLCFG1_CFG_ADDR_ORDER(x) \ 105 (((x) >> 5) & 0x3) 106 #define CTRLCFG1_CFG_CTRL_EN_ECC(x) \ 107 (((x) >> 7) & 0x1) 108 109 #define DRAMTIMING0_CFG_TCL(x) \ 110 (((x) >> 0) & 0x7F) 111 112 #define CALTIMING0_CFG_ACT_TO_RDWR(x) \ 113 (((x) >> 0) & 0x3F) 114 #define CALTIMING0_CFG_ACT_TO_PCH(x) \ 115 (((x) >> 6) & 0x3F) 116 #define CALTIMING0_CFG_ACT_TO_ACT(x) \ 117 (((x) >> 12) & 0x3F) 118 #define CALTIMING0_CFG_ACT_TO_ACT_DB(x) \ 119 (((x) >> 18) & 0x3F) 120 121 #define CALTIMING1_CFG_RD_TO_RD(x) \ 122 (((x) >> 0) & 0x3F) 123 #define CALTIMING1_CFG_RD_TO_RD_DC(x) \ 124 (((x) >> 6) & 0x3F) 125 #define CALTIMING1_CFG_RD_TO_RD_DB(x) \ 126 (((x) >> 12) & 0x3F) 127 #define CALTIMING1_CFG_RD_TO_WR(x) \ 128 (((x) >> 18) & 0x3F) 129 #define CALTIMING1_CFG_RD_TO_WR_DC(x) \ 130 (((x) >> 24) & 0x3F) 131 132 #define CALTIMING2_CFG_RD_TO_WR_DB(x) \ 133 (((x) >> 0) & 0x3F) 134 #define CALTIMING2_CFG_RD_TO_WR_PCH(x) \ 135 (((x) >> 6) & 0x3F) 136 #define CALTIMING2_CFG_RD_AP_TO_VALID(x) \ 137 (((x) >> 12) & 0x3F) 138 #define CALTIMING2_CFG_WR_TO_WR(x) \ 139 (((x) >> 18) & 0x3F) 140 #define CALTIMING2_CFG_WR_TO_WR_DC(x) \ 141 (((x) >> 24) & 0x3F) 142 143 #define CALTIMING3_CFG_WR_TO_WR_DB(x) \ 144 (((x) >> 0) & 0x3F) 145 #define CALTIMING3_CFG_WR_TO_RD(x) \ 146 (((x) >> 6) & 0x3F) 147 #define CALTIMING3_CFG_WR_TO_RD_DC(x) \ 148 (((x) >> 12) & 0x3F) 149 #define CALTIMING3_CFG_WR_TO_RD_DB(x) \ 150 (((x) >> 18) & 0x3F) 151 #define CALTIMING3_CFG_WR_TO_PCH(x) \ 152 (((x) >> 24) & 0x3F) 153 154 #define CALTIMING4_CFG_WR_AP_TO_VALID(x) \ 155 (((x) >> 0) & 0x3F) 156 #define CALTIMING4_CFG_PCH_TO_VALID(x) \ 157 (((x) >> 6) & 0x3F) 158 #define CALTIMING4_CFG_PCH_ALL_TO_VALID(x) \ 159 (((x) >> 12) & 0x3F) 160 #define CALTIMING4_CFG_ARF_TO_VALID(x) \ 161 (((x) >> 18) & 0xFF) 162 #define CALTIMING4_CFG_PDN_TO_VALID(x) \ 163 (((x) >> 26) & 0x3F) 164 165 #define CALTIMING9_CFG_4_ACT_TO_ACT(x) \ 166 (((x) >> 0) & 0xFF) 167 168 /* Firewall DDR scheduler MPFE */ 169 #define FW_HMC_ADAPTOR_REG_ADDR 0xf8020004 170 #define FW_HMC_ADAPTOR_MPU_MASK BIT(0) 171 172 u32 hmc_readl(struct altera_sdram_plat *plat, u32 reg); 173 u32 hmc_ecc_readl(struct altera_sdram_plat *plat, u32 reg); 174 u32 hmc_ecc_writel(struct altera_sdram_plat *plat, 175 u32 data, u32 reg); 176 u32 ddr_sch_writel(struct altera_sdram_plat *plat, u32 data, 177 u32 reg); 178 int emif_clear(struct altera_sdram_plat *plat); 179 int emif_reset(struct altera_sdram_plat *plat); 180 int poll_hmc_clock_status(void); 181 void sdram_clear_mem(phys_addr_t addr, phys_size_t size); 182 void sdram_init_ecc_bits(struct bd_info *bd); 183 void sdram_size_check(struct bd_info *bd); 184 phys_size_t sdram_calculate_size(struct altera_sdram_plat *plat); 185 int sdram_mmr_init_full(struct udevice *dev); 186 187 #endif /* _SDRAM_SOC64_H_ */ 188