1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2019 Marvell International Ltd.
4 */
5
6 #include <clk.h>
7 #include <cpu_func.h>
8 #include <dm.h>
9 #include <dm/device-internal.h>
10 #include <dm/lists.h>
11 #include <env.h>
12 #include <errno.h>
13 #include <fdtdec.h>
14 #include <log.h>
15 #include <malloc.h>
16 #include <memalign.h>
17 #include <mmc.h>
18 #include <part.h>
19 #include <pci.h>
20 #include <pci_ids.h>
21 #include <power/regulator.h>
22 #include <time.h>
23 #include <watchdog.h>
24 #include <asm/io.h>
25 #include <linux/delay.h>
26 #include <linux/kernel.h>
27 #include <linux/libfdt.h>
28
29 #if defined(CONFIG_ARCH_OCTEON)
30 #include <mach/octeon-model.h>
31 #include <mach/cvmx-regs.h>
32 #include <mach/cvmx-mio-emm-defs.h>
33 #else
34 #include <asm/arch/board.h>
35 #include <asm/arch/clock.h>
36 #include <asm/arch/csrs/csrs-mio_emm.h>
37 #endif
38
39 #include "octeontx_hsmmc.h"
40
41 /* Use dummy implementation for MIPS Octeon to always return false */
42 #if defined(CONFIG_ARCH_OCTEON)
43 #define otx_is_soc(ver) 0
44 #endif
45
46 #define MMC_TIMEOUT_SHORT 20 /* in ms */
47 #define MMC_TIMEOUT_LONG 1000
48 #define MMC_TIMEOUT_ERASE 10000
49
50 #define MMC_DEFAULT_DATA_IN_TAP 10
51 #define MMC_DEFAULT_CMD_IN_TAP 10
52 #define MMC_DEFAULT_CMD_OUT_TAP 39
53 #define MMC_DEFAULT_DATA_OUT_TAP 39
54 #define MMC_DEFAULT_HS200_CMD_IN_TAP 24
55 #define MMC_DEFAULT_HS200_DATA_IN_TAP 24
56 #define MMC_DEFAULT_HS200_CMD_OUT_TAP (otx_is_soc(CN95XX) ? 10 : 5)
57 #define MMC_DEFAULT_HS200_DATA_OUT_TAP (otx_is_soc(CN95XX) ? 10 : 5)
58 #define MMC_DEFAULT_HS400_CMD_OUT_TAP (otx_is_soc(CN95XX) ? 10 : 5)
59 #define MMC_DEFAULT_HS400_DATA_OUT_TAP (otx_is_soc(CN95XX) ? 5 : 3)
60 #define MMC_DEFAULT_HS200_CMD_OUT_DLY 800 /* Delay in ps */
61 #define MMC_DEFAULT_HS200_DATA_OUT_DLY 800 /* Delay in ps */
62 #define MMC_DEFAULT_HS400_CMD_OUT_DLY 800 /* Delay in ps */
63 #define MMC_DEFAULT_HS400_DATA_OUT_DLY 400 /* Delay in ps */
64 #define MMC_DEFAULT_SD_UHS_SDR104_CMD_OUT_TAP MMC_DEFAULT_HS200_CMD_OUT_TAP
65 #define MMC_DEFAULT_SD_UHS_SDR104_DATA_OUT_TAP MMC_DEFAULT_HS200_DATA_OUT_TAP
66 #define MMC_LEGACY_DEFAULT_CMD_OUT_TAP 39
67 #define MMC_LEGACY_DEFAULT_DATA_OUT_TAP 39
68 #define MMC_SD_LEGACY_DEFAULT_CMD_OUT_TAP 63
69 #define MMC_SD_LEGACY_DEFAULT_DATA_OUT_TAP 63
70 #define MMC_HS_CMD_OUT_TAP 32
71 #define MMC_HS_DATA_OUT_TAP 32
72 #define MMC_SD_HS_CMD_OUT_TAP 26
73 #define MMC_SD_HS_DATA_OUT_TAP 26
74 #define MMC_SD_UHS_SDR25_CMD_OUT_TAP 26
75 #define MMC_SD_UHS_SDR25_DATA_OUT_TAP 26
76 #define MMC_SD_UHS_SDR50_CMD_OUT_TAP 26
77 #define MMC_SD_UHS_SDR50_DATA_OUT_TAP 26
78 #define MMC_DEFAULT_TAP_DELAY 4
79 #define TOTAL_NO_OF_TAPS 512
80 static void octeontx_mmc_switch_to(struct mmc *mmc);
81 static void set_wdog(struct mmc *mmc, u64 us);
82 static void do_switch(struct mmc *mmc, union mio_emm_switch emm_switch);
83 static int octeontx_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
84 struct mmc_data *data);
85 static int octeontx_mmc_configure_delay(struct mmc *mmc);
86 static int octeontx_mmc_calibrate_delay(struct mmc *mmc);
87 #if !defined(CONFIG_ARCH_OCTEON)
88 static int octeontx2_mmc_calc_delay(struct mmc *mmc, int delay);
89 static void octeontx_mmc_set_timing(struct mmc *mmc);
90 static int octeontx_mmc_set_input_bus_timing(struct mmc *mmc);
91 static int octeontx_mmc_set_output_bus_timing(struct mmc *mmc);
92 #endif
93
94 static bool host_probed;
95
96 /**
97 * Get the slot data structure from a MMC data structure
98 */
mmc_to_slot(struct mmc * mmc)99 static inline struct octeontx_mmc_slot *mmc_to_slot(struct mmc *mmc)
100 {
101 return container_of(mmc, struct octeontx_mmc_slot, mmc);
102 }
103
mmc_to_host(struct mmc * mmc)104 static inline struct octeontx_mmc_host *mmc_to_host(struct mmc *mmc)
105 {
106 return mmc_to_slot(mmc)->host;
107 }
108
dev_to_mmc_slot(struct udevice * dev)109 static inline struct octeontx_mmc_slot *dev_to_mmc_slot(struct udevice *dev)
110 {
111 return dev_get_priv(dev);
112 }
113
dev_to_mmc(struct udevice * dev)114 static inline struct mmc *dev_to_mmc(struct udevice *dev)
115 {
116 return &((struct octeontx_mmc_slot *)dev_get_priv(dev))->mmc;
117 }
118
119 #ifdef DEBUG
mmc_reg_str(u64 reg)120 const char *mmc_reg_str(u64 reg)
121 {
122 if (reg == MIO_EMM_DMA_CFG())
123 return "MIO_EMM_DMA_CFG";
124 if (reg == MIO_EMM_DMA_ADR())
125 return "MIO_EMM_DMA_ADR";
126 if (reg == MIO_EMM_DMA_INT())
127 return "MIO_EMM_DMA_INT";
128 if (reg == MIO_EMM_CFG())
129 return "MIO_EMM_CFG";
130 if (reg == MIO_EMM_MODEX(0))
131 return "MIO_EMM_MODE0";
132 if (reg == MIO_EMM_MODEX(1))
133 return "MIO_EMM_MODE1";
134 if (reg == MIO_EMM_MODEX(2))
135 return "MIO_EMM_MODE2";
136 if (reg == MIO_EMM_MODEX(3))
137 return "MIO_EMM_MODE3";
138 if (reg == MIO_EMM_IO_CTL())
139 return "MIO_EMM_IO_CTL";
140 if (reg == MIO_EMM_SWITCH())
141 return "MIO_EMM_SWITCH";
142 if (reg == MIO_EMM_DMA())
143 return "MIO_EMM_DMA";
144 if (reg == MIO_EMM_CMD())
145 return "MIO_EMM_CMD";
146 if (reg == MIO_EMM_RSP_STS())
147 return "MIO_EMM_RSP_STS";
148 if (reg == MIO_EMM_RSP_LO())
149 return "MIO_EMM_RSP_LO";
150 if (reg == MIO_EMM_RSP_HI())
151 return "MIO_EMM_RSP_HI";
152 if (reg == MIO_EMM_INT())
153 return "MIO_EMM_INT";
154 if (reg == MIO_EMM_WDOG())
155 return "MIO_EMM_WDOG";
156 if (reg == MIO_EMM_DMA_ARG())
157 return "MIO_EMM_DMA_ARG";
158 if (IS_ENABLED(CONFIG_ARCH_OCTEONTX)) {
159 if (reg == MIO_EMM_SAMPLE())
160 return "MIO_EMM_SAMPLE";
161 }
162 if (reg == MIO_EMM_STS_MASK())
163 return "MIO_EMM_STS_MASK";
164 if (reg == MIO_EMM_RCA())
165 return "MIO_EMM_RCA";
166 if (reg == MIO_EMM_BUF_IDX())
167 return "MIO_EMM_BUF_IDX";
168 if (reg == MIO_EMM_BUF_DAT())
169 return "MIO_EMM_BUF_DAT";
170 if (!IS_ENABLED(CONFIG_ARCH_OCTEONTX)) {
171 if (reg == MIO_EMM_CALB())
172 return "MIO_EMM_CALB";
173 if (reg == MIO_EMM_TAP())
174 return "MIO_EMM_TAP";
175 if (reg == MIO_EMM_TIMING())
176 return "MIO_EMM_TIMING";
177 if (reg == MIO_EMM_DEBUG())
178 return "MIO_EMM_DEBUG";
179 }
180
181 return "UNKNOWN";
182 }
183 #endif
184
octeontx_print_rsp_sts(struct mmc * mmc)185 static void octeontx_print_rsp_sts(struct mmc *mmc)
186 {
187 #ifdef DEBUG
188 union mio_emm_rsp_sts emm_rsp_sts;
189 const struct octeontx_mmc_host *host = mmc_to_host(mmc);
190 static const char * const ctype_xor_str[] = {
191 "No data",
192 "Read data into Dbuf",
193 "Write data from Dbuf",
194 "Reserved"
195 };
196
197 static const char * const rtype_xor_str[] = {
198 "No response",
199 "R1, 48 bits",
200 "R2, 136 bits",
201 "R3, 48 bits",
202 "R4, 48 bits",
203 "R5, 48 bits",
204 "Reserved 6",
205 "Reserved 7"
206 };
207
208 emm_rsp_sts.u = readq(host->base_addr + MIO_EMM_RSP_STS());
209 printf("\nMIO_EMM_RSP_STS: 0x%016llx\n", emm_rsp_sts.u);
210 printf(" 60-61: bus_id: %u\n", emm_rsp_sts.s.bus_id);
211 printf(" 59: cmd_val: %s\n",
212 emm_rsp_sts.s.cmd_val ? "yes" : "no");
213 printf(" 58: switch_val: %s\n",
214 emm_rsp_sts.s.switch_val ? "yes" : "no");
215 printf(" 57: dma_val: %s\n",
216 emm_rsp_sts.s.dma_val ? "yes" : "no");
217 printf(" 56: dma_pend: %s\n",
218 emm_rsp_sts.s.dma_pend ? "yes" : "no");
219 printf(" 28: dbuf_err: %s\n",
220 emm_rsp_sts.s.dbuf_err ? "yes" : "no");
221 printf(" 23: dbuf: %u\n", emm_rsp_sts.s.dbuf);
222 printf(" 22: blk_timeout: %s\n",
223 emm_rsp_sts.s.blk_timeout ? "yes" : "no");
224 printf(" 21: blk_crc_err: %s\n",
225 emm_rsp_sts.s.blk_crc_err ? "yes" : "no");
226 printf(" 20: rsp_busybit: %s\n",
227 emm_rsp_sts.s.rsp_busybit ? "yes" : "no");
228 printf(" 19: stp_timeout: %s\n",
229 emm_rsp_sts.s.stp_timeout ? "yes" : "no");
230 printf(" 18: stp_crc_err: %s\n",
231 emm_rsp_sts.s.stp_crc_err ? "yes" : "no");
232 printf(" 17: stp_bad_sts: %s\n",
233 emm_rsp_sts.s.stp_bad_sts ? "yes" : "no");
234 printf(" 16: stp_val: %s\n",
235 emm_rsp_sts.s.stp_val ? "yes" : "no");
236 printf(" 15: rsp_timeout: %s\n",
237 emm_rsp_sts.s.rsp_timeout ? "yes" : "no");
238 printf(" 14: rsp_crc_err: %s\n",
239 emm_rsp_sts.s.rsp_crc_err ? "yes" : "no");
240 printf(" 13: rsp_bad_sts: %s\n",
241 emm_rsp_sts.s.rsp_bad_sts ? "yes" : "no");
242 printf(" 12: rsp_val: %s\n",
243 emm_rsp_sts.s.rsp_val ? "yes" : "no");
244 printf(" 9-11: rsp_type: %s\n",
245 rtype_xor_str[emm_rsp_sts.s.rsp_type]);
246 printf(" 7-8: cmd_type: %s\n",
247 ctype_xor_str[emm_rsp_sts.s.cmd_type]);
248 printf(" 1-6: cmd_idx: %u\n",
249 emm_rsp_sts.s.cmd_idx);
250 printf(" 0: cmd_done: %s\n",
251 emm_rsp_sts.s.cmd_done ? "yes" : "no");
252 #endif
253 }
254
read_csr(struct mmc * mmc,u64 reg)255 static inline u64 read_csr(struct mmc *mmc, u64 reg)
256 {
257 const struct octeontx_mmc_host *host = mmc_to_host(mmc);
258 u64 value = readq(host->base_addr + reg);
259 #ifdef DEBUG_CSR
260 printf(" %s: %s(0x%p) => 0x%llx\n", __func__,
261 mmc_reg_str(reg), host->base_addr + reg,
262 value);
263 #endif
264 return value;
265 }
266
267 /**
268 * Writes to a CSR register
269 *
270 * @param[in] mmc pointer to mmc data structure
271 * @param reg register offset
272 * @param value value to write to register
273 */
write_csr(struct mmc * mmc,u64 reg,u64 value)274 static inline void write_csr(struct mmc *mmc, u64 reg, u64 value)
275 {
276 const struct octeontx_mmc_host *host = mmc_to_host(mmc);
277 void *addr = host->base_addr + reg;
278
279 #ifdef DEBUG_CSR
280 printf(" %s: %s(0x%p) <= 0x%llx\n", __func__, mmc_reg_str(reg),
281 addr, value);
282 #endif
283 writeq(value, addr);
284 }
285
286 #ifdef DEBUG
mmc_print_status(u32 status)287 static void mmc_print_status(u32 status)
288 {
289 #ifdef DEBUG_STATUS
290 static const char * const state[] = {
291 "Idle", /* 0 */
292 "Ready", /* 1 */
293 "Ident", /* 2 */
294 "Standby", /* 3 */
295 "Tran", /* 4 */
296 "Data", /* 5 */
297 "Receive", /* 6 */
298 "Program", /* 7 */
299 "Dis", /* 8 */
300 "Btst", /* 9 */
301 "Sleep", /* 10 */
302 "reserved", /* 11 */
303 "reserved", /* 12 */
304 "reserved", /* 13 */
305 "reserved", /* 14 */
306 "reserved" /* 15 */ };
307 if (status & R1_APP_CMD)
308 puts("MMC ACMD\n");
309 if (status & R1_SWITCH_ERROR)
310 puts("MMC switch error\n");
311 if (status & R1_READY_FOR_DATA)
312 puts("MMC ready for data\n");
313 printf("MMC %s state\n", state[R1_CURRENT_STATE(status)]);
314 if (status & R1_ERASE_RESET)
315 puts("MMC erase reset\n");
316 if (status & R1_WP_ERASE_SKIP)
317 puts("MMC partial erase due to write protected blocks\n");
318 if (status & R1_CID_CSD_OVERWRITE)
319 puts("MMC CID/CSD overwrite error\n");
320 if (status & R1_ERROR)
321 puts("MMC undefined device error\n");
322 if (status & R1_CC_ERROR)
323 puts("MMC device error\n");
324 if (status & R1_CARD_ECC_FAILED)
325 puts("MMC internal ECC failed to correct data\n");
326 if (status & R1_ILLEGAL_COMMAND)
327 puts("MMC illegal command\n");
328 if (status & R1_COM_CRC_ERROR)
329 puts("MMC CRC of previous command failed\n");
330 if (status & R1_LOCK_UNLOCK_FAILED)
331 puts("MMC sequence or password error in lock/unlock device command\n");
332 if (status & R1_CARD_IS_LOCKED)
333 puts("MMC device locked by host\n");
334 if (status & R1_WP_VIOLATION)
335 puts("MMC attempt to program write protected block\n");
336 if (status & R1_ERASE_PARAM)
337 puts("MMC invalid selection of erase groups for erase\n");
338 if (status & R1_ERASE_SEQ_ERROR)
339 puts("MMC error in sequence of erase commands\n");
340 if (status & R1_BLOCK_LEN_ERROR)
341 puts("MMC block length error\n");
342 if (status & R1_ADDRESS_ERROR)
343 puts("MMC address misalign error\n");
344 if (status & R1_OUT_OF_RANGE)
345 puts("MMC address out of range\n");
346 #endif
347 }
348 #endif
349
350 #if !defined(CONFIG_ARCH_OCTEON)
351 /**
352 * Print out all of the register values where mmc is optional
353 *
354 * @param mmc MMC device (can be NULL)
355 * @param host Pointer to host data structure (can be NULL if mmc is !NULL)
356 */
octeontx_mmc_print_registers2(struct mmc * mmc,struct octeontx_mmc_host * host)357 static void octeontx_mmc_print_registers2(struct mmc *mmc,
358 struct octeontx_mmc_host *host)
359 {
360 struct octeontx_mmc_slot *slot = mmc ? mmc->priv : NULL;
361 union mio_emm_dma_cfg emm_dma_cfg;
362 union mio_emm_dma_adr emm_dma_adr;
363 union mio_emm_dma_int emm_dma_int;
364 union mio_emm_cfg emm_cfg;
365 union mio_emm_modex emm_mode;
366 union mio_emm_switch emm_switch;
367 union mio_emm_dma emm_dma;
368 union mio_emm_cmd emm_cmd;
369 union mio_emm_rsp_sts emm_rsp_sts;
370 union mio_emm_rsp_lo emm_rsp_lo;
371 union mio_emm_rsp_hi emm_rsp_hi;
372 union mio_emm_int emm_int;
373 union mio_emm_wdog emm_wdog;
374 union mio_emm_sample emm_sample;
375 union mio_emm_calb emm_calb;
376 union mio_emm_tap emm_tap;
377 union mio_emm_timing emm_timing;
378 union mio_emm_io_ctl io_ctl;
379 union mio_emm_debug emm_debug;
380 union mio_emm_sts_mask emm_sts_mask;
381 union mio_emm_rca emm_rca;
382 int bus;
383
384 static const char * const bus_width_str[] = {
385 "1-bit data bus (power on)",
386 "4-bit data bus",
387 "8-bit data bus",
388 "reserved (3)",
389 "reserved (4)",
390 "4-bit data bus (dual data rate)",
391 "8-bit data bus (dual data rate)",
392 "reserved (7)",
393 "reserved (8)",
394 "invalid (9)",
395 "invalid (10)",
396 "invalid (11)",
397 "invalid (12)",
398 "invalid (13)",
399 "invalid (14)",
400 "invalid (15)",
401 };
402 static const char * const ctype_xor_str[] = {
403 "No data",
404 "Read data into Dbuf",
405 "Write data from Dbuf",
406 "Reserved"
407 };
408
409 static const char * const rtype_xor_str[] = {
410 "No response",
411 "R1, 48 bits",
412 "R2, 136 bits",
413 "R3, 48 bits",
414 "R4, 48 bits",
415 "R5, 48 bits",
416 "Reserved 6",
417 "Reserved 7"
418 };
419
420 if (!host && mmc)
421 host = mmc_to_host(mmc);
422
423 if (mmc)
424 printf("%s: bus id: %u\n", __func__, slot->bus_id);
425 emm_dma_cfg.u = readq(host->base_addr + MIO_EMM_DMA_CFG());
426 printf("MIO_EMM_DMA_CFG: 0x%016llx\n",
427 emm_dma_cfg.u);
428 printf(" 63: en: %s\n",
429 emm_dma_cfg.s.en ? "enabled" : "disabled");
430 printf(" 62: rw: %s\n",
431 emm_dma_cfg.s.rw ? "write" : "read");
432 printf(" 61: clr: %s\n",
433 emm_dma_cfg.s.clr ? "clear" : "not clear");
434 printf(" 59: swap32: %s\n",
435 emm_dma_cfg.s.swap32 ? "yes" : "no");
436 printf(" 58: swap16: %s\n",
437 emm_dma_cfg.s.swap16 ? "yes" : "no");
438 printf(" 57: swap8: %s\n",
439 emm_dma_cfg.s.swap8 ? "yes" : "no");
440 printf(" 56: endian: %s\n",
441 emm_dma_cfg.s.endian ? "little" : "big");
442 printf(" 36-55: size: %u\n",
443 emm_dma_cfg.s.size);
444
445 emm_dma_adr.u = readq(host->base_addr + MIO_EMM_DMA_ADR());
446 printf("MIO_EMM_DMA_ADR: 0x%016llx\n", emm_dma_adr.u);
447 printf(" 0-49: adr: 0x%llx\n",
448 (u64)emm_dma_adr.s.adr);
449
450 emm_dma_int.u = readq(host->base_addr + MIO_EMM_DMA_INT());
451 printf("\nMIO_EMM_DMA_INT: 0x%016llx\n",
452 emm_dma_int.u);
453 printf(" 1: FIFO: %s\n",
454 emm_dma_int.s.fifo ? "yes" : "no");
455 printf(" 0: Done: %s\n",
456 emm_dma_int.s.done ? "yes" : "no");
457 emm_cfg.u = readq(host->base_addr + MIO_EMM_CFG());
458
459 printf("\nMIO_EMM_CFG: 0x%016llx\n",
460 emm_cfg.u);
461 printf(" 3: bus_ena3: %s\n",
462 emm_cfg.s.bus_ena & 0x08 ? "yes" : "no");
463 printf(" 2: bus_ena2: %s\n",
464 emm_cfg.s.bus_ena & 0x04 ? "yes" : "no");
465 printf(" 1: bus_ena1: %s\n",
466 emm_cfg.s.bus_ena & 0x02 ? "yes" : "no");
467 printf(" 0: bus_ena0: %s\n",
468 emm_cfg.s.bus_ena & 0x01 ? "yes" : "no");
469 for (bus = 0; bus < 4; bus++) {
470 emm_mode.u = readq(host->base_addr + MIO_EMM_MODEX(bus));
471 printf("\nMIO_EMM_MODE%u: 0x%016llx\n",
472 bus, emm_mode.u);
473 if (!IS_ENABLED(CONFIG_ARCH_OCTEONTX)) {
474 printf(" 50: hs400_timing: %s\n",
475 emm_mode.s.hs400_timing ? "yes" : "no");
476 printf(" 49: hs200_timing: %s\n",
477 emm_mode.s.hs200_timing ? "yes" : "no");
478 }
479 printf(" 48: hs_timing: %s\n",
480 emm_mode.s.hs_timing ? "yes" : "no");
481 printf(" 40-42: bus_width: %s\n",
482 bus_width_str[emm_mode.s.bus_width]);
483 printf(" 32-35: power_class %u\n",
484 emm_mode.s.power_class);
485 printf(" 16-31: clk_hi: %u\n",
486 emm_mode.s.clk_hi);
487 printf(" 0-15: clk_lo: %u\n",
488 emm_mode.s.clk_lo);
489 }
490
491 emm_switch.u = readq(host->base_addr + MIO_EMM_SWITCH());
492 printf("\nMIO_EMM_SWITCH: 0x%016llx\n", emm_switch.u);
493 printf(" 60-61: bus_id: %u\n", emm_switch.s.bus_id);
494 printf(" 59: switch_exe: %s\n",
495 emm_switch.s.switch_exe ? "yes" : "no");
496 printf(" 58: switch_err0: %s\n",
497 emm_switch.s.switch_err0 ? "yes" : "no");
498 printf(" 57: switch_err1: %s\n",
499 emm_switch.s.switch_err1 ? "yes" : "no");
500 printf(" 56: switch_err2: %s\n",
501 emm_switch.s.switch_err2 ? "yes" : "no");
502 printf(" 48: hs_timing: %s\n",
503 emm_switch.s.hs_timing ? "yes" : "no");
504 printf(" 42-40: bus_width: %s\n",
505 bus_width_str[emm_switch.s.bus_width]);
506 printf(" 32-35: power_class: %u\n",
507 emm_switch.s.power_class);
508 printf(" 16-31: clk_hi: %u\n",
509 emm_switch.s.clk_hi);
510 printf(" 0-15: clk_lo: %u\n", emm_switch.s.clk_lo);
511
512 emm_dma.u = readq(host->base_addr + MIO_EMM_DMA());
513 printf("\nMIO_EMM_DMA: 0x%016llx\n", emm_dma.u);
514 printf(" 60-61: bus_id: %u\n", emm_dma.s.bus_id);
515 printf(" 59: dma_val: %s\n",
516 emm_dma.s.dma_val ? "yes" : "no");
517 printf(" 58: sector: %s mode\n",
518 emm_dma.s.sector ? "sector" : "byte");
519 printf(" 57: dat_null: %s\n",
520 emm_dma.s.dat_null ? "yes" : "no");
521 printf(" 51-56: thres: %u\n", emm_dma.s.thres);
522 printf(" 50: rel_wr: %s\n",
523 emm_dma.s.rel_wr ? "yes" : "no");
524 printf(" 49: rw: %s\n",
525 emm_dma.s.rw ? "write" : "read");
526 printf(" 48: multi: %s\n",
527 emm_dma.s.multi ? "yes" : "no");
528 printf(" 32-47: block_cnt: %u\n",
529 emm_dma.s.block_cnt);
530 printf(" 0-31: card_addr: 0x%x\n",
531 emm_dma.s.card_addr);
532
533 emm_cmd.u = readq(host->base_addr + MIO_EMM_CMD());
534 printf("\nMIO_EMM_CMD: 0x%016llx\n", emm_cmd.u);
535 printf("\n 62: skip_busy: %s\n",
536 emm_cmd.s.skip_busy ? "yes" : "no");
537 printf(" 60-61: bus_id: %u\n", emm_cmd.s.bus_id);
538 printf(" 59: cmd_val: %s\n",
539 emm_cmd.s.cmd_val ? "yes" : "no");
540 printf(" 55: dbuf: %u\n", emm_cmd.s.dbuf);
541 printf(" 49-54: offset: %u\n", emm_cmd.s.offset);
542 printf(" 41-42: ctype_xor: %s\n",
543 ctype_xor_str[emm_cmd.s.ctype_xor]);
544 printf(" 38-40: rtype_xor: %s\n",
545 rtype_xor_str[emm_cmd.s.rtype_xor]);
546 printf(" 32-37: cmd_idx: %u\n", emm_cmd.s.cmd_idx);
547 printf(" 0-31: arg: 0x%x\n", emm_cmd.s.arg);
548
549 emm_rsp_sts.u = readq(host->base_addr + MIO_EMM_RSP_STS());
550 printf("\nMIO_EMM_RSP_STS: 0x%016llx\n", emm_rsp_sts.u);
551 printf(" 60-61: bus_id: %u\n", emm_rsp_sts.s.bus_id);
552 printf(" 59: cmd_val: %s\n",
553 emm_rsp_sts.s.cmd_val ? "yes" : "no");
554 printf(" 58: switch_val: %s\n",
555 emm_rsp_sts.s.switch_val ? "yes" : "no");
556 printf(" 57: dma_val: %s\n",
557 emm_rsp_sts.s.dma_val ? "yes" : "no");
558 printf(" 56: dma_pend: %s\n",
559 emm_rsp_sts.s.dma_pend ? "yes" : "no");
560 printf(" 28: dbuf_err: %s\n",
561 emm_rsp_sts.s.dbuf_err ? "yes" : "no");
562 printf(" 23: dbuf: %u\n", emm_rsp_sts.s.dbuf);
563 printf(" 22: blk_timeout: %s\n",
564 emm_rsp_sts.s.blk_timeout ? "yes" : "no");
565 printf(" 21: blk_crc_err: %s\n",
566 emm_rsp_sts.s.blk_crc_err ? "yes" : "no");
567 printf(" 20: rsp_busybit: %s\n",
568 emm_rsp_sts.s.rsp_busybit ? "yes" : "no");
569 printf(" 19: stp_timeout: %s\n",
570 emm_rsp_sts.s.stp_timeout ? "yes" : "no");
571 printf(" 18: stp_crc_err: %s\n",
572 emm_rsp_sts.s.stp_crc_err ? "yes" : "no");
573 printf(" 17: stp_bad_sts: %s\n",
574 emm_rsp_sts.s.stp_bad_sts ? "yes" : "no");
575 printf(" 16: stp_val: %s\n",
576 emm_rsp_sts.s.stp_val ? "yes" : "no");
577 printf(" 15: rsp_timeout: %s\n",
578 emm_rsp_sts.s.rsp_timeout ? "yes" : "no");
579 printf(" 14: rsp_crc_err: %s\n",
580 emm_rsp_sts.s.rsp_crc_err ? "yes" : "no");
581 printf(" 13: rsp_bad_sts: %s\n",
582 emm_rsp_sts.s.rsp_bad_sts ? "yes" : "no");
583 printf(" 12: rsp_val: %s\n",
584 emm_rsp_sts.s.rsp_val ? "yes" : "no");
585 printf(" 9-11: rsp_type: %s\n",
586 rtype_xor_str[emm_rsp_sts.s.rsp_type]);
587 printf(" 7-8: cmd_type: %s\n",
588 ctype_xor_str[emm_rsp_sts.s.cmd_type]);
589 printf(" 1-6: cmd_idx: %u\n",
590 emm_rsp_sts.s.cmd_idx);
591 printf(" 0: cmd_done: %s\n",
592 emm_rsp_sts.s.cmd_done ? "yes" : "no");
593
594 emm_rsp_lo.u = readq(host->base_addr + MIO_EMM_RSP_LO());
595 printf("\nMIO_EMM_RSP_STS_LO: 0x%016llx\n", emm_rsp_lo.u);
596
597 emm_rsp_hi.u = readq(host->base_addr + MIO_EMM_RSP_HI());
598 printf("\nMIO_EMM_RSP_STS_HI: 0x%016llx\n", emm_rsp_hi.u);
599
600 emm_int.u = readq(host->base_addr + MIO_EMM_INT());
601 printf("\nMIO_EMM_INT: 0x%016llx\n", emm_int.u);
602 printf(" 6: switch_err: %s\n",
603 emm_int.s.switch_err ? "yes" : "no");
604 printf(" 5: switch_done: %s\n",
605 emm_int.s.switch_done ? "yes" : "no");
606 printf(" 4: dma_err: %s\n",
607 emm_int.s.dma_err ? "yes" : "no");
608 printf(" 3: cmd_err: %s\n",
609 emm_int.s.cmd_err ? "yes" : "no");
610 printf(" 2: dma_done: %s\n",
611 emm_int.s.dma_done ? "yes" : "no");
612 printf(" 1: cmd_done: %s\n",
613 emm_int.s.cmd_done ? "yes" : "no");
614 printf(" 0: buf_done: %s\n",
615 emm_int.s.buf_done ? "yes" : "no");
616
617 emm_wdog.u = readq(host->base_addr + MIO_EMM_WDOG());
618 printf("\nMIO_EMM_WDOG: 0x%016llx (%u)\n",
619 emm_wdog.u, emm_wdog.s.clk_cnt);
620
621 if (IS_ENABLED(CONFIG_ARCH_OCTEONTX)) {
622 emm_sample.u = readq(host->base_addr + MIO_EMM_SAMPLE());
623 printf("\nMIO_EMM_SAMPLE: 0x%016llx\n",
624 emm_sample.u);
625 printf(" 16-25: cmd_cnt: %u\n",
626 emm_sample.s.cmd_cnt);
627 printf(" 0-9: dat_cnt: %u\n",
628 emm_sample.s.dat_cnt);
629 }
630
631 emm_sts_mask.u = readq(host->base_addr + MIO_EMM_STS_MASK());
632 printf("\nMIO_EMM_STS_MASK: 0x%016llx\n", emm_sts_mask.u);
633
634 emm_rca.u = readq(host->base_addr + MIO_EMM_RCA());
635 printf("\nMIO_EMM_RCA: 0x%016llx\n", emm_rca.u);
636 printf(" 0-15: card_rca: 0x%04x\n",
637 emm_rca.s.card_rca);
638 if (!IS_ENABLED(CONFIG_ARCH_OCTEONTX)) {
639 emm_calb.u = readq(host->base_addr + MIO_EMM_CALB());
640 printf("\nMIO_EMM_CALB: 0x%016llx\n",
641 emm_calb.u);
642 printf(" 0: start: %u\n",
643 emm_calb.s.start);
644 emm_tap.u = readq(host->base_addr + MIO_EMM_TAP());
645 printf("\nMIO_EMM_TAP: 0x%016llx\n",
646 emm_tap.u);
647 printf(" 7-0: delay: %u\n", emm_tap.s.delay);
648 emm_timing.u = readq(host->base_addr + MIO_EMM_TIMING());
649 printf("\nMIO_EMM_TIMING: 0x%016llx\n",
650 emm_timing.u);
651 printf(" 53-48: cmd_in_tap: %u\n",
652 emm_timing.s.cmd_in_tap);
653 printf(" 37-32: cmd_out_tap: %u\n",
654 emm_timing.s.cmd_out_tap);
655 printf(" 21-16: data_in_tap: %u\n",
656 emm_timing.s.data_in_tap);
657 printf(" 5-0: data_out_tap: %u\n",
658 emm_timing.s.data_out_tap);
659 io_ctl.u = readq(host->base_addr + MIO_EMM_IO_CTL());
660 printf("\nMIO_IO_CTL: 0x%016llx\n", io_ctl.u);
661 printf(" 3-2: drive: %u (%u mA)\n",
662 io_ctl.s.drive, 2 << io_ctl.s.drive);
663 printf(" 0: slew: %u %s\n", io_ctl.s.slew,
664 io_ctl.s.slew ? "high" : "low");
665 emm_debug.u = readq(host->base_addr + MIO_EMM_DEBUG());
666 printf("\nMIO_EMM_DEBUG: 0x%016llx\n",
667 emm_debug.u);
668 printf(" 21: rdsync_rst 0x%x\n",
669 emm_debug.s.rdsync_rst);
670 printf(" 20: emmc_clk_disable 0x%x\n",
671 emm_debug.s.emmc_clk_disable);
672 printf(" 19-16: dma_sm: 0x%x\n",
673 emm_debug.s.dma_sm);
674 printf(" 15-12: data_sm: 0x%x\n",
675 emm_debug.s.data_sm);
676 printf(" 11-8: cmd_sm: 0x%x\n",
677 emm_debug.s.cmd_sm);
678 printf(" 0: clk_on: 0x%x\n",
679 emm_debug.s.clk_on);
680 }
681
682 puts("\n");
683 }
684
685 /**
686 * Print out all of the register values
687 *
688 * @param mmc MMC device
689 */
octeontx_mmc_print_registers(struct mmc * mmc)690 static void octeontx_mmc_print_registers(struct mmc *mmc)
691 {
692 #ifdef DEBUG_REGISTERS
693 const int print = 1;
694 #else
695 const int print = 0;
696 #endif
697 if (print)
698 octeontx_mmc_print_registers2(mmc, mmc_to_host(mmc));
699 }
700 #else
octeontx_mmc_print_registers(struct mmc * mmc)701 static void octeontx_mmc_print_registers(struct mmc *mmc)
702 {
703 return;
704 }
705 #endif
706
707 static const struct octeontx_sd_mods octeontx_cr_types[] = {
708 { {0, 0}, {0, 0}, {0, 0} }, /* CMD0 */
709 { {0, 3}, {0, 3}, {0, 0} }, /* CMD1 */
710 { {0, 2}, {0, 2}, {0, 0} }, /* CMD2 */
711 { {0, 1}, {0, 3}, {0, 0} }, /* CMD3 SD_CMD_SEND_RELATIVE_ADDR 0, 2 */
712 { {0, 0}, {0, 0}, {0, 0} }, /* CMD4 */
713 { {0, 1}, {0, 1}, {0, 0} }, /* CMD5 */
714 { {0, 1}, {1, 1}, {0, 1} }, /*
715 * CMD6 SD_CMD_SWITCH_FUNC 1,0
716 * (ACMD) SD_APP_SET_BUS_WIDTH
717 */
718 { {0, 1}, {0, 1}, {0, 0} }, /* CMD7 */
719 { {1, 1}, {0, 3}, {0, 0} }, /* CMD8 SD_CMD_SEND_IF_COND 1,2 */
720 { {0, 2}, {0, 2}, {0, 0} }, /* CMD9 */
721 { {0, 2}, {0, 2}, {0, 0} }, /* CMD10 */
722 { {1, 1}, {0, 1}, {1, 1} }, /* CMD11 SD_CMD_SWITCH_UHS18V 1,0 */
723 { {0, 1}, {0, 1}, {0, 0} }, /* CMD12 */
724 { {0, 1}, {0, 1}, {1, 3} }, /* CMD13 (ACMD)) SD_CMD_APP_SD_STATUS 1,2 */
725 { {1, 1}, {1, 1}, {0, 0} }, /* CMD14 */
726 { {0, 0}, {0, 0}, {0, 0} }, /* CMD15 */
727 { {0, 1}, {0, 1}, {0, 0} }, /* CMD16 */
728 { {1, 1}, {1, 1}, {0, 0} }, /* CMD17 */
729 { {1, 1}, {1, 1}, {0, 0} }, /* CMD18 */
730 { {3, 1}, {3, 1}, {0, 0} }, /* CMD19 */
731 { {2, 1}, {0, 0}, {0, 0} }, /* CMD20 */ /* SD 2,0 */
732 { {0, 0}, {0, 0}, {0, 0} }, /* CMD21 */
733 { {0, 0}, {0, 0}, {1, 1} }, /* CMD22 (ACMD) SD_APP_SEND_NUM_WR_BLKS 1,0 */
734 { {0, 1}, {0, 1}, {0, 1} }, /* CMD23 */ /* SD ACMD 1,0 */
735 { {2, 1}, {2, 1}, {2, 1} }, /* CMD24 */
736 { {2, 1}, {2, 1}, {2, 1} }, /* CMD25 */
737 { {2, 1}, {2, 1}, {2, 1} }, /* CMD26 */
738 { {2, 1}, {2, 1}, {2, 1} }, /* CMD27 */
739 { {0, 1}, {0, 1}, {0, 1} }, /* CMD28 */
740 { {0, 1}, {0, 1}, {0, 1} }, /* CMD29 */
741 { {1, 1}, {1, 1}, {1, 1} }, /* CMD30 */
742 { {1, 1}, {1, 1}, {1, 1} }, /* CMD31 */
743 { {0, 0}, {0, 1}, {0, 0} }, /* CMD32 SD_CMD_ERASE_WR_BLK_START 0,1 */
744 { {0, 0}, {0, 1}, {0, 0} }, /* CMD33 SD_CMD_ERASE_WR_BLK_END 0,1 */
745 { {0, 0}, {0, 0}, {0, 0} }, /* CMD34 */
746 { {0, 1}, {0, 1}, {0, 1} }, /* CMD35 */
747 { {0, 1}, {0, 1}, {0, 1} }, /* CMD36 */
748 { {0, 0}, {0, 0}, {0, 0} }, /* CMD37 */
749 { {0, 1}, {0, 1}, {0, 1} }, /* CMD38 */
750 { {0, 4}, {0, 4}, {0, 4} }, /* CMD39 */
751 { {0, 5}, {0, 5}, {0, 5} }, /* CMD40 */
752 { {0, 0}, {0, 0}, {0, 3} }, /* CMD41 (ACMD) SD_CMD_APP_SEND_OP_COND 0,3 */
753 { {2, 1}, {2, 1}, {2, 1} }, /* CMD42 */
754 { {0, 0}, {0, 0}, {0, 0} }, /* CMD43 */
755 { {0, 0}, {0, 0}, {0, 0} }, /* CMD44 */
756 { {0, 0}, {0, 0}, {0, 0} }, /* CMD45 */
757 { {0, 0}, {0, 0}, {0, 0} }, /* CMD46 */
758 { {0, 0}, {0, 0}, {0, 0} }, /* CMD47 */
759 { {0, 0}, {1, 0}, {0, 0} }, /* CMD48 SD_CMD_READ_EXTR_SINGLE */
760 { {0, 0}, {2, 0}, {0, 0} }, /* CMD49 SD_CMD_WRITE_EXTR_SINGLE */
761 { {0, 0}, {0, 0}, {0, 0} }, /* CMD50 */
762 { {0, 0}, {0, 0}, {1, 1} }, /* CMD51 (ACMD) SD_CMD_APP_SEND_SCR 1,1 */
763 { {0, 0}, {0, 0}, {0, 0} }, /* CMD52 */
764 { {0, 0}, {0, 0}, {0, 0} }, /* CMD53 */
765 { {0, 0}, {0, 0}, {0, 0} }, /* CMD54 */
766 { {0, 1}, {0, 1}, {0, 1} }, /* CMD55 */
767 { {0xff, 0xff}, {0xff, 0xff}, {0xff, 0xff} }, /* CMD56 */
768 { {0, 0}, {0, 0}, {0, 0} }, /* CMD57 */
769 { {0, 0}, {0, 3}, {0, 3} }, /* CMD58 SD_CMD_SPI_READ_OCR 0,3 */
770 { {0, 0}, {0, 1}, {0, 0} }, /* CMD59 SD_CMD_SPI_CRC_ON_OFF 0,1 */
771 { {0, 0}, {0, 0}, {0, 0} }, /* CMD60 */
772 { {0, 0}, {0, 0}, {0, 0} }, /* CMD61 */
773 { {0, 0}, {0, 0}, {0, 0} }, /* CMD62 */
774 { {0, 0}, {0, 0}, {0, 0} } /* CMD63 */
775 };
776
777 /**
778 * Returns XOR values needed for SD commands and other quirks
779 *
780 * @param mmc mmc device
781 * @param cmd command information
782 *
783 * @return octeontx_mmc_cr_mods data structure with various quirks and flags
784 */
785 static struct octeontx_mmc_cr_mods
octeontx_mmc_get_cr_mods(struct mmc * mmc,const struct mmc_cmd * cmd,const struct mmc_data * data)786 octeontx_mmc_get_cr_mods(struct mmc *mmc, const struct mmc_cmd *cmd,
787 const struct mmc_data *data)
788 {
789 struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
790 struct octeontx_mmc_cr_mods cr = {0, 0};
791 const struct octeontx_sd_mods *sdm =
792 &octeontx_cr_types[cmd->cmdidx & 0x3f];
793 u8 c = sdm->mmc.c, r = sdm->mmc.r;
794 u8 desired_ctype = 0;
795
796 if (IS_MMC(mmc)) {
797 #ifdef MMC_SUPPORTS_TUNING
798 if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
799 if (cmd->resp_type == MMC_RSP_R1)
800 cr.rtype_xor = 1;
801 if (data && data->flags & MMC_DATA_READ)
802 cr.ctype_xor = 1;
803 }
804 #endif
805 return cr;
806 }
807
808 if (cmd->cmdidx == 56)
809 c = (cmd->cmdarg & 1) ? 1 : 2;
810
811 if (data) {
812 if (data->flags & MMC_DATA_READ)
813 desired_ctype = 1;
814 else if (data->flags & MMC_DATA_WRITE)
815 desired_ctype = 2;
816 }
817
818 cr.ctype_xor = c ^ desired_ctype;
819 if (slot->is_acmd)
820 cr.rtype_xor = r ^ sdm->sdacmd.r;
821 else
822 cr.rtype_xor = r ^ sdm->sd.r;
823
824 debug("%s(%s): mmc c: %d, mmc r: %d, desired c: %d, xor c: %d, xor r: %d\n",
825 __func__, mmc->dev->name, c, r, desired_ctype,
826 cr.ctype_xor, cr.rtype_xor);
827 return cr;
828 }
829
830 /**
831 * Keep track of switch commands internally
832 */
octeontx_mmc_track_switch(struct mmc * mmc,u32 cmd_arg)833 static void octeontx_mmc_track_switch(struct mmc *mmc, u32 cmd_arg)
834 {
835 struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
836 u8 how = (cmd_arg >> 24) & 3;
837 u8 where = (u8)(cmd_arg >> 16);
838 u8 val = (u8)(cmd_arg >> 8);
839
840 slot->want_switch = slot->cached_switch;
841
842 if (slot->is_acmd)
843 return;
844
845 if (how != 3)
846 return;
847
848 switch (where) {
849 case EXT_CSD_BUS_WIDTH:
850 slot->want_switch.s.bus_width = val;
851 break;
852 case EXT_CSD_POWER_CLASS:
853 slot->want_switch.s.power_class = val;
854 break;
855 case EXT_CSD_HS_TIMING:
856 slot->want_switch.s.hs_timing = 0;
857 #if !defined(CONFIG_ARCH_OCTEON)
858 slot->want_switch.s.hs200_timing = 0;
859 slot->want_switch.s.hs400_timing = 0;
860 #endif
861 switch (val & 0xf) {
862 case 0:
863 break;
864 case 1:
865 slot->want_switch.s.hs_timing = 1;
866 break;
867 #if !defined(CONFIG_ARCH_OCTEON)
868 case 2:
869 if (!slot->is_asim && !slot->is_emul)
870 slot->want_switch.s.hs200_timing = 1;
871 break;
872 case 3:
873 if (!slot->is_asim && !slot->is_emul)
874 slot->want_switch.s.hs400_timing = 1;
875 break;
876 #endif
877 default:
878 pr_err("%s(%s): Unsupported timing mode 0x%x\n",
879 __func__, mmc->dev->name, val & 0xf);
880 break;
881 }
882 break;
883 default:
884 break;
885 }
886 }
887
octeontx_mmc_print_rsp_errors(struct mmc * mmc,union mio_emm_rsp_sts rsp_sts)888 static int octeontx_mmc_print_rsp_errors(struct mmc *mmc,
889 union mio_emm_rsp_sts rsp_sts)
890 {
891 bool err = false;
892 const char *name = mmc->dev->name;
893
894 if (rsp_sts.s.acc_timeout) {
895 pr_warn("%s(%s): acc_timeout\n", __func__, name);
896 err = true;
897 }
898 if (rsp_sts.s.dbuf_err) {
899 pr_warn("%s(%s): dbuf_err\n", __func__, name);
900 err = true;
901 }
902 if (rsp_sts.s.blk_timeout) {
903 pr_warn("%s(%s): blk_timeout\n", __func__, name);
904 err = true;
905 }
906 if (rsp_sts.s.blk_crc_err) {
907 pr_warn("%s(%s): blk_crc_err\n", __func__, name);
908 err = true;
909 }
910 if (rsp_sts.s.stp_timeout) {
911 pr_warn("%s(%s): stp_timeout\n", __func__, name);
912 err = true;
913 }
914 if (rsp_sts.s.stp_crc_err) {
915 pr_warn("%s(%s): stp_crc_err\n", __func__, name);
916 err = true;
917 }
918 if (rsp_sts.s.stp_bad_sts) {
919 pr_warn("%s(%s): stp_bad_sts\n", __func__, name);
920 err = true;
921 }
922 if (err)
923 pr_warn(" rsp_sts: 0x%llx\n", rsp_sts.u);
924
925 return err ? -1 : 0;
926 }
927
928 /**
929 * Starts a DMA operation for block read/write
930 *
931 * @param mmc mmc device
932 * @param write true if write operation
933 * @param clear true to clear DMA operation
934 * @param adr source or destination DMA address
935 * @param size size in blocks
936 * @param timeout timeout in ms
937 */
octeontx_mmc_start_dma(struct mmc * mmc,bool write,bool clear,u32 block,dma_addr_t adr,u32 size,int timeout)938 static void octeontx_mmc_start_dma(struct mmc *mmc, bool write,
939 bool clear, u32 block, dma_addr_t adr,
940 u32 size, int timeout)
941 {
942 const struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
943 union mio_emm_dma_cfg emm_dma_cfg;
944 union mio_emm_dma_adr emm_dma_adr;
945 union mio_emm_dma emm_dma;
946
947 /* Clear any interrupts */
948 write_csr(mmc, MIO_EMM_DMA_INT(),
949 read_csr(mmc, MIO_EMM_DMA_INT()));
950
951 emm_dma_cfg.u = 0;
952 emm_dma_cfg.s.en = 1;
953 emm_dma_cfg.s.rw = !!write;
954 emm_dma_cfg.s.clr = !!clear;
955 emm_dma_cfg.s.size = ((u64)(size * mmc->read_bl_len) / 8) - 1;
956 #if __BYTE_ORDER != __BIG_ENDIAN
957 emm_dma_cfg.s.endian = 1;
958 #endif
959 emm_dma_adr.u = 0;
960 emm_dma_adr.s.adr = adr;
961 write_csr(mmc, MIO_EMM_DMA_ADR(), emm_dma_adr.u);
962 write_csr(mmc, MIO_EMM_DMA_CFG(), emm_dma_cfg.u);
963
964 emm_dma.u = 0;
965 emm_dma.s.bus_id = slot->bus_id;
966 emm_dma.s.dma_val = 1;
967 emm_dma.s.rw = !!write;
968 emm_dma.s.sector = mmc->high_capacity ? 1 : 0;
969
970 if (size > 1 && ((IS_SD(mmc) && (mmc->scr[0] & 2)) || !IS_SD(mmc)))
971 emm_dma.s.multi = 1;
972 else
973 emm_dma.s.multi = 0;
974
975 emm_dma.s.block_cnt = size;
976 if (!mmc->high_capacity)
977 block *= mmc->read_bl_len;
978 emm_dma.s.card_addr = block;
979 debug("%s(%s): card address: 0x%x, size: %d, multi: %d\n",
980 __func__, mmc->dev->name, block, size, emm_dma.s.multi);
981
982 if (timeout > 0)
983 timeout = (timeout * 1000) - 1000;
984 set_wdog(mmc, timeout);
985
986 debug(" Writing 0x%llx to mio_emm_dma\n", emm_dma.u);
987 write_csr(mmc, MIO_EMM_DMA(), emm_dma.u);
988 }
989
990 /**
991 * Waits for a DMA operation to complete
992 *
993 * @param mmc mmc device
994 * @param timeout timeout in ms
995 *
996 * @return 0 for success (could be DMA errors), -ETIMEDOUT on timeout
997 */
998
999 /**
1000 * Cleanup DMA engine after a failure
1001 *
1002 * @param mmc mmc device
1003 * @param rsp_sts rsp status
1004 */
octeontx_mmc_cleanup_dma(struct mmc * mmc,union mio_emm_rsp_sts rsp_sts)1005 static void octeontx_mmc_cleanup_dma(struct mmc *mmc,
1006 union mio_emm_rsp_sts rsp_sts)
1007 {
1008 struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
1009 union mio_emm_dma emm_dma;
1010 ulong start;
1011 int retries = 3;
1012
1013 do {
1014 debug("%s(%s): rsp_sts: 0x%llx, rsp_lo: 0x%llx, dma_int: 0x%llx\n",
1015 __func__, mmc->dev->name, rsp_sts.u,
1016 read_csr(mmc, MIO_EMM_RSP_LO()),
1017 read_csr(mmc, MIO_EMM_DMA_INT()));
1018 emm_dma.u = read_csr(mmc, MIO_EMM_DMA());
1019 emm_dma.s.dma_val = 1;
1020 emm_dma.s.dat_null = 1;
1021 emm_dma.s.bus_id = slot->bus_id;
1022 write_csr(mmc, MIO_EMM_DMA(), emm_dma.u);
1023 start = get_timer(0);
1024 do {
1025 rsp_sts.u = read_csr(mmc, MIO_EMM_RSP_STS());
1026 WATCHDOG_RESET();
1027 } while (get_timer(start) < 100 &&
1028 (rsp_sts.s.dma_val || rsp_sts.s.dma_pend));
1029 } while (retries-- >= 0 && rsp_sts.s.dma_pend);
1030 if (rsp_sts.s.dma_val)
1031 pr_err("%s(%s): Error: could not clean up DMA. RSP_STS: 0x%llx, RSP_LO: 0x%llx\n",
1032 __func__, mmc->dev->name, rsp_sts.u,
1033 read_csr(mmc, MIO_EMM_RSP_LO()));
1034 debug(" rsp_sts after clearing up DMA: 0x%llx\n",
1035 read_csr(mmc, MIO_EMM_RSP_STS()));
1036 }
1037
1038 /**
1039 * Waits for a DMA operation to complete
1040 *
1041 * @param mmc mmc device
1042 * @param timeout timeout in ms
1043 * @param verbose true to print out error information
1044 *
1045 * @return 0 for success (could be DMA errors), -ETIMEDOUT on timeout
1046 * or -EIO if IO error.
1047 */
octeontx_mmc_wait_dma(struct mmc * mmc,bool write,ulong timeout,bool verbose)1048 static int octeontx_mmc_wait_dma(struct mmc *mmc, bool write, ulong timeout,
1049 bool verbose)
1050 {
1051 struct octeontx_mmc_host *host = mmc_to_host(mmc);
1052 ulong start_time = get_timer(0);
1053 union mio_emm_dma_int emm_dma_int;
1054 union mio_emm_rsp_sts rsp_sts;
1055 union mio_emm_dma emm_dma;
1056 bool timed_out = false;
1057 bool err = false;
1058
1059 debug("%s(%s, %lu, %d), delay: %uus\n", __func__, mmc->dev->name,
1060 timeout, verbose, host->dma_wait_delay);
1061
1062 udelay(host->dma_wait_delay);
1063 do {
1064 emm_dma_int.u = read_csr(mmc, MIO_EMM_DMA_INT());
1065 rsp_sts.u = read_csr(mmc, MIO_EMM_RSP_STS());
1066 if (write) {
1067 if ((rsp_sts.s.dma_pend && !rsp_sts.s.dma_val) ||
1068 rsp_sts.s.blk_timeout ||
1069 rsp_sts.s.stp_timeout ||
1070 rsp_sts.s.rsp_timeout) {
1071 err = true;
1072 #ifdef DEBUG
1073 debug("%s: f1\n", __func__);
1074 octeontx_mmc_print_rsp_errors(mmc, rsp_sts);
1075 #endif
1076 break;
1077 }
1078 } else {
1079 if (rsp_sts.s.blk_crc_err ||
1080 (rsp_sts.s.dma_pend && !rsp_sts.s.dma_val)) {
1081 err = true;
1082 #if defined(DEBUG)
1083 octeontx_mmc_print_rsp_errors(mmc, rsp_sts);
1084 #endif
1085 break;
1086 }
1087 }
1088 if (rsp_sts.s.dma_pend) {
1089 /*
1090 * If this is set then an error has occurred.
1091 * Try and restart the DMA operation.
1092 */
1093 emm_dma.u = read_csr(mmc, MIO_EMM_DMA());
1094 if (verbose) {
1095 pr_err("%s(%s): DMA pending error: rsp_sts: 0x%llx, dma_int: 0x%llx, emm_dma: 0x%llx\n",
1096 __func__, mmc->dev->name, rsp_sts.u,
1097 emm_dma_int.u, emm_dma.u);
1098 octeontx_print_rsp_sts(mmc);
1099 debug(" MIO_EMM_DEBUG: 0x%llx\n",
1100 read_csr(mmc, MIO_EMM_DEBUG()));
1101 pr_err("%s: Trying DMA resume...\n", __func__);
1102 }
1103 emm_dma.s.dma_val = 1;
1104 emm_dma.s.dat_null = 1;
1105 write_csr(mmc, MIO_EMM_DMA(), emm_dma.u);
1106 udelay(10);
1107 } else if (!rsp_sts.s.dma_val && emm_dma_int.s.done) {
1108 break;
1109 }
1110 WATCHDOG_RESET();
1111 timed_out = (get_timer(start_time) > timeout);
1112 } while (!timed_out);
1113
1114 if (timed_out || err) {
1115 if (verbose) {
1116 pr_err("%s(%s): MMC DMA %s after %lu ms, rsp_sts: 0x%llx, dma_int: 0x%llx, rsp_sts_lo: 0x%llx, emm_dma: 0x%llx\n",
1117 __func__, mmc->dev->name,
1118 timed_out ? "timed out" : "error",
1119 get_timer(start_time), rsp_sts.u,
1120 emm_dma_int.u,
1121 read_csr(mmc, MIO_EMM_RSP_LO()),
1122 read_csr(mmc, MIO_EMM_DMA()));
1123 octeontx_print_rsp_sts(mmc);
1124 }
1125 if (rsp_sts.s.dma_pend)
1126 octeontx_mmc_cleanup_dma(mmc, rsp_sts);
1127 } else {
1128 write_csr(mmc, MIO_EMM_DMA_INT(),
1129 read_csr(mmc, MIO_EMM_DMA_INT()));
1130 }
1131
1132 return timed_out ? -ETIMEDOUT : (err ? -EIO : 0);
1133 }
1134
1135 /**
1136 * Read blocks from the MMC/SD device
1137 *
1138 * @param mmc mmc device
1139 * @param cmd command
1140 * @param data data for read
1141 * @param verbose true to print out error information
1142 *
1143 * @return number of blocks read or 0 if error
1144 */
octeontx_mmc_read_blocks(struct mmc * mmc,struct mmc_cmd * cmd,struct mmc_data * data,bool verbose)1145 static int octeontx_mmc_read_blocks(struct mmc *mmc, struct mmc_cmd *cmd,
1146 struct mmc_data *data, bool verbose)
1147 {
1148 struct octeontx_mmc_host *host = mmc_to_host(mmc);
1149 union mio_emm_rsp_sts rsp_sts;
1150 dma_addr_t dma_addr = (dma_addr_t)dm_pci_virt_to_mem(host->dev,
1151 data->dest);
1152 ulong count;
1153 ulong blkcnt = data->blocks;
1154 ulong start = cmd->cmdarg;
1155 int timeout = 1000 + blkcnt * 20;
1156 bool timed_out = false;
1157 bool multi_xfer = cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK;
1158
1159 debug("%s(%s): dest: %p, dma address: 0x%llx, blkcnt: %lu, start: %lu\n",
1160 __func__, mmc->dev->name, data->dest, dma_addr, blkcnt, start);
1161 debug("%s: rsp_sts: 0x%llx\n", __func__,
1162 read_csr(mmc, MIO_EMM_RSP_STS()));
1163 /* use max timeout for multi-block transfers */
1164 /* timeout = 0; */
1165
1166 /*
1167 * If we have a valid SD card in the slot, we set the response bit
1168 * mask to check for CRC errors and timeouts only.
1169 * Otherwise, use the default power on reset value.
1170 */
1171 write_csr(mmc, MIO_EMM_STS_MASK(),
1172 IS_SD(mmc) ? 0x00b00000ull : 0xe4390080ull);
1173 invalidate_dcache_range((u64)data->dest,
1174 (u64)data->dest + blkcnt * data->blocksize);
1175
1176 if (multi_xfer) {
1177 octeontx_mmc_start_dma(mmc, false, false, start, dma_addr,
1178 blkcnt, timeout);
1179 timed_out = !!octeontx_mmc_wait_dma(mmc, false, timeout,
1180 verbose);
1181 rsp_sts.u = read_csr(mmc, MIO_EMM_RSP_STS());
1182 if (timed_out || rsp_sts.s.dma_val || rsp_sts.s.dma_pend) {
1183 if (!verbose)
1184 return 0;
1185
1186 pr_err("%s(%s): Error: DMA timed out. rsp_sts: 0x%llx, emm_int: 0x%llx, dma_int: 0x%llx, rsp_lo: 0x%llx\n",
1187 __func__, mmc->dev->name, rsp_sts.u,
1188 read_csr(mmc, MIO_EMM_INT()),
1189 read_csr(mmc, MIO_EMM_DMA_INT()),
1190 read_csr(mmc, MIO_EMM_RSP_LO()));
1191 pr_err("%s: block count: %lu, start: 0x%lx\n",
1192 __func__, blkcnt, start);
1193 octeontx_mmc_print_registers(mmc);
1194 return 0;
1195 }
1196 } else {
1197 count = blkcnt;
1198 timeout = 1000;
1199 do {
1200 octeontx_mmc_start_dma(mmc, false, false, start,
1201 dma_addr, 1, timeout);
1202 dma_addr += mmc->read_bl_len;
1203 start++;
1204
1205 timed_out = !!octeontx_mmc_wait_dma(mmc, false,
1206 timeout, verbose);
1207 rsp_sts.u = read_csr(mmc, MIO_EMM_RSP_STS());
1208 if (timed_out || rsp_sts.s.dma_val ||
1209 rsp_sts.s.dma_pend) {
1210 if (verbose) {
1211 pr_err("%s: Error: DMA timed out. rsp_sts: 0x%llx, emm_int: 0x%llx, dma_int: 0x%llx, rsp_lo: 0x%llx\n",
1212 __func__, rsp_sts.u,
1213 read_csr(mmc, MIO_EMM_INT()),
1214 read_csr(mmc, MIO_EMM_DMA_INT()),
1215 read_csr(mmc, MIO_EMM_RSP_LO()));
1216 pr_err("%s: block count: 1, start: 0x%lx\n",
1217 __func__, start);
1218 octeontx_mmc_print_registers(mmc);
1219 }
1220 return blkcnt - count;
1221 }
1222 WATCHDOG_RESET();
1223 } while (--count);
1224 }
1225 #ifdef DEBUG
1226 debug("%s(%s): Read %lu (0x%lx) blocks starting at block %u (0x%x) to address %p (dma address 0x%llx)\n",
1227 __func__, mmc->dev->name, blkcnt, blkcnt,
1228 cmd->cmdarg, cmd->cmdarg, data->dest,
1229 dm_pci_virt_to_mem(host->dev, data->dest));
1230 print_buffer(0, data->dest, 1, 0x200, 0);
1231 #endif
1232 return blkcnt;
1233 }
1234
octeontx_mmc_poll_ready(struct mmc * mmc,ulong timeout)1235 static int octeontx_mmc_poll_ready(struct mmc *mmc, ulong timeout)
1236 {
1237 ulong start;
1238 struct mmc_cmd cmd;
1239 int err;
1240 bool not_ready = false;
1241
1242 memset(&cmd, 0, sizeof(cmd));
1243 cmd.cmdidx = MMC_CMD_SEND_STATUS;
1244 cmd.cmdarg = mmc->rca << 16;
1245 cmd.resp_type = MMC_RSP_R1;
1246 start = get_timer(0);
1247 do {
1248 err = octeontx_mmc_send_cmd(mmc, &cmd, NULL);
1249 if (err) {
1250 pr_err("%s(%s): MMC command error: %d; Retry...\n",
1251 __func__, mmc->dev->name, err);
1252 not_ready = true;
1253 } else if (cmd.response[0] & R1_READY_FOR_DATA) {
1254 return 0;
1255 }
1256 WATCHDOG_RESET();
1257 } while (get_timer(start) < timeout);
1258
1259 if (not_ready)
1260 pr_err("%s(%s): MMC command error; Retry timeout\n",
1261 __func__, mmc->dev->name);
1262 return -ETIMEDOUT;
1263 }
1264
octeontx_mmc_write_blocks(struct mmc * mmc,struct mmc_cmd * cmd,struct mmc_data * data)1265 static ulong octeontx_mmc_write_blocks(struct mmc *mmc, struct mmc_cmd *cmd,
1266 struct mmc_data *data)
1267 {
1268 struct octeontx_mmc_host *host = mmc_to_host(mmc);
1269 ulong start = cmd->cmdarg;
1270 ulong blkcnt = data->blocks;
1271 dma_addr_t dma_addr;
1272 union mio_emm_rsp_sts rsp_sts;
1273 union mio_emm_sts_mask emm_sts_mask;
1274 ulong timeout;
1275 int count;
1276 bool timed_out = false;
1277 bool multi_xfer = (blkcnt > 1) &&
1278 ((IS_SD(mmc) && mmc->scr[0] & 2) || !IS_SD(mmc));
1279
1280 octeontx_mmc_switch_to(mmc);
1281 emm_sts_mask.u = 0;
1282 emm_sts_mask.s.sts_msk = R1_BLOCK_WRITE_MASK;
1283 write_csr(mmc, MIO_EMM_STS_MASK(), emm_sts_mask.u);
1284
1285 if (octeontx_mmc_poll_ready(mmc, 10000)) {
1286 pr_err("%s(%s): Ready timed out\n", __func__, mmc->dev->name);
1287 return 0;
1288 }
1289 flush_dcache_range((u64)data->src,
1290 (u64)data->src + blkcnt * mmc->write_bl_len);
1291 dma_addr = (u64)dm_pci_virt_to_mem(host->dev, (void *)data->src);
1292 if (multi_xfer) {
1293 timeout = 5000 + 100 * blkcnt;
1294 octeontx_mmc_start_dma(mmc, true, false, start, dma_addr,
1295 blkcnt, timeout);
1296 timed_out = !!octeontx_mmc_wait_dma(mmc, true, timeout, true);
1297 rsp_sts.u = read_csr(mmc, MIO_EMM_RSP_STS());
1298 if (timed_out || rsp_sts.s.dma_val || rsp_sts.s.dma_pend) {
1299 pr_err("%s(%s): Error: multi-DMA timed out after %lums. rsp_sts: 0x%llx, emm_int: 0x%llx, emm_dma_int: 0x%llx, rsp_sts_lo: 0x%llx, emm_dma: 0x%llx\n",
1300 __func__, mmc->dev->name, timeout,
1301 rsp_sts.u,
1302 read_csr(mmc, MIO_EMM_INT()),
1303 read_csr(mmc, MIO_EMM_DMA_INT()),
1304 read_csr(mmc, MIO_EMM_RSP_LO()),
1305 read_csr(mmc, MIO_EMM_DMA()));
1306 return 0;
1307 }
1308 } else {
1309 timeout = 5000;
1310 count = blkcnt;
1311 do {
1312 octeontx_mmc_start_dma(mmc, true, false, start,
1313 dma_addr, 1, timeout);
1314 dma_addr += mmc->read_bl_len;
1315 start++;
1316
1317 timed_out = !!octeontx_mmc_wait_dma(mmc, true, timeout,
1318 true);
1319 rsp_sts.u = read_csr(mmc, MIO_EMM_RSP_STS());
1320 if (timed_out || rsp_sts.s.dma_val ||
1321 rsp_sts.s.dma_pend) {
1322 pr_err("%s(%s): Error: single-DMA timed out after %lums. rsp_sts: 0x%llx, emm_int: 0x%llx, emm_dma_int: 0x%llx, rsp_sts_lo: 0x%llx, emm_dma: 0x%llx\n",
1323 __func__, mmc->dev->name, timeout,
1324 rsp_sts.u,
1325 read_csr(mmc, MIO_EMM_RSP_STS()),
1326 read_csr(mmc, MIO_EMM_DMA_INT()),
1327 read_csr(mmc, MIO_EMM_RSP_LO()),
1328 read_csr(mmc, MIO_EMM_DMA()));
1329 return blkcnt - count;
1330 }
1331 WATCHDOG_RESET();
1332 } while (--count);
1333 }
1334
1335 return blkcnt;
1336 }
1337
1338 /**
1339 * Send a command to the eMMC/SD device
1340 *
1341 * @param mmc mmc device
1342 * @param cmd cmd to send and response
1343 * @param data additional data
1344 * @param flags
1345 * @return 0 for success, otherwise error
1346 */
octeontx_mmc_send_cmd(struct mmc * mmc,struct mmc_cmd * cmd,struct mmc_data * data)1347 static int octeontx_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1348 struct mmc_data *data)
1349 {
1350 struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
1351 const char *name = slot->dev->name;
1352 struct octeontx_mmc_cr_mods mods = {0, 0};
1353 union mio_emm_rsp_sts rsp_sts;
1354 union mio_emm_cmd emm_cmd;
1355 union mio_emm_rsp_lo rsp_lo;
1356 union mio_emm_buf_idx emm_buf_idx;
1357 union mio_emm_buf_dat emm_buf_dat;
1358 ulong start;
1359 int i;
1360 ulong blkcnt;
1361
1362 /**
1363 * This constant has a 1 bit for each command which should have a short
1364 * timeout and a 0 for each bit with a long timeout. Currently the
1365 * following commands have a long timeout:
1366 * CMD6, CMD17, CMD18, CMD24, CMD25, CMD32, CMD33, CMD35, CMD36 and
1367 * CMD38.
1368 */
1369 static const u64 timeout_short = 0xFFFFFFA4FCF9FFDFull;
1370 uint timeout;
1371
1372 if (cmd->cmdidx == MMC_CMD_SEND_EXT_CSD) {
1373 union mio_emm_rca emm_rca;
1374
1375 emm_rca.u = 0;
1376 emm_rca.s.card_rca = mmc->rca;
1377 write_csr(mmc, MIO_EMM_RCA(), emm_rca.u);
1378 }
1379
1380 if (timeout_short & (1ull << cmd->cmdidx))
1381 timeout = MMC_TIMEOUT_SHORT;
1382 else if (cmd->cmdidx == MMC_CMD_SWITCH && IS_SD(mmc))
1383 timeout = 2560;
1384 else if (cmd->cmdidx == MMC_CMD_ERASE)
1385 timeout = MMC_TIMEOUT_ERASE;
1386 else
1387 timeout = MMC_TIMEOUT_LONG;
1388
1389 debug("%s(%s): cmd idx: %u, arg: 0x%x, resp type: 0x%x, timeout: %u\n",
1390 __func__, name, cmd->cmdidx, cmd->cmdarg, cmd->resp_type,
1391 timeout);
1392 if (data)
1393 debug(" data: addr: %p, flags: 0x%x, blocks: %u, blocksize: %u\n",
1394 data->dest, data->flags, data->blocks, data->blocksize);
1395
1396 octeontx_mmc_switch_to(mmc);
1397
1398 /* Clear any interrupts */
1399 write_csr(mmc, MIO_EMM_INT(), read_csr(mmc, MIO_EMM_INT()));
1400
1401 /*
1402 * We need to override the default command types and response types
1403 * when dealing with SD cards.
1404 */
1405 mods = octeontx_mmc_get_cr_mods(mmc, cmd, data);
1406
1407 /* Handle block read/write/stop operations */
1408 switch (cmd->cmdidx) {
1409 case MMC_CMD_GO_IDLE_STATE:
1410 slot->tuned = false;
1411 slot->hs200_tuned = false;
1412 slot->hs400_tuned = false;
1413 break;
1414 case MMC_CMD_STOP_TRANSMISSION:
1415 return 0;
1416 case MMC_CMD_READ_MULTIPLE_BLOCK:
1417 case MMC_CMD_READ_SINGLE_BLOCK:
1418 pr_debug("%s(%s): Reading blocks\n", __func__, name);
1419 blkcnt = octeontx_mmc_read_blocks(mmc, cmd, data, true);
1420 return (blkcnt > 0) ? 0 : -1;
1421 case MMC_CMD_WRITE_MULTIPLE_BLOCK:
1422 case MMC_CMD_WRITE_SINGLE_BLOCK:
1423 blkcnt = octeontx_mmc_write_blocks(mmc, cmd, data);
1424 return (blkcnt > 0) ? 0 : -1;
1425 case MMC_CMD_SELECT_CARD:
1426 /* Set the RCA register (is it set automatically?) */
1427 if (IS_SD(mmc)) {
1428 union mio_emm_rca emm_rca;
1429
1430 emm_rca.u = 0;
1431 emm_rca.s.card_rca = (cmd->cmdarg >> 16);
1432 write_csr(mmc, MIO_EMM_RCA(), emm_rca.u);
1433 debug("%s: Set SD relative address (RCA) to 0x%x\n",
1434 __func__, emm_rca.s.card_rca);
1435 }
1436 break;
1437
1438 case MMC_CMD_SWITCH:
1439 if (!data && !slot->is_acmd)
1440 octeontx_mmc_track_switch(mmc, cmd->cmdarg);
1441 break;
1442 }
1443
1444 emm_cmd.u = 0;
1445 emm_cmd.s.cmd_val = 1;
1446 emm_cmd.s.bus_id = slot->bus_id;
1447 emm_cmd.s.cmd_idx = cmd->cmdidx;
1448 emm_cmd.s.arg = cmd->cmdarg;
1449 emm_cmd.s.ctype_xor = mods.ctype_xor;
1450 emm_cmd.s.rtype_xor = mods.rtype_xor;
1451 if (data && data->blocks == 1 && data->blocksize != 512) {
1452 emm_cmd.s.offset =
1453 64 - ((data->blocks * data->blocksize) / 8);
1454 debug("%s: offset set to %u\n", __func__, emm_cmd.s.offset);
1455 }
1456
1457 if (data && data->flags & MMC_DATA_WRITE) {
1458 u8 *src = (u8 *)data->src;
1459
1460 if (!src) {
1461 pr_err("%s(%s): Error: data source for cmd 0x%x is NULL!\n",
1462 __func__, name, cmd->cmdidx);
1463 return -1;
1464 }
1465 if (data->blocksize > 512) {
1466 pr_err("%s(%s): Error: data for cmd 0x%x exceeds 512 bytes\n",
1467 __func__, name, cmd->cmdidx);
1468 return -1;
1469 }
1470 #ifdef DEBUG
1471 debug("%s: Sending %d bytes data\n", __func__, data->blocksize);
1472 print_buffer(0, src, 1, data->blocksize, 0);
1473 #endif
1474 emm_buf_idx.u = 0;
1475 emm_buf_idx.s.inc = 1;
1476 write_csr(mmc, MIO_EMM_BUF_IDX(), emm_buf_idx.u);
1477 for (i = 0; i < (data->blocksize + 7) / 8; i++) {
1478 memcpy(&emm_buf_dat.u, src, sizeof(emm_buf_dat.u));
1479 write_csr(mmc, MIO_EMM_BUF_DAT(),
1480 cpu_to_be64(emm_buf_dat.u));
1481 src += sizeof(emm_buf_dat.u);
1482 }
1483 write_csr(mmc, MIO_EMM_BUF_IDX(), 0);
1484 }
1485 debug("%s(%s): Sending command %u (emm_cmd: 0x%llx)\n", __func__,
1486 name, cmd->cmdidx, emm_cmd.u);
1487 set_wdog(mmc, timeout * 1000);
1488 write_csr(mmc, MIO_EMM_CMD(), emm_cmd.u);
1489
1490 /* Wait for command to finish or time out */
1491 start = get_timer(0);
1492 do {
1493 rsp_sts.u = read_csr(mmc, MIO_EMM_RSP_STS());
1494 WATCHDOG_RESET();
1495 } while (!rsp_sts.s.cmd_done && !rsp_sts.s.rsp_timeout &&
1496 (get_timer(start) < timeout + 10));
1497 octeontx_mmc_print_rsp_errors(mmc, rsp_sts);
1498 if (rsp_sts.s.rsp_timeout || !rsp_sts.s.cmd_done) {
1499 debug("%s(%s): Error: command %u(0x%x) timed out. rsp_sts: 0x%llx\n",
1500 __func__, name, cmd->cmdidx, cmd->cmdarg, rsp_sts.u);
1501 octeontx_mmc_print_registers(mmc);
1502 return -ETIMEDOUT;
1503 }
1504 if (rsp_sts.s.rsp_crc_err) {
1505 debug("%s(%s): RSP CRC error, rsp_sts: 0x%llx, cmdidx: %u, arg: 0x%08x\n",
1506 __func__, name, rsp_sts.u, cmd->cmdidx, cmd->cmdarg);
1507 octeontx_mmc_print_registers(mmc);
1508 return -1;
1509 }
1510 if (slot->bus_id != rsp_sts.s.bus_id) {
1511 pr_warn("%s(%s): bus id mismatch, got %d, expected %d for command 0x%x(0x%x)\n",
1512 __func__, name,
1513 rsp_sts.s.bus_id, slot->bus_id,
1514 cmd->cmdidx, cmd->cmdarg);
1515 goto error;
1516 }
1517 if (rsp_sts.s.rsp_bad_sts) {
1518 rsp_lo.u = read_csr(mmc, MIO_EMM_RSP_LO());
1519 debug("%s: Bad response for bus id %d, cmd id %d:\n"
1520 " rsp_timeout: %d\n"
1521 " rsp_bad_sts: %d\n"
1522 " rsp_crc_err: %d\n",
1523 __func__, slot->bus_id, cmd->cmdidx,
1524 rsp_sts.s.rsp_timeout,
1525 rsp_sts.s.rsp_bad_sts,
1526 rsp_sts.s.rsp_crc_err);
1527 if (rsp_sts.s.rsp_type == 1 && rsp_sts.s.rsp_bad_sts) {
1528 debug(" Response status: 0x%llx\n",
1529 (rsp_lo.u >> 8) & 0xffffffff);
1530 #ifdef DEBUG
1531 mmc_print_status((rsp_lo.u >> 8) & 0xffffffff);
1532 #endif
1533 }
1534 goto error;
1535 }
1536 if (rsp_sts.s.cmd_idx != cmd->cmdidx) {
1537 debug("%s(%s): Command response index %d does not match command index %d\n",
1538 __func__, name, rsp_sts.s.cmd_idx, cmd->cmdidx);
1539 octeontx_print_rsp_sts(mmc);
1540 debug("%s: rsp_lo: 0x%llx\n", __func__,
1541 read_csr(mmc, MIO_EMM_RSP_LO()));
1542
1543 goto error;
1544 }
1545
1546 slot->is_acmd = (cmd->cmdidx == MMC_CMD_APP_CMD);
1547
1548 if (!cmd->resp_type & MMC_RSP_PRESENT)
1549 debug(" Response type: 0x%x, no response expected\n",
1550 cmd->resp_type);
1551 /* Get the response if present */
1552 if (rsp_sts.s.rsp_val && (cmd->resp_type & MMC_RSP_PRESENT)) {
1553 union mio_emm_rsp_hi rsp_hi;
1554
1555 rsp_lo.u = read_csr(mmc, MIO_EMM_RSP_LO());
1556
1557 switch (rsp_sts.s.rsp_type) {
1558 case 1:
1559 case 3:
1560 case 4:
1561 case 5:
1562 cmd->response[0] = (rsp_lo.u >> 8) & 0xffffffffull;
1563 debug(" response: 0x%08x\n",
1564 cmd->response[0]);
1565 cmd->response[1] = 0;
1566 cmd->response[2] = 0;
1567 cmd->response[3] = 0;
1568 break;
1569 case 2:
1570 cmd->response[3] = rsp_lo.u & 0xffffffff;
1571 cmd->response[2] = (rsp_lo.u >> 32) & 0xffffffff;
1572 rsp_hi.u = read_csr(mmc, MIO_EMM_RSP_HI());
1573 cmd->response[1] = rsp_hi.u & 0xffffffff;
1574 cmd->response[0] = (rsp_hi.u >> 32) & 0xffffffff;
1575 debug(" response: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1576 cmd->response[0], cmd->response[1],
1577 cmd->response[2], cmd->response[3]);
1578 break;
1579 default:
1580 pr_err("%s(%s): Unknown response type 0x%x for command %d, arg: 0x%x, rsp_sts: 0x%llx\n",
1581 __func__, name, rsp_sts.s.rsp_type, cmd->cmdidx,
1582 cmd->cmdarg, rsp_sts.u);
1583 return -1;
1584 }
1585 } else {
1586 debug(" Response not expected\n");
1587 }
1588
1589 if (data && data->flags & MMC_DATA_READ) {
1590 u8 *dest = (u8 *)data->dest;
1591
1592 if (!dest) {
1593 pr_err("%s(%s): Error, destination buffer NULL!\n",
1594 __func__, mmc->dev->name);
1595 goto error;
1596 }
1597 if (data->blocksize > 512) {
1598 printf("%s(%s): Error: data size %u exceeds 512\n",
1599 __func__, mmc->dev->name,
1600 data->blocksize);
1601 goto error;
1602 }
1603 emm_buf_idx.u = 0;
1604 emm_buf_idx.s.inc = 1;
1605 write_csr(mmc, MIO_EMM_BUF_IDX(), emm_buf_idx.u);
1606 for (i = 0; i < (data->blocksize + 7) / 8; i++) {
1607 emm_buf_dat.u = read_csr(mmc, MIO_EMM_BUF_DAT());
1608 emm_buf_dat.u = be64_to_cpu(emm_buf_dat.u);
1609 memcpy(dest, &emm_buf_dat.u, sizeof(emm_buf_dat.u));
1610 dest += sizeof(emm_buf_dat.u);
1611 }
1612 write_csr(mmc, MIO_EMM_BUF_IDX(), 0);
1613 #ifdef DEBUG
1614 debug("%s: Received %d bytes data\n", __func__,
1615 data->blocksize);
1616 print_buffer(0, data->dest, 1, data->blocksize, 0);
1617 #endif
1618 }
1619
1620 return 0;
1621 error:
1622 #ifdef DEBUG
1623 octeontx_mmc_print_registers(mmc);
1624 #endif
1625 return -1;
1626 }
1627
octeontx_mmc_dev_send_cmd(struct udevice * dev,struct mmc_cmd * cmd,struct mmc_data * data)1628 static int octeontx_mmc_dev_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1629 struct mmc_data *data)
1630 {
1631 return octeontx_mmc_send_cmd(dev_to_mmc(dev), cmd, data);
1632 }
1633
1634 #ifdef MMC_SUPPORTS_TUNING
octeontx_mmc_test_cmd(struct mmc * mmc,u32 opcode,int * statp)1635 static int octeontx_mmc_test_cmd(struct mmc *mmc, u32 opcode, int *statp)
1636 {
1637 struct mmc_cmd cmd;
1638 int err;
1639
1640 memset(&cmd, 0, sizeof(cmd));
1641
1642 debug("%s(%s, %u, %p)\n", __func__, mmc->dev->name, opcode, statp);
1643 cmd.cmdidx = opcode;
1644 cmd.resp_type = MMC_RSP_R1;
1645 cmd.cmdarg = mmc->rca << 16;
1646
1647 err = octeontx_mmc_send_cmd(mmc, &cmd, NULL);
1648 if (err)
1649 debug("%s(%s, %u) returned %d\n", __func__,
1650 mmc->dev->name, opcode, err);
1651 if (statp)
1652 *statp = cmd.response[0];
1653 return err;
1654 }
1655
octeontx_mmc_test_get_ext_csd(struct mmc * mmc,u32 opcode,int * statp)1656 static int octeontx_mmc_test_get_ext_csd(struct mmc *mmc, u32 opcode,
1657 int *statp)
1658 {
1659 struct mmc_cmd cmd;
1660 struct mmc_data data;
1661 int err;
1662 u8 ext_csd[MMC_MAX_BLOCK_LEN];
1663
1664 debug("%s(%s, %u, %p)\n", __func__, mmc->dev->name, opcode, statp);
1665 memset(&cmd, 0, sizeof(cmd));
1666
1667 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
1668 cmd.resp_type = MMC_RSP_R1;
1669 cmd.cmdarg = 0;
1670
1671 data.dest = (char *)ext_csd;
1672 data.blocks = 1;
1673 data.blocksize = MMC_MAX_BLOCK_LEN;
1674 data.flags = MMC_DATA_READ;
1675
1676 err = octeontx_mmc_send_cmd(mmc, &cmd, &data);
1677 if (statp)
1678 *statp = cmd.response[0];
1679
1680 return err;
1681 }
1682
1683 /**
1684 * Wrapper to set the MIO_EMM_TIMING register
1685 *
1686 * @param mmc pointer to mmc data structure
1687 * @param emm_timing New emm_timing register value
1688 *
1689 * On some devices it is possible that changing the data out value can
1690 * cause a glitch on an internal fifo. This works around this problem
1691 * by performing a soft-reset immediately before setting the timing register.
1692 *
1693 * Note: this function should not be called from any function that
1694 * performs DMA or block operations since not all registers are
1695 * preserved.
1696 */
octeontx_mmc_set_emm_timing(struct mmc * mmc,union mio_emm_timing emm_timing)1697 static void octeontx_mmc_set_emm_timing(struct mmc *mmc,
1698 union mio_emm_timing emm_timing)
1699 {
1700 union mio_emm_cfg emm_cfg;
1701 struct octeontx_mmc_slot *slot = mmc->priv;
1702 union mio_emm_debug emm_debug;
1703
1704 debug("%s(%s, 0x%llx) din: %u\n", __func__, mmc->dev->name,
1705 emm_timing.u, emm_timing.s.data_in_tap);
1706
1707 udelay(1);
1708 if (slot->host->tap_requires_noclk) {
1709 /* Turn off the clock */
1710 emm_debug.u = read_csr(mmc, MIO_EMM_DEBUG());
1711 emm_debug.s.emmc_clk_disable = 1;
1712 write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
1713 udelay(1);
1714 emm_debug.s.rdsync_rst = 1;
1715 write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
1716 }
1717 emm_cfg.u = read_csr(mmc, MIO_EMM_CFG());
1718 emm_cfg.s.bus_ena = 1 << 3;
1719 write_csr(mmc, MIO_EMM_CFG(), emm_cfg.u);
1720
1721 udelay(1);
1722 write_csr(mmc, MIO_EMM_TIMING(), emm_timing.u);
1723 udelay(1);
1724
1725 if (slot->host->tap_requires_noclk) {
1726 /* Turn on the clock */
1727 emm_debug.s.rdsync_rst = 0;
1728 write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
1729 udelay(1);
1730 emm_debug.s.emmc_clk_disable = 0;
1731 write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
1732 udelay(1);
1733 }
1734 emm_cfg.s.bus_ena = 1 << mmc_to_slot(mmc)->bus_id;
1735 write_csr(mmc, MIO_EMM_CFG(), emm_cfg.u);
1736 }
1737
1738 static const u8 octeontx_hs400_tuning_block[512] = {
1739 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
1740 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
1741 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
1742 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
1743 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
1744 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
1745 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
1746 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
1747 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
1748 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
1749 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
1750 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
1751 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
1752 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
1753 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
1754 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
1755 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
1756 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
1757 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
1758 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
1759 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
1760 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
1761 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
1762 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
1763 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
1764 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
1765 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
1766 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
1767 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
1768 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
1769 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
1770 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
1771 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
1772 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
1773 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
1774 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
1775 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
1776 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
1777 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
1778 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
1779 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
1780 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
1781 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
1782 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
1783 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
1784 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
1785 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
1786 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
1787 0xff, 0x00, 0x00, 0xff, 0xff, 0x00, 0xff, 0x00,
1788 0x00, 0xff, 0x00, 0xff, 0x55, 0xaa, 0x55, 0xaa,
1789 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
1790 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
1791 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
1792 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
1793 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
1794 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
1795 0xff, 0x00, 0xff, 0x00, 0xff, 0x00, 0xff, 0x00,
1796 0x00, 0xff, 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,
1797 0x01, 0xfe, 0x01, 0xfe, 0xcc, 0xcc, 0xcc, 0xff,
1798 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
1799 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
1800 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
1801 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
1802 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
1803
1804 };
1805
1806 /**
1807 * Perform tuning in HS400 mode
1808 *
1809 * @param[in] mmc mmc data structure
1810 *
1811 * @ret 0 for success, otherwise error
1812 */
octeontx_tune_hs400(struct mmc * mmc)1813 static int octeontx_tune_hs400(struct mmc *mmc)
1814 {
1815 struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
1816 struct mmc_cmd cmd;
1817 struct mmc_data data;
1818 union mio_emm_timing emm_timing;
1819 u8 buffer[mmc->read_bl_len];
1820 int tap_adj;
1821 int err = -1;
1822 int tap;
1823 int run = 0;
1824 int start_run = -1;
1825 int best_run = 0;
1826 int best_start = -1;
1827 bool prev_ok = false;
1828 char env_name[64];
1829 char how[MAX_NO_OF_TAPS + 1] = "";
1830
1831 if (slot->hs400_tuning_block == -1)
1832 return 0;
1833
1834 /* The eMMC standard disables all tuning support when operating in
1835 * DDR modes like HS400. The problem with this is that there are
1836 * many cases where the HS200 tuning does not work for HS400 mode.
1837 * In order to perform this tuning, while in HS200 a block is written
1838 * to a block specified in the device tree (marvell,hs400-tuning-block)
1839 * which is used for tuning in this function by repeatedly reading
1840 * this block and comparing the data and return code. This function
1841 * chooses the data input tap in the middle of the longest run of
1842 * successful read operations.
1843 */
1844
1845 emm_timing = slot->hs200_taps;
1846 debug("%s(%s): Start ci: %d, co: %d, di: %d, do: %d\n",
1847 __func__, mmc->dev->name, emm_timing.s.cmd_in_tap,
1848 emm_timing.s.cmd_out_tap, emm_timing.s.data_in_tap,
1849 emm_timing.s.data_out_tap);
1850 memset(buffer, 0xdb, sizeof(buffer));
1851
1852 snprintf(env_name, sizeof(env_name), "emmc%d_data_in_tap_hs400",
1853 slot->bus_id);
1854 tap = env_get_ulong(env_name, 10, -1L);
1855 if (tap >= 0 && tap < MAX_NO_OF_TAPS) {
1856 printf("Overriding data input tap for HS400 mode to %d\n", tap);
1857 emm_timing.s.data_in_tap = tap;
1858 octeontx_mmc_set_emm_timing(mmc, emm_timing);
1859 return 0;
1860 }
1861
1862 for (tap = 0; tap <= MAX_NO_OF_TAPS; tap++, prev_ok = !err) {
1863 if (tap < MAX_NO_OF_TAPS) {
1864 debug("%s: Testing data in tap %d\n", __func__, tap);
1865 emm_timing.s.data_in_tap = tap;
1866 octeontx_mmc_set_emm_timing(mmc, emm_timing);
1867
1868 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
1869 cmd.cmdarg = slot->hs400_tuning_block;
1870 cmd.resp_type = MMC_RSP_R1;
1871 data.dest = (void *)buffer;
1872 data.blocks = 1;
1873 data.blocksize = mmc->read_bl_len;
1874 data.flags = MMC_DATA_READ;
1875 err = !octeontx_mmc_read_blocks(mmc, &cmd, &data,
1876 false);
1877 if (err || memcmp(buffer, octeontx_hs400_tuning_block,
1878 sizeof(buffer))) {
1879 #ifdef DEBUG
1880 if (!err) {
1881 debug("%s: data mismatch. Read:\n",
1882 __func__);
1883 print_buffer(0, buffer, 1,
1884 sizeof(buffer), 0);
1885 debug("\nExpected:\n");
1886 print_buffer(0,
1887 octeontx_hs400_tuning_block, 1,
1888 sizeof(octeontx_hs400_tuning_block),
1889 0);
1890 } else {
1891 debug("%s: Error %d reading block\n",
1892 __func__, err);
1893 }
1894 #endif
1895 err = -EINVAL;
1896 } else {
1897 debug("%s: tap %d good\n", __func__, tap);
1898 }
1899 how[tap] = "-+"[!err];
1900 } else {
1901 err = -EINVAL;
1902 }
1903
1904 if (!err) {
1905 if (!prev_ok)
1906 start_run = tap;
1907 } else if (prev_ok) {
1908 run = tap - 1 - start_run;
1909 if (start_run >= 0 && run > best_run) {
1910 best_start = start_run;
1911 best_run = run;
1912 }
1913 }
1914 }
1915
1916 how[tap - 1] = '\0';
1917 if (best_start < 0) {
1918 printf("%s(%s): %lldMHz tuning failed for HS400\n",
1919 __func__, mmc->dev->name, slot->clock / 1000000);
1920 return -EINVAL;
1921 }
1922 tap = best_start + best_run / 2;
1923
1924 snprintf(env_name, sizeof(env_name), "emmc%d_data_in_tap_adj_hs400",
1925 slot->bus_id);
1926 tap_adj = env_get_ulong(env_name, 10, slot->hs400_tap_adj);
1927 /*
1928 * Keep it in range and if out of range force it back in with a small
1929 * buffer.
1930 */
1931 if (best_run > 3) {
1932 tap = tap + tap_adj;
1933 if (tap >= best_start + best_run)
1934 tap = best_start + best_run - 2;
1935 if (tap <= best_start)
1936 tap = best_start + 2;
1937 }
1938 how[tap] = '@';
1939 debug("Tuning: %s\n", how);
1940 debug("%s(%s): HS400 tap: best run start: %d, length: %d, tap: %d\n",
1941 __func__, mmc->dev->name, best_start, best_run, tap);
1942 slot->hs400_taps = slot->hs200_taps;
1943 slot->hs400_taps.s.data_in_tap = tap;
1944 slot->hs400_tuned = true;
1945 if (env_get_yesno("emmc_export_hs400_taps") > 0) {
1946 debug("%s(%s): Exporting HS400 taps\n",
1947 __func__, mmc->dev->name);
1948 env_set_ulong("emmc_timing_tap", slot->host->timing_taps);
1949 snprintf(env_name, sizeof(env_name),
1950 "emmc%d_hs400_data_in_tap_debug",
1951 slot->bus_id);
1952 env_set(env_name, how);
1953 snprintf(env_name, sizeof(env_name),
1954 "emmc%d_hs400_data_in_tap_val",
1955 slot->bus_id);
1956 env_set_ulong(env_name, tap);
1957 snprintf(env_name, sizeof(env_name),
1958 "emmc%d_hs400_data_in_tap_start",
1959 slot->bus_id);
1960 env_set_ulong(env_name, best_start);
1961 snprintf(env_name, sizeof(env_name),
1962 "emmc%d_hs400_data_in_tap_end",
1963 slot->bus_id);
1964 env_set_ulong(env_name, best_start + best_run);
1965 snprintf(env_name, sizeof(env_name),
1966 "emmc%d_hs400_cmd_in_tap",
1967 slot->bus_id);
1968 env_set_ulong(env_name, slot->hs400_taps.s.cmd_in_tap);
1969 snprintf(env_name, sizeof(env_name),
1970 "emmc%d_hs400_cmd_out_tap",
1971 slot->bus_id);
1972 env_set_ulong(env_name, slot->hs400_taps.s.cmd_out_tap);
1973 snprintf(env_name, sizeof(env_name),
1974 "emmc%d_hs400_cmd_out_delay",
1975 slot->bus_id);
1976 env_set_ulong(env_name, slot->cmd_out_hs400_delay);
1977 snprintf(env_name, sizeof(env_name),
1978 "emmc%d_hs400_data_out_tap",
1979 slot->bus_id);
1980 env_set_ulong(env_name, slot->hs400_taps.s.data_out_tap);
1981 snprintf(env_name, sizeof(env_name),
1982 "emmc%d_hs400_data_out_delay",
1983 slot->bus_id);
1984 env_set_ulong(env_name, slot->data_out_hs400_delay);
1985 } else {
1986 debug("%s(%s): HS400 environment export disabled\n",
1987 __func__, mmc->dev->name);
1988 }
1989 octeontx_mmc_set_timing(mmc);
1990
1991 return 0;
1992 }
1993
1994 struct adj {
1995 const char *name;
1996 u8 mask_shift;
1997 int (*test)(struct mmc *mmc, u32 opcode, int *error);
1998 u32 opcode;
1999 bool ddr_only;
2000 bool hs200_only;
2001 bool not_hs200_only;
2002 u8 num_runs;
2003 };
2004
2005 struct adj adj[] = {
2006 { "CMD_IN", 48, octeontx_mmc_test_cmd, MMC_CMD_SEND_STATUS,
2007 false, false, false, 2, },
2008 /* { "CMD_OUT", 32, octeontx_mmc_test_cmd, MMC_CMD_SEND_STATUS, },*/
2009 { "DATA_IN(HS200)", 16, mmc_send_tuning,
2010 MMC_CMD_SEND_TUNING_BLOCK_HS200, false, true, false, 2, },
2011 { "DATA_IN", 16, octeontx_mmc_test_get_ext_csd, 0, false, false,
2012 true, 2, },
2013 /* { "DATA_OUT", 0, octeontx_mmc_test_cmd, 0, true, false},*/
2014 { NULL, },
2015 };
2016
2017 /**
2018 * Perform tuning tests to find optimal timing
2019 *
2020 * @param mmc mmc device
2021 * @param adj parameter to tune
2022 * @param opcode command opcode to use
2023 *
2024 * @return 0 for success, -1 if tuning failed
2025 */
octeontx_mmc_adjust_tuning(struct mmc * mmc,struct adj * adj,u32 opcode)2026 static int octeontx_mmc_adjust_tuning(struct mmc *mmc, struct adj *adj,
2027 u32 opcode)
2028 {
2029 struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
2030 union mio_emm_timing timing;
2031 union mio_emm_debug emm_debug;
2032 int tap;
2033 int err = -1;
2034 int run = 0;
2035 int count;
2036 int start_run = -1;
2037 int best_run = 0;
2038 int best_start = -1;
2039 bool prev_ok = false;
2040 u64 tap_status = 0;
2041 const int tap_adj = slot->hs200_tap_adj;
2042 char how[MAX_NO_OF_TAPS + 1] = "";
2043 bool is_hs200 = mmc->selected_mode == MMC_HS_200;
2044
2045 debug("%s(%s, %s, %d), hs200: %d\n", __func__, mmc->dev->name,
2046 adj->name, opcode, is_hs200);
2047 octeontx_mmc_set_emm_timing(mmc,
2048 is_hs200 ? slot->hs200_taps : slot->taps);
2049
2050 #ifdef DEBUG
2051 if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
2052 printf("%s(%s): Before tuning %s, opcode: %d\n",
2053 __func__, mmc->dev->name, adj->name, opcode);
2054 octeontx_mmc_print_registers2(mmc, NULL);
2055 }
2056 #endif
2057
2058 /*
2059 * The algorithm to find the optimal timing is to start
2060 * at the end and work backwards and select the second
2061 * value that passes. Each test is repeated twice.
2062 */
2063 for (tap = 0; tap <= MAX_NO_OF_TAPS; tap++, prev_ok = !err) {
2064 if (tap < MAX_NO_OF_TAPS) {
2065 if (slot->host->tap_requires_noclk) {
2066 /* Turn off the clock */
2067 emm_debug.u = read_csr(mmc, MIO_EMM_DEBUG());
2068 emm_debug.s.emmc_clk_disable = 1;
2069 write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
2070 udelay(1);
2071 emm_debug.s.rdsync_rst = 1;
2072 write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
2073 udelay(1);
2074 }
2075
2076 timing.u = read_csr(mmc, MIO_EMM_TIMING());
2077 timing.u &= ~(0x3full << adj->mask_shift);
2078 timing.u |= (u64)tap << adj->mask_shift;
2079 write_csr(mmc, MIO_EMM_TIMING(), timing.u);
2080 debug("%s(%s): Testing ci: %d, co: %d, di: %d, do: %d\n",
2081 __func__, mmc->dev->name, timing.s.cmd_in_tap,
2082 timing.s.cmd_out_tap, timing.s.data_in_tap,
2083 timing.s.data_out_tap);
2084
2085 if (slot->host->tap_requires_noclk) {
2086 /* Turn off the clock */
2087 emm_debug.s.rdsync_rst = 0;
2088 write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
2089 udelay(1);
2090 emm_debug.u = read_csr(mmc, MIO_EMM_DEBUG());
2091 emm_debug.s.emmc_clk_disable = 0;
2092 write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
2093 udelay(1);
2094 }
2095 for (count = 0; count < 2; count++) {
2096 err = adj->test(mmc, opcode, NULL);
2097 if (err) {
2098 debug("%s(%s, %s): tap %d failed, count: %d, rsp_sts: 0x%llx, rsp_lo: 0x%llx\n",
2099 __func__, mmc->dev->name,
2100 adj->name, tap, count,
2101 read_csr(mmc,
2102 MIO_EMM_RSP_STS()),
2103 read_csr(mmc,
2104 MIO_EMM_RSP_LO()));
2105 debug("%s(%s, %s): tap: %d, do: %d, di: %d, co: %d, ci: %d\n",
2106 __func__, mmc->dev->name,
2107 adj->name, tap,
2108 timing.s.data_out_tap,
2109 timing.s.data_in_tap,
2110 timing.s.cmd_out_tap,
2111 timing.s.cmd_in_tap);
2112 break;
2113 }
2114 debug("%s(%s, %s): tap %d passed, count: %d, rsp_sts: 0x%llx, rsp_lo: 0x%llx\n",
2115 __func__, mmc->dev->name, adj->name, tap,
2116 count,
2117 read_csr(mmc, MIO_EMM_RSP_STS()),
2118 read_csr(mmc, MIO_EMM_RSP_LO()));
2119 }
2120 tap_status |= (u64)(!err) << tap;
2121 how[tap] = "-+"[!err];
2122 } else {
2123 /*
2124 * Putting the end+1 case in the loop simplifies
2125 * logic, allowing 'prev_ok' to process a sweet
2126 * spot in tuning which extends to the wall.
2127 */
2128 err = -EINVAL;
2129 }
2130 if (!err) {
2131 /*
2132 * If no CRC/etc errors in the response, but previous
2133 * failed, note the start of a new run.
2134 */
2135 debug(" prev_ok: %d\n", prev_ok);
2136 if (!prev_ok)
2137 start_run = tap;
2138 } else if (prev_ok) {
2139 run = tap - 1 - start_run;
2140 /* did we just exit a wider sweet spot? */
2141 if (start_run >= 0 && run > best_run) {
2142 best_start = start_run;
2143 best_run = run;
2144 }
2145 }
2146 }
2147 how[tap - 1] = '\0';
2148 if (best_start < 0) {
2149 printf("%s(%s, %s): %lldMHz tuning %s failed\n", __func__,
2150 mmc->dev->name, adj->name, slot->clock / 1000000,
2151 adj->name);
2152 return -EINVAL;
2153 }
2154
2155 tap = best_start + best_run / 2;
2156 debug(" tap %d is center, start: %d, run: %d\n", tap,
2157 best_start, best_run);
2158 if (is_hs200) {
2159 slot->hs200_taps.u &= ~(0x3full << adj->mask_shift);
2160 slot->hs200_taps.u |= (u64)tap << adj->mask_shift;
2161 } else {
2162 slot->taps.u &= ~(0x3full << adj->mask_shift);
2163 slot->taps.u |= (u64)tap << adj->mask_shift;
2164 }
2165 if (best_start < 0) {
2166 printf("%s(%s, %s): %lldMHz tuning %s failed\n", __func__,
2167 mmc->dev->name, adj->name, slot->clock / 1000000,
2168 adj->name);
2169 return -EINVAL;
2170 }
2171
2172 tap = best_start + best_run / 2;
2173 if (is_hs200 && (tap + tap_adj >= 0) && (tap + tap_adj < 64) &&
2174 tap_status & (1ULL << (tap + tap_adj))) {
2175 debug("Adjusting tap from %d by %d to %d\n",
2176 tap, tap_adj, tap + tap_adj);
2177 tap += tap_adj;
2178 }
2179 how[tap] = '@';
2180 debug("%s/%s %d/%d/%d %s\n", mmc->dev->name,
2181 adj->name, best_start, tap, best_start + best_run, how);
2182
2183 if (is_hs200) {
2184 slot->hs200_taps.u &= ~(0x3full << adj->mask_shift);
2185 slot->hs200_taps.u |= (u64)tap << adj->mask_shift;
2186 } else {
2187 slot->taps.u &= ~(0x3full << adj->mask_shift);
2188 slot->taps.u |= (u64)tap << adj->mask_shift;
2189 }
2190
2191 #ifdef DEBUG
2192 if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
2193 debug("%s(%s, %s): After successful tuning\n",
2194 __func__, mmc->dev->name, adj->name);
2195 debug("%s(%s, %s): tap: %d, new do: %d, di: %d, co: %d, ci: %d\n",
2196 __func__, mmc->dev->name, adj->name, tap,
2197 slot->taps.s.data_out_tap,
2198 slot->taps.s.data_in_tap,
2199 slot->taps.s.cmd_out_tap,
2200 slot->taps.s.cmd_in_tap);
2201 debug("%s(%s, %s): tap: %d, new do HS200: %d, di: %d, co: %d, ci: %d\n",
2202 __func__, mmc->dev->name, adj->name, tap,
2203 slot->hs200_taps.s.data_out_tap,
2204 slot->hs200_taps.s.data_in_tap,
2205 slot->hs200_taps.s.cmd_out_tap,
2206 slot->hs200_taps.s.cmd_in_tap);
2207 }
2208 #endif
2209 octeontx_mmc_set_timing(mmc);
2210
2211 if (is_hs200 && env_get_yesno("emmc_export_hs200_taps")) {
2212 char env_name[64];
2213
2214 env_set_ulong("emmc_timing_tap", slot->host->timing_taps);
2215 switch (opcode) {
2216 case MMC_CMD_SEND_TUNING_BLOCK:
2217 snprintf(env_name, sizeof(env_name),
2218 "emmc%d_hs200_data_in_tap_debug",
2219 slot->bus_id);
2220 env_set(env_name, how);
2221 snprintf(env_name, sizeof(env_name),
2222 "emmc%d_hs200_data_in_tap_val", slot->bus_id);
2223 env_set_ulong(env_name, tap);
2224 snprintf(env_name, sizeof(env_name),
2225 "emmc%d_hs200_data_in_tap_start",
2226 slot->bus_id);
2227 env_set_ulong(env_name, best_start);
2228 snprintf(env_name, sizeof(env_name),
2229 "emmc%d_hs200_data_in_tap_end",
2230 slot->bus_id);
2231 env_set_ulong(env_name, best_start + best_run);
2232 break;
2233 case MMC_CMD_SEND_STATUS:
2234 snprintf(env_name, sizeof(env_name),
2235 "emmc%d_hs200_cmd_in_tap_debug",
2236 slot->bus_id);
2237 env_set(env_name, how);
2238 snprintf(env_name, sizeof(env_name),
2239 "emmc%d_hs200_cmd_in_tap_val", slot->bus_id);
2240 env_set_ulong(env_name, tap);
2241 snprintf(env_name, sizeof(env_name),
2242 "emmc%d_hs200_cmd_in_tap_start",
2243 slot->bus_id);
2244 env_set_ulong(env_name, best_start);
2245 snprintf(env_name, sizeof(env_name),
2246 "emmc%d_hs200_cmd_in_tap_end",
2247 slot->bus_id);
2248 env_set_ulong(env_name, best_start + best_run);
2249 break;
2250 default:
2251 snprintf(env_name, sizeof(env_name),
2252 "emmc%d_hs200_data_out_tap", slot->bus_id);
2253 env_set_ulong(env_name, slot->data_out_hs200_delay);
2254 snprintf(env_name, sizeof(env_name),
2255 "emmc%d_hs200_cmd_out_tap", slot->bus_id);
2256 env_set_ulong(env_name, slot->cmd_out_hs200_delay);
2257 break;
2258 }
2259 }
2260
2261 return 0;
2262 }
2263
octeontx_mmc_execute_tuning(struct udevice * dev,u32 opcode)2264 static int octeontx_mmc_execute_tuning(struct udevice *dev, u32 opcode)
2265 {
2266 struct mmc *mmc = dev_to_mmc(dev);
2267 struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
2268 union mio_emm_timing emm_timing;
2269 int err;
2270 struct adj *a;
2271 bool is_hs200;
2272 char env_name[64];
2273
2274 pr_info("%s re-tuning, opcode 0x%x\n", dev->name, opcode);
2275
2276 if (slot->is_asim || slot->is_emul)
2277 return 0;
2278
2279 is_hs200 = (mmc->selected_mode == MMC_HS_200);
2280 if (is_hs200) {
2281 slot->hs200_tuned = false;
2282 slot->hs400_tuned = false;
2283 } else {
2284 slot->tuned = false;
2285 }
2286 octeontx_mmc_set_output_bus_timing(mmc);
2287 octeontx_mmc_set_input_bus_timing(mmc);
2288 emm_timing.u = read_csr(mmc, MIO_EMM_TIMING());
2289 if (mmc->selected_mode == MMC_HS_200) {
2290 slot->hs200_taps.s.cmd_out_tap = emm_timing.s.cmd_out_tap;
2291 slot->hs200_taps.s.data_out_tap = emm_timing.s.data_out_tap;
2292 } else {
2293 slot->taps.s.cmd_out_tap = emm_timing.s.cmd_out_tap;
2294 slot->taps.s.data_out_tap = emm_timing.s.data_out_tap;
2295 }
2296 octeontx_mmc_set_input_bus_timing(mmc);
2297 octeontx_mmc_set_output_bus_timing(mmc);
2298
2299 for (a = adj; a->name; a++) {
2300 ulong in_tap;
2301
2302 if (!strcmp(a->name, "CMD_IN")) {
2303 snprintf(env_name, sizeof(env_name),
2304 "emmc%d_cmd_in_tap", slot->bus_id);
2305 in_tap = env_get_ulong(env_name, 10, (ulong)-1);
2306 if (in_tap != (ulong)-1) {
2307 if (mmc->selected_mode == MMC_HS_200 ||
2308 a->hs200_only) {
2309 slot->hs200_taps.s.cmd_in_tap = in_tap;
2310 slot->hs400_taps.s.cmd_in_tap = in_tap;
2311 } else {
2312 slot->taps.s.cmd_in_tap = in_tap;
2313 }
2314 continue;
2315 }
2316 } else if (a->hs200_only &&
2317 !strcmp(a->name, "DATA_IN(HS200)")) {
2318 snprintf(env_name, sizeof(env_name),
2319 "emmc%d_data_in_tap_hs200", slot->bus_id);
2320 in_tap = env_get_ulong(env_name, 10, (ulong)-1);
2321 if (in_tap != (ulong)-1) {
2322 debug("%s(%s): Overriding HS200 data in tap to %d\n",
2323 __func__, dev->name, (int)in_tap);
2324 slot->hs200_taps.s.data_in_tap = in_tap;
2325 continue;
2326 }
2327 } else if (!a->hs200_only && !strcmp(a->name, "DATA_IN")) {
2328 snprintf(env_name, sizeof(env_name),
2329 "emmc%d_data_in_tap", slot->bus_id);
2330 in_tap = env_get_ulong(env_name, 10, (ulong)-1);
2331 if (in_tap != (ulong)-1) {
2332 debug("%s(%s): Overriding non-HS200 data in tap to %d\n",
2333 __func__, dev->name, (int)in_tap);
2334 slot->taps.s.data_in_tap = in_tap;
2335 continue;
2336 }
2337 }
2338
2339 debug("%s(%s): Testing: %s, mode: %s, opcode: %u\n", __func__,
2340 dev->name, a->name, mmc_mode_name(mmc->selected_mode),
2341 opcode);
2342
2343 /* Skip DDR only test when not in DDR mode */
2344 if (a->ddr_only && !mmc->ddr_mode) {
2345 debug("%s(%s): Skipping %s due to non-DDR mode\n",
2346 __func__, dev->name, a->name);
2347 continue;
2348 }
2349 /* Skip hs200 tests in non-hs200 mode and
2350 * non-hs200 tests in hs200 mode
2351 */
2352 if (is_hs200) {
2353 if (a->not_hs200_only) {
2354 debug("%s(%s): Skipping %s\n", __func__,
2355 dev->name, a->name);
2356 continue;
2357 }
2358 } else {
2359 if (a->hs200_only) {
2360 debug("%s(%s): Skipping %s\n", __func__,
2361 dev->name, a->name);
2362 continue;
2363 }
2364 }
2365
2366 err = octeontx_mmc_adjust_tuning(mmc, a, a->opcode ?
2367 a->opcode : opcode);
2368 if (err) {
2369 pr_err("%s(%s, %u): tuning %s failed\n", __func__,
2370 dev->name, opcode, a->name);
2371 return err;
2372 }
2373 }
2374
2375 octeontx_mmc_set_timing(mmc);
2376 if (is_hs200)
2377 slot->hs200_tuned = true;
2378 else
2379 slot->tuned = true;
2380
2381 if (slot->hs400_tuning_block != -1) {
2382 struct mmc_cmd cmd;
2383 struct mmc_data data;
2384 u8 buffer[mmc->read_bl_len];
2385
2386 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
2387 cmd.cmdarg = slot->hs400_tuning_block;
2388 cmd.resp_type = MMC_RSP_R1;
2389 data.dest = (void *)buffer;
2390 data.blocks = 1;
2391 data.blocksize = mmc->read_bl_len;
2392 data.flags = MMC_DATA_READ;
2393 err = octeontx_mmc_read_blocks(mmc, &cmd, &data, true) != 1;
2394
2395 if (err) {
2396 printf("%s: Cannot read HS400 tuning block %u\n",
2397 dev->name, slot->hs400_tuning_block);
2398 return err;
2399 }
2400 if (memcmp(buffer, octeontx_hs400_tuning_block,
2401 sizeof(buffer))) {
2402 debug("%s(%s): Writing new HS400 tuning block to block %d\n",
2403 __func__, dev->name, slot->hs400_tuning_block);
2404 cmd.cmdidx = MMC_CMD_WRITE_SINGLE_BLOCK;
2405 data.src = (void *)octeontx_hs400_tuning_block;
2406 data.flags = MMC_DATA_WRITE;
2407 err = !octeontx_mmc_write_blocks(mmc, &cmd, &data);
2408 if (err) {
2409 printf("%s: Cannot write HS400 tuning block %u\n",
2410 dev->name, slot->hs400_tuning_block);
2411 return -EINVAL;
2412 }
2413 }
2414 }
2415
2416 return 0;
2417 }
2418 #else /* MMC_SUPPORTS_TUNING */
octeontx_mmc_set_emm_timing(struct mmc * mmc,union mio_emm_timing emm_timing)2419 static void octeontx_mmc_set_emm_timing(struct mmc *mmc,
2420 union mio_emm_timing emm_timing)
2421 {
2422 }
2423 #endif /* MMC_SUPPORTS_TUNING */
2424
2425 /**
2426 * Calculate the clock period with rounding up
2427 *
2428 * @param mmc mmc device
2429 * @return clock period in system clocks for clk_lo + clk_hi
2430 */
octeontx_mmc_calc_clk_period(struct mmc * mmc)2431 static u32 octeontx_mmc_calc_clk_period(struct mmc *mmc)
2432 {
2433 struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
2434 struct octeontx_mmc_host *host = slot->host;
2435
2436 if (mmc->clock)
2437 return DIV_ROUND_UP(host->sys_freq, mmc->clock);
2438
2439 return 0;
2440 }
2441
octeontx_mmc_set_ios(struct udevice * dev)2442 static int octeontx_mmc_set_ios(struct udevice *dev)
2443 {
2444 struct octeontx_mmc_slot *slot = dev_to_mmc_slot(dev);
2445 struct mmc *mmc = &slot->mmc;
2446 struct octeontx_mmc_host *host = slot->host;
2447 union mio_emm_switch emm_switch;
2448 union mio_emm_modex mode;
2449 uint clock;
2450 int bus_width = 0;
2451 int clk_period = 0;
2452 int power_class = 10;
2453 int err = 0;
2454 bool is_hs200 = false;
2455 bool is_hs400 = false;
2456
2457 debug("%s(%s): Entry\n", __func__, dev->name);
2458 debug(" clock: %u, bus width: %u, mode: %u\n", mmc->clock,
2459 mmc->bus_width, mmc->selected_mode);
2460 debug(" host caps: 0x%x, card caps: 0x%x\n", mmc->host_caps,
2461 mmc->card_caps);
2462 octeontx_mmc_switch_to(mmc);
2463
2464 clock = mmc->clock;
2465 if (!clock)
2466 clock = mmc->cfg->f_min;
2467
2468 switch (mmc->bus_width) {
2469 case 8:
2470 bus_width = 2;
2471 break;
2472 case 4:
2473 bus_width = 1;
2474 break;
2475 case 1:
2476 bus_width = 0;
2477 break;
2478 default:
2479 pr_warn("%s(%s): Invalid bus width %d, defaulting to 1\n",
2480 __func__, dev->name, mmc->bus_width);
2481 bus_width = 0;
2482 }
2483
2484 /* DDR is available for 4/8 bit bus width */
2485 if (mmc->ddr_mode && bus_width)
2486 bus_width |= 4;
2487
2488 debug("%s: sys_freq: %llu\n", __func__, host->sys_freq);
2489 clk_period = octeontx_mmc_calc_clk_period(mmc);
2490
2491 emm_switch.u = 0;
2492 emm_switch.s.bus_width = bus_width;
2493 emm_switch.s.power_class = power_class;
2494 emm_switch.s.clk_hi = clk_period / 2;
2495 emm_switch.s.clk_lo = clk_period / 2;
2496
2497 debug("%s: last mode: %d, mode: %d, last clock: %u, clock: %u, ddr: %d\n",
2498 __func__, slot->last_mode, mmc->selected_mode,
2499 slot->last_clock, mmc->clock, mmc->ddr_mode);
2500 switch (mmc->selected_mode) {
2501 case MMC_LEGACY:
2502 break;
2503 case MMC_HS:
2504 case SD_HS:
2505 case MMC_HS_52:
2506 emm_switch.s.hs_timing = 1;
2507 break;
2508 case MMC_HS_200:
2509 is_hs200 = true;
2510 fallthrough;
2511 case UHS_SDR12:
2512 case UHS_SDR25:
2513 case UHS_SDR50:
2514 case UHS_SDR104:
2515 #if !defined(CONFIG_ARCH_OCTEON)
2516 emm_switch.s.hs200_timing = 1;
2517 #endif
2518 break;
2519 case MMC_HS_400:
2520 is_hs400 = true;
2521 fallthrough;
2522 case UHS_DDR50:
2523 case MMC_DDR_52:
2524 #if !defined(CONFIG_ARCH_OCTEON)
2525 emm_switch.s.hs400_timing = 1;
2526 #endif
2527 break;
2528 default:
2529 pr_err("%s(%s): Unsupported mode 0x%x\n", __func__, dev->name,
2530 mmc->selected_mode);
2531 return -1;
2532 }
2533 emm_switch.s.bus_id = slot->bus_id;
2534
2535 if (!is_hs200 && !is_hs400 &&
2536 (mmc->selected_mode != slot->last_mode ||
2537 mmc->clock != slot->last_clock) &&
2538 !mmc->ddr_mode) {
2539 slot->tuned = false;
2540 slot->last_mode = mmc->selected_mode;
2541 slot->last_clock = mmc->clock;
2542 }
2543
2544 if (CONFIG_IS_ENABLED(MMC_VERBOSE)) {
2545 debug("%s(%s): Setting bus mode to %s\n", __func__, dev->name,
2546 mmc_mode_name(mmc->selected_mode));
2547 } else {
2548 debug("%s(%s): Setting bus mode to 0x%x\n", __func__, dev->name,
2549 mmc->selected_mode);
2550 }
2551
2552 #if !defined(CONFIG_ARCH_OCTEON)
2553 debug(" Trying switch 0x%llx w%d hs:%d hs200:%d hs400:%d\n",
2554 emm_switch.u, emm_switch.s.bus_width, emm_switch.s.hs_timing,
2555 emm_switch.s.hs200_timing, emm_switch.s.hs400_timing);
2556 #endif
2557
2558 set_wdog(mmc, 1000);
2559 do_switch(mmc, emm_switch);
2560 mdelay(100);
2561 mode.u = read_csr(mmc, MIO_EMM_MODEX(slot->bus_id));
2562 #if !defined(CONFIG_ARCH_OCTEON)
2563 debug("%s(%s): mode: 0x%llx w:%d, hs:%d, hs200:%d, hs400:%d\n",
2564 __func__, dev->name, mode.u, mode.s.bus_width,
2565 mode.s.hs_timing, mode.s.hs200_timing, mode.s.hs400_timing);
2566 #endif
2567
2568 err = octeontx_mmc_configure_delay(mmc);
2569
2570 #ifdef MMC_SUPPORTS_TUNING
2571 if (!err && mmc->selected_mode == MMC_HS_400 && !slot->hs400_tuned) {
2572 debug("%s: Tuning HS400 mode\n", __func__);
2573 err = octeontx_tune_hs400(mmc);
2574 }
2575 #endif
2576
2577 return err;
2578 }
2579
2580 /**
2581 * Gets the status of the card detect pin
2582 */
octeontx_mmc_get_cd(struct udevice * dev)2583 static int octeontx_mmc_get_cd(struct udevice *dev)
2584 {
2585 struct octeontx_mmc_slot *slot = dev_to_mmc_slot(dev);
2586 int val = 1;
2587
2588 if (dm_gpio_is_valid(&slot->cd_gpio)) {
2589 val = dm_gpio_get_value(&slot->cd_gpio);
2590 val ^= slot->cd_inverted;
2591 }
2592 debug("%s(%s): cd: %d\n", __func__, dev->name, val);
2593 return val;
2594 }
2595
2596 /**
2597 * Gets the status of the write protect pin
2598 */
octeontx_mmc_get_wp(struct udevice * dev)2599 static int octeontx_mmc_get_wp(struct udevice *dev)
2600 {
2601 struct octeontx_mmc_slot *slot = dev_to_mmc_slot(dev);
2602 int val = 0;
2603
2604 if (dm_gpio_is_valid(&slot->wp_gpio)) {
2605 val = dm_gpio_get_value(&slot->wp_gpio);
2606 val ^= slot->wp_inverted;
2607 }
2608 debug("%s(%s): wp: %d\n", __func__, dev->name, val);
2609 return val;
2610 }
2611
2612 #if defined(CONFIG_ARCH_OCTEON)
octeontx_mmc_configure_delay(struct mmc * mmc)2613 static int octeontx_mmc_configure_delay(struct mmc *mmc)
2614 {
2615 struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
2616 union mio_emm_sample emm_sample;
2617
2618 debug("%s(%s)\n", __func__, mmc->dev->name);
2619
2620 emm_sample.u = 0;
2621 emm_sample.s.cmd_cnt = slot->cmd_cnt;
2622 emm_sample.s.dat_cnt = slot->dat_cnt;
2623 write_csr(mmc, MIO_EMM_SAMPLE(), emm_sample.u);
2624
2625 return 0;
2626 }
2627
octeontx_mmc_io_drive_setup(struct mmc * mmc)2628 static void octeontx_mmc_io_drive_setup(struct mmc *mmc)
2629 {
2630 }
2631 #else
octeontx_mmc_set_timing(struct mmc * mmc)2632 static void octeontx_mmc_set_timing(struct mmc *mmc)
2633 {
2634 union mio_emm_timing timing;
2635 struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
2636
2637 switch (mmc->selected_mode) {
2638 case MMC_HS_200:
2639 timing = slot->hs200_taps;
2640 break;
2641 case MMC_HS_400:
2642 timing = slot->hs400_tuned ?
2643 slot->hs400_taps : slot->hs200_taps;
2644 break;
2645 default:
2646 timing = slot->taps;
2647 break;
2648 }
2649
2650 debug("%s(%s):\n cmd_in_tap: %u\n cmd_out_tap: %u\n data_in_tap: %u\n data_out_tap: %u\n",
2651 __func__, mmc->dev->name, timing.s.cmd_in_tap,
2652 timing.s.cmd_out_tap, timing.s.data_in_tap,
2653 timing.s.data_out_tap);
2654
2655 octeontx_mmc_set_emm_timing(mmc, timing);
2656 }
2657
octeontx_mmc_configure_delay(struct mmc * mmc)2658 static int octeontx_mmc_configure_delay(struct mmc *mmc)
2659 {
2660 struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
2661 struct octeontx_mmc_host *host __maybe_unused = slot->host;
2662 bool __maybe_unused is_hs200;
2663 bool __maybe_unused is_hs400;
2664
2665 debug("%s(%s)\n", __func__, mmc->dev->name);
2666
2667 if (IS_ENABLED(CONFIG_ARCH_OCTEON) ||
2668 IS_ENABLED(CONFIG_ARCH_OCTEONTX)) {
2669 union mio_emm_sample emm_sample;
2670
2671 emm_sample.u = 0;
2672 emm_sample.s.cmd_cnt = slot->cmd_cnt;
2673 emm_sample.s.dat_cnt = slot->dat_cnt;
2674 write_csr(mmc, MIO_EMM_SAMPLE(), emm_sample.u);
2675 } else {
2676 is_hs200 = (mmc->selected_mode == MMC_HS_200);
2677 is_hs400 = (mmc->selected_mode == MMC_HS_400);
2678
2679 if ((is_hs200 && slot->hs200_tuned) ||
2680 (is_hs400 && slot->hs400_tuned) ||
2681 (!is_hs200 && !is_hs400 && slot->tuned)) {
2682 octeontx_mmc_set_output_bus_timing(mmc);
2683 } else {
2684 int half = MAX_NO_OF_TAPS / 2;
2685 int dout, cout;
2686
2687 switch (mmc->selected_mode) {
2688 case MMC_LEGACY:
2689 if (IS_SD(mmc)) {
2690 cout = MMC_SD_LEGACY_DEFAULT_CMD_OUT_TAP;
2691 dout = MMC_SD_LEGACY_DEFAULT_DATA_OUT_TAP;
2692 } else {
2693 cout = MMC_LEGACY_DEFAULT_CMD_OUT_TAP;
2694 dout = MMC_LEGACY_DEFAULT_DATA_OUT_TAP;
2695 }
2696 break;
2697 case MMC_HS:
2698 cout = MMC_HS_CMD_OUT_TAP;
2699 dout = MMC_HS_DATA_OUT_TAP;
2700 break;
2701 case SD_HS:
2702 case UHS_SDR12:
2703 case UHS_SDR25:
2704 case UHS_SDR50:
2705 cout = MMC_SD_HS_CMD_OUT_TAP;
2706 dout = MMC_SD_HS_DATA_OUT_TAP;
2707 break;
2708 case UHS_SDR104:
2709 case UHS_DDR50:
2710 case MMC_HS_52:
2711 case MMC_DDR_52:
2712 cout = MMC_DEFAULT_CMD_OUT_TAP;
2713 dout = MMC_DEFAULT_DATA_OUT_TAP;
2714 break;
2715 case MMC_HS_200:
2716 cout = -1;
2717 dout = -1;
2718 if (host->timing_calibrated) {
2719 cout = octeontx2_mmc_calc_delay(
2720 mmc, slot->cmd_out_hs200_delay);
2721 dout = octeontx2_mmc_calc_delay(
2722 mmc,
2723 slot->data_out_hs200_delay);
2724 debug("%s(%s): Calibrated HS200/HS400 cmd out delay: %dps tap: %d, data out delay: %d, tap: %d\n",
2725 __func__, mmc->dev->name,
2726 slot->cmd_out_hs200_delay, cout,
2727 slot->data_out_hs200_delay, dout);
2728 } else {
2729 cout = MMC_DEFAULT_HS200_CMD_OUT_TAP;
2730 dout = MMC_DEFAULT_HS200_DATA_OUT_TAP;
2731 }
2732 is_hs200 = true;
2733 break;
2734 case MMC_HS_400:
2735 cout = -1;
2736 dout = -1;
2737 if (host->timing_calibrated) {
2738 if (slot->cmd_out_hs400_delay)
2739 cout = octeontx2_mmc_calc_delay(
2740 mmc,
2741 slot->cmd_out_hs400_delay);
2742 if (slot->data_out_hs400_delay)
2743 dout = octeontx2_mmc_calc_delay(
2744 mmc,
2745 slot->data_out_hs400_delay);
2746 debug("%s(%s): Calibrated HS200/HS400 cmd out delay: %dps tap: %d, data out delay: %d, tap: %d\n",
2747 __func__, mmc->dev->name,
2748 slot->cmd_out_hs400_delay, cout,
2749 slot->data_out_hs400_delay, dout);
2750 } else {
2751 cout = MMC_DEFAULT_HS400_CMD_OUT_TAP;
2752 dout = MMC_DEFAULT_HS400_DATA_OUT_TAP;
2753 }
2754 is_hs400 = true;
2755 break;
2756 default:
2757 pr_err("%s(%s): Invalid mode %d\n", __func__,
2758 mmc->dev->name, mmc->selected_mode);
2759 return -1;
2760 }
2761 debug("%s(%s): Not tuned, hs200: %d, hs200 tuned: %d, hs400: %d, hs400 tuned: %d, tuned: %d\n",
2762 __func__, mmc->dev->name, is_hs200,
2763 slot->hs200_tuned,
2764 is_hs400, slot->hs400_tuned, slot->tuned);
2765 /* Set some defaults */
2766 if (is_hs200) {
2767 slot->hs200_taps.u = 0;
2768 slot->hs200_taps.s.cmd_out_tap = cout;
2769 slot->hs200_taps.s.data_out_tap = dout;
2770 slot->hs200_taps.s.cmd_in_tap = half;
2771 slot->hs200_taps.s.data_in_tap = half;
2772 } else if (is_hs400) {
2773 slot->hs400_taps.u = 0;
2774 slot->hs400_taps.s.cmd_out_tap = cout;
2775 slot->hs400_taps.s.data_out_tap = dout;
2776 slot->hs400_taps.s.cmd_in_tap = half;
2777 slot->hs400_taps.s.data_in_tap = half;
2778 } else {
2779 slot->taps.u = 0;
2780 slot->taps.s.cmd_out_tap = cout;
2781 slot->taps.s.data_out_tap = dout;
2782 slot->taps.s.cmd_in_tap = half;
2783 slot->taps.s.data_in_tap = half;
2784 }
2785 }
2786
2787 if (is_hs200)
2788 debug("%s(%s): hs200 taps: ci: %u, co: %u, di: %u, do: %u\n",
2789 __func__, mmc->dev->name,
2790 slot->hs200_taps.s.cmd_in_tap,
2791 slot->hs200_taps.s.cmd_out_tap,
2792 slot->hs200_taps.s.data_in_tap,
2793 slot->hs200_taps.s.data_out_tap);
2794 else if (is_hs400)
2795 debug("%s(%s): hs400 taps: ci: %u, co: %u, di: %u, do: %u\n",
2796 __func__, mmc->dev->name,
2797 slot->hs400_taps.s.cmd_in_tap,
2798 slot->hs400_taps.s.cmd_out_tap,
2799 slot->hs400_taps.s.data_in_tap,
2800 slot->hs400_taps.s.data_out_tap);
2801 else
2802 debug("%s(%s): taps: ci: %u, co: %u, di: %u, do: %u\n",
2803 __func__, mmc->dev->name, slot->taps.s.cmd_in_tap,
2804 slot->taps.s.cmd_out_tap,
2805 slot->taps.s.data_in_tap,
2806 slot->taps.s.data_out_tap);
2807 octeontx_mmc_set_timing(mmc);
2808 debug("%s: Done\n", __func__);
2809 }
2810
2811 return 0;
2812 }
2813
2814 /**
2815 * Set the IO drive strength and slew
2816 *
2817 * @param mmc mmc device
2818 */
octeontx_mmc_io_drive_setup(struct mmc * mmc)2819 static void octeontx_mmc_io_drive_setup(struct mmc *mmc)
2820 {
2821 if (IS_ENABLED(CONFIG_ARCH_OCTEONTX2)) {
2822 struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
2823 union mio_emm_io_ctl io_ctl;
2824
2825 if (slot->drive < 0 || slot->slew < 0)
2826 return;
2827
2828 io_ctl.u = 0;
2829 io_ctl.s.drive = slot->drive;
2830 io_ctl.s.slew = slot->slew;
2831 write_csr(mmc, MIO_EMM_IO_CTL(), io_ctl.u);
2832 }
2833 }
2834 #endif
2835
2836 /**
2837 * Sets the MMC watchdog timer in microseconds
2838 *
2839 * @param mmc mmc device
2840 * @param us timeout in microseconds, 0 for maximum timeout
2841 */
set_wdog(struct mmc * mmc,u64 us)2842 static void set_wdog(struct mmc *mmc, u64 us)
2843 {
2844 union mio_emm_wdog wdog;
2845 u64 val;
2846
2847 val = (us * mmc->clock) / 1000000;
2848 if (val >= (1 << 26) || !us) {
2849 if (us)
2850 pr_debug("%s: warning: timeout %llu exceeds max value %llu, truncating\n",
2851 __func__, us,
2852 (u64)(((1ULL << 26) - 1) * 1000000ULL) /
2853 mmc->clock);
2854 val = (1 << 26) - 1;
2855 }
2856 wdog.u = 0;
2857 wdog.s.clk_cnt = val;
2858 write_csr(mmc, MIO_EMM_WDOG(), wdog.u);
2859 }
2860
2861 /**
2862 * Print switch errors
2863 *
2864 * @param mmc mmc device
2865 */
check_switch_errors(struct mmc * mmc)2866 static void check_switch_errors(struct mmc *mmc)
2867 {
2868 union mio_emm_switch emm_switch;
2869
2870 emm_switch.u = read_csr(mmc, MIO_EMM_SWITCH());
2871 if (emm_switch.s.switch_err0)
2872 pr_err("%s: Switch power class error\n", mmc->cfg->name);
2873 if (emm_switch.s.switch_err1)
2874 pr_err("%s: Switch HS timing error\n", mmc->cfg->name);
2875 if (emm_switch.s.switch_err2)
2876 pr_err("%s: Switch bus width error\n", mmc->cfg->name);
2877 }
2878
do_switch(struct mmc * mmc,union mio_emm_switch emm_switch)2879 static void do_switch(struct mmc *mmc, union mio_emm_switch emm_switch)
2880 {
2881 union mio_emm_rsp_sts rsp_sts;
2882 struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
2883 int bus_id = emm_switch.s.bus_id;
2884 ulong start;
2885
2886 if (emm_switch.s.bus_id != 0) {
2887 emm_switch.s.bus_id = 0;
2888 write_csr(mmc, MIO_EMM_SWITCH(), emm_switch.u);
2889 udelay(100);
2890 emm_switch.s.bus_id = bus_id;
2891 }
2892 debug("%s(%s, 0x%llx)\n", __func__, mmc->dev->name, emm_switch.u);
2893 write_csr(mmc, MIO_EMM_SWITCH(), emm_switch.u);
2894
2895 start = get_timer(0);
2896 do {
2897 rsp_sts.u = read_csr(mmc, MIO_EMM_RSP_STS());
2898 if (!rsp_sts.s.switch_val)
2899 break;
2900 udelay(100);
2901 } while (get_timer(start) < 10);
2902 if (rsp_sts.s.switch_val) {
2903 pr_warn("%s(%s): Warning: writing 0x%llx to emm_switch timed out, status: 0x%llx\n",
2904 __func__, mmc->dev->name, emm_switch.u, rsp_sts.u);
2905 }
2906 slot->cached_switch = emm_switch;
2907 check_switch_errors(mmc);
2908 slot->cached_switch.u = emm_switch.u;
2909 debug("%s: emm_switch: 0x%llx, rsp_lo: 0x%llx\n",
2910 __func__, read_csr(mmc, MIO_EMM_SWITCH()),
2911 read_csr(mmc, MIO_EMM_RSP_LO()));
2912 }
2913
2914 /**
2915 * Calibrates the delay based on the internal clock
2916 *
2917 * @param mmc Pointer to mmc data structure
2918 *
2919 * @return 0 for success or -ETIMEDOUT on error
2920 *
2921 * NOTE: On error a default value will be calculated.
2922 */
2923 #if defined(CONFIG_ARCH_OCTEON)
octeontx_mmc_set_input_bus_timing(struct mmc * mmc)2924 static int octeontx_mmc_set_input_bus_timing(struct mmc *mmc)
2925 {
2926 return 0;
2927 }
2928
octeontx_mmc_set_output_bus_timing(struct mmc * mmc)2929 static int octeontx_mmc_set_output_bus_timing(struct mmc *mmc)
2930 {
2931 return 0;
2932 }
2933
octeontx_mmc_calibrate_delay(struct mmc * mmc)2934 static int octeontx_mmc_calibrate_delay(struct mmc *mmc)
2935 {
2936 return 0;
2937 }
2938 #else
2939 /**
2940 * Given a delay in ps, return the tap delay count
2941 *
2942 * @param mmc mmc data structure
2943 * @param delay delay in picoseconds
2944 *
2945 * @return Number of tap cycles or error if -1
2946 */
octeontx2_mmc_calc_delay(struct mmc * mmc,int delay)2947 static int octeontx2_mmc_calc_delay(struct mmc *mmc, int delay)
2948 {
2949 struct octeontx_mmc_host *host = mmc_to_host(mmc);
2950
2951 if (host->is_asim || host->is_emul)
2952 return 63;
2953
2954 if (!host->timing_taps) {
2955 pr_err("%s(%s): Error: host timing not calibrated\n",
2956 __func__, mmc->dev->name);
2957 return -1;
2958 }
2959 debug("%s(%s, %d) timing taps: %llu\n", __func__, mmc->dev->name,
2960 delay, host->timing_taps);
2961 return min_t(int, DIV_ROUND_UP(delay, host->timing_taps), 63);
2962 }
2963
octeontx_mmc_calibrate_delay(struct mmc * mmc)2964 static int octeontx_mmc_calibrate_delay(struct mmc *mmc)
2965 {
2966 union mio_emm_calb emm_calb;
2967 union mio_emm_tap emm_tap;
2968 union mio_emm_cfg emm_cfg;
2969 union mio_emm_io_ctl emm_io_ctl;
2970 union mio_emm_switch emm_switch;
2971 union mio_emm_wdog emm_wdog;
2972 union mio_emm_sts_mask emm_sts_mask;
2973 union mio_emm_debug emm_debug;
2974 union mio_emm_timing emm_timing;
2975 struct octeontx_mmc_host *host = mmc_to_host(mmc);
2976 ulong start;
2977 u8 bus_id, bus_ena;
2978
2979 debug("%s: Calibrating delay\n", __func__);
2980 if (host->is_asim || host->is_emul) {
2981 debug(" No calibration for ASIM\n");
2982 return 0;
2983 }
2984 emm_tap.u = 0;
2985 if (host->calibrate_glitch) {
2986 emm_tap.s.delay = MMC_DEFAULT_TAP_DELAY;
2987 } else {
2988 /* Save registers */
2989 emm_cfg.u = read_csr(mmc, MIO_EMM_CFG());
2990 emm_io_ctl.u = read_csr(mmc, MIO_EMM_IO_CTL());
2991 emm_switch.u = read_csr(mmc, MIO_EMM_SWITCH());
2992 emm_wdog.u = read_csr(mmc, MIO_EMM_WDOG());
2993 emm_sts_mask.u = read_csr(mmc, MIO_EMM_STS_MASK());
2994 emm_debug.u = read_csr(mmc, MIO_EMM_DEBUG());
2995 emm_timing.u = read_csr(mmc, MIO_EMM_TIMING());
2996 bus_ena = emm_cfg.s.bus_ena;
2997 bus_id = emm_switch.s.bus_id;
2998 emm_cfg.s.bus_ena = 0;
2999 write_csr(mmc, MIO_EMM_CFG(), emm_cfg.u);
3000 udelay(1);
3001 emm_cfg.s.bus_ena = 1ULL << 3;
3002 write_csr(mmc, MIO_EMM_CFG(), emm_cfg.u);
3003 mdelay(1);
3004 emm_calb.u = 0;
3005 write_csr(mmc, MIO_EMM_CALB(), emm_calb.u);
3006 emm_calb.s.start = 1;
3007 write_csr(mmc, MIO_EMM_CALB(), emm_calb.u);
3008 start = get_timer(0);
3009 /* This should only take 3 microseconds */
3010 do {
3011 udelay(5);
3012 emm_tap.u = read_csr(mmc, MIO_EMM_TAP());
3013 } while (!emm_tap.s.delay && get_timer(start) < 10);
3014
3015 emm_calb.s.start = 0;
3016 write_csr(mmc, MIO_EMM_CALB(), emm_calb.u);
3017
3018 emm_cfg.s.bus_ena = 0;
3019 write_csr(mmc, MIO_EMM_CFG(), emm_cfg.u);
3020 udelay(1);
3021 /* Restore registers */
3022 emm_cfg.s.bus_ena = bus_ena;
3023 write_csr(mmc, MIO_EMM_CFG(), emm_cfg.u);
3024 if (host->tap_requires_noclk) {
3025 /* Turn off the clock */
3026 emm_debug.u = read_csr(mmc, MIO_EMM_DEBUG());
3027 emm_debug.s.emmc_clk_disable = 1;
3028 write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
3029 udelay(1);
3030 emm_debug.s.rdsync_rst = 1;
3031 write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
3032 udelay(1);
3033 }
3034
3035 write_csr(mmc, MIO_EMM_TIMING(), emm_timing.u);
3036 if (host->tap_requires_noclk) {
3037 /* Turn the clock back on */
3038 udelay(1);
3039 emm_debug.s.rdsync_rst = 0;
3040 write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
3041 udelay(1);
3042 emm_debug.s.emmc_clk_disable = 0;
3043 write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
3044 }
3045 udelay(1);
3046 write_csr(mmc, MIO_EMM_IO_CTL(), emm_io_ctl.u);
3047 bus_id = emm_switch.s.bus_id;
3048 emm_switch.s.bus_id = 0;
3049 write_csr(mmc, MIO_EMM_SWITCH(), emm_switch.u);
3050 emm_switch.s.bus_id = bus_id;
3051 write_csr(mmc, MIO_EMM_SWITCH(), emm_switch.u);
3052 write_csr(mmc, MIO_EMM_WDOG(), emm_wdog.u);
3053 write_csr(mmc, MIO_EMM_STS_MASK(), emm_sts_mask.u);
3054 write_csr(mmc, MIO_EMM_RCA(), mmc->rca);
3055 write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
3056
3057 if (!emm_tap.s.delay) {
3058 pr_err("%s: Error: delay calibration failed, timed out.\n",
3059 __func__);
3060 /* Set to default value if timed out */
3061 emm_tap.s.delay = MMC_DEFAULT_TAP_DELAY;
3062 return -ETIMEDOUT;
3063 }
3064 }
3065 /* Round up */
3066 host->timing_taps = (10 * 1000 * emm_tap.s.delay) / TOTAL_NO_OF_TAPS;
3067 debug("%s(%s): timing taps: %llu, delay: %u\n",
3068 __func__, mmc->dev->name, host->timing_taps, emm_tap.s.delay);
3069 host->timing_calibrated = true;
3070 return 0;
3071 }
3072
octeontx_mmc_set_input_bus_timing(struct mmc * mmc)3073 static int octeontx_mmc_set_input_bus_timing(struct mmc *mmc)
3074 {
3075 struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
3076
3077 if (IS_ENABLED(CONFIG_ARCH_OCTEONTX)) {
3078 union mio_emm_sample sample;
3079
3080 sample.u = 0;
3081 sample.s.cmd_cnt = slot->cmd_clk_skew;
3082 sample.s.dat_cnt = slot->dat_clk_skew;
3083 write_csr(mmc, MIO_EMM_SAMPLE(), sample.u);
3084 } else {
3085 union mio_emm_timing timing;
3086
3087 timing.u = read_csr(mmc, MIO_EMM_TIMING());
3088 if (mmc->selected_mode == MMC_HS_200) {
3089 if (slot->hs200_tuned) {
3090 timing.s.cmd_in_tap =
3091 slot->hs200_taps.s.cmd_in_tap;
3092 timing.s.data_in_tap =
3093 slot->hs200_taps.s.data_in_tap;
3094 } else {
3095 pr_warn("%s(%s): Warning: hs200 timing not tuned\n",
3096 __func__, mmc->dev->name);
3097 timing.s.cmd_in_tap =
3098 MMC_DEFAULT_HS200_CMD_IN_TAP;
3099 timing.s.data_in_tap =
3100 MMC_DEFAULT_HS200_DATA_IN_TAP;
3101 }
3102 } else if (mmc->selected_mode == MMC_HS_400) {
3103 if (slot->hs400_tuned) {
3104 timing.s.cmd_in_tap =
3105 slot->hs400_taps.s.cmd_in_tap;
3106 timing.s.data_in_tap =
3107 slot->hs400_taps.s.data_in_tap;
3108 } else if (slot->hs200_tuned) {
3109 timing.s.cmd_in_tap =
3110 slot->hs200_taps.s.cmd_in_tap;
3111 timing.s.data_in_tap =
3112 slot->hs200_taps.s.data_in_tap;
3113 } else {
3114 pr_warn("%s(%s): Warning: hs400 timing not tuned\n",
3115 __func__, mmc->dev->name);
3116 timing.s.cmd_in_tap =
3117 MMC_DEFAULT_HS200_CMD_IN_TAP;
3118 timing.s.data_in_tap =
3119 MMC_DEFAULT_HS200_DATA_IN_TAP;
3120 }
3121 } else if (slot->tuned) {
3122 timing.s.cmd_in_tap = slot->taps.s.cmd_in_tap;
3123 timing.s.data_in_tap = slot->taps.s.data_in_tap;
3124 } else {
3125 timing.s.cmd_in_tap = MMC_DEFAULT_CMD_IN_TAP;
3126 timing.s.data_in_tap = MMC_DEFAULT_DATA_IN_TAP;
3127 }
3128 octeontx_mmc_set_emm_timing(mmc, timing);
3129 }
3130
3131 return 0;
3132 }
3133
3134 /**
3135 * Sets the default bus timing for the current mode.
3136 *
3137 * @param mmc mmc data structure
3138 *
3139 * @return 0 for success, error otherwise
3140 */
octeontx_mmc_set_output_bus_timing(struct mmc * mmc)3141 static int octeontx_mmc_set_output_bus_timing(struct mmc *mmc)
3142 {
3143 struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
3144 union mio_emm_timing timing;
3145 int cout_bdelay, dout_bdelay;
3146 unsigned int cout_delay, dout_delay;
3147 char env_name[32];
3148
3149 if (IS_ENABLED(CONFIG_ARCH_OCTEONTX))
3150 return 0;
3151
3152 debug("%s(%s)\n", __func__, mmc->dev->name);
3153 if (slot->is_asim || slot->is_emul)
3154 return 0;
3155
3156 octeontx_mmc_calibrate_delay(mmc);
3157
3158 if (mmc->clock < 26000000) {
3159 cout_delay = 5000;
3160 dout_delay = 5000;
3161 } else if (mmc->clock <= 52000000) {
3162 cout_delay = 2500;
3163 dout_delay = 2500;
3164 } else if (!mmc_is_mode_ddr(mmc->selected_mode)) {
3165 cout_delay = slot->cmd_out_hs200_delay;
3166 dout_delay = slot->data_out_hs200_delay;
3167 } else {
3168 cout_delay = slot->cmd_out_hs400_delay;
3169 dout_delay = slot->data_out_hs400_delay;
3170 }
3171
3172 snprintf(env_name, sizeof(env_name), "mmc%d_hs200_dout_delay_ps",
3173 slot->bus_id);
3174 dout_delay = env_get_ulong(env_name, 10, dout_delay);
3175 debug("%s: dout_delay: %u\n", __func__, dout_delay);
3176
3177 cout_bdelay = octeontx2_mmc_calc_delay(mmc, cout_delay);
3178 dout_bdelay = octeontx2_mmc_calc_delay(mmc, dout_delay);
3179
3180 debug("%s: cmd output delay: %u, data output delay: %u, cmd bdelay: %d, data bdelay: %d, clock: %d\n",
3181 __func__, cout_delay, dout_delay, cout_bdelay, dout_bdelay,
3182 mmc->clock);
3183 if (cout_bdelay < 0 || dout_bdelay < 0) {
3184 pr_err("%s: Error: could not calculate command and/or data clock skew\n",
3185 __func__);
3186 return -1;
3187 }
3188 timing.u = read_csr(mmc, MIO_EMM_TIMING());
3189 timing.s.cmd_out_tap = cout_bdelay;
3190 timing.s.data_out_tap = dout_bdelay;
3191 if (mmc->selected_mode == MMC_HS_200) {
3192 slot->hs200_taps.s.cmd_out_tap = cout_bdelay;
3193 slot->hs200_taps.s.data_out_tap = dout_bdelay;
3194 } else if (mmc->selected_mode == MMC_HS_400) {
3195 slot->hs400_taps.s.cmd_out_tap = cout_bdelay;
3196 slot->hs400_taps.s.data_out_tap = dout_bdelay;
3197 } else {
3198 slot->taps.s.cmd_out_tap = cout_bdelay;
3199 slot->taps.s.data_out_tap = dout_bdelay;
3200 }
3201 octeontx_mmc_set_emm_timing(mmc, timing);
3202 debug("%s(%s): bdelay: %d/%d, clock: %d, ddr: %s, timing taps: %llu, do: %d, di: %d, co: %d, ci: %d\n",
3203 __func__, mmc->dev->name, cout_bdelay, dout_bdelay, mmc->clock,
3204 mmc->ddr_mode ? "yes" : "no",
3205 mmc_to_host(mmc)->timing_taps,
3206 timing.s.data_out_tap,
3207 timing.s.data_in_tap,
3208 timing.s.cmd_out_tap,
3209 timing.s.cmd_in_tap);
3210
3211 return 0;
3212 }
3213 #endif
3214
octeontx_mmc_set_clock(struct mmc * mmc)3215 static void octeontx_mmc_set_clock(struct mmc *mmc)
3216 {
3217 struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
3218 uint clock;
3219
3220 clock = min(mmc->cfg->f_max, (uint)slot->clock);
3221 clock = max(mmc->cfg->f_min, clock);
3222 debug("%s(%s): f_min: %u, f_max: %u, clock: %u\n", __func__,
3223 mmc->dev->name, mmc->cfg->f_min, mmc->cfg->f_max, clock);
3224 slot->clock = clock;
3225 mmc->clock = clock;
3226 }
3227
3228 /**
3229 * This switches I/O power as needed when switching between slots.
3230 *
3231 * @param mmc mmc data structure
3232 */
octeontx_mmc_switch_io(struct mmc * mmc)3233 static void octeontx_mmc_switch_io(struct mmc *mmc)
3234 {
3235 struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
3236 struct octeontx_mmc_host *host = slot->host;
3237 struct mmc *last_mmc = host->last_mmc;
3238 static struct udevice *last_reg;
3239 union mio_emm_cfg emm_cfg;
3240 int bus;
3241 static bool initialized;
3242
3243 /* First time? */
3244 if (!initialized || mmc != host->last_mmc) {
3245 struct mmc *ommc;
3246
3247 /* Switch to bus 3 which is unused */
3248 emm_cfg.u = read_csr(mmc, MIO_EMM_CFG());
3249 emm_cfg.s.bus_ena = 1 << 3;
3250 write_csr(mmc, MIO_EMM_CFG(), emm_cfg.u);
3251
3252 /* Turn off all other I/O interfaces with first initialization
3253 * if at least one supply was found.
3254 */
3255 for (bus = 0; bus <= OCTEONTX_MAX_MMC_SLOT; bus++) {
3256 ommc = &host->slots[bus].mmc;
3257
3258 /* Handle self case later */
3259 if (ommc == mmc || !ommc->vqmmc_supply)
3260 continue;
3261
3262 /* Skip if we're not switching regulators */
3263 if (last_reg == mmc->vqmmc_supply)
3264 continue;
3265
3266 /* Turn off other regulators */
3267 if (ommc->vqmmc_supply != mmc->vqmmc_supply)
3268 regulator_set_enable(ommc->vqmmc_supply, false);
3269 }
3270 /* Turn ourself on */
3271 if (mmc->vqmmc_supply && last_reg != mmc->vqmmc_supply)
3272 regulator_set_enable(mmc->vqmmc_supply, true);
3273 mdelay(1); /* Settle time */
3274 /* Switch to new bus */
3275 emm_cfg.s.bus_ena = 1 << slot->bus_id;
3276 write_csr(mmc, MIO_EMM_CFG(), emm_cfg.u);
3277 last_reg = mmc->vqmmc_supply;
3278 initialized = true;
3279 return;
3280 }
3281
3282 /* No change in device */
3283 if (last_mmc == mmc)
3284 return;
3285
3286 if (!last_mmc) {
3287 pr_warn("%s(%s): No previous slot detected in IO slot switch!\n",
3288 __func__, mmc->dev->name);
3289 return;
3290 }
3291
3292 debug("%s(%s): last: %s, supply: %p\n", __func__, mmc->dev->name,
3293 last_mmc->dev->name, mmc->vqmmc_supply);
3294
3295 /* The supply is the same so we do nothing */
3296 if (last_mmc->vqmmc_supply == mmc->vqmmc_supply)
3297 return;
3298
3299 /* Turn off the old slot I/O supply */
3300 if (last_mmc->vqmmc_supply) {
3301 debug("%s(%s): Turning off IO to %s, supply: %s\n",
3302 __func__, mmc->dev->name, last_mmc->dev->name,
3303 last_mmc->vqmmc_supply->name);
3304 regulator_set_enable(last_mmc->vqmmc_supply, false);
3305 }
3306 /* Turn on the new slot I/O supply */
3307 if (mmc->vqmmc_supply) {
3308 debug("%s(%s): Turning on IO to slot %d, supply: %s\n",
3309 __func__, mmc->dev->name, slot->bus_id,
3310 mmc->vqmmc_supply->name);
3311 regulator_set_enable(mmc->vqmmc_supply, true);
3312 }
3313 /* Allow power to settle */
3314 mdelay(1);
3315 }
3316
3317 /**
3318 * Called to switch between mmc devices
3319 *
3320 * @param mmc new mmc device
3321 */
octeontx_mmc_switch_to(struct mmc * mmc)3322 static void octeontx_mmc_switch_to(struct mmc *mmc)
3323 {
3324 struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
3325 struct octeontx_mmc_slot *old_slot;
3326 struct octeontx_mmc_host *host = slot->host;
3327 union mio_emm_switch emm_switch;
3328 union mio_emm_sts_mask emm_sts_mask;
3329 union mio_emm_rca emm_rca;
3330
3331 if (slot->bus_id == host->last_slotid)
3332 return;
3333
3334 debug("%s(%s) switching from slot %d to slot %d\n", __func__,
3335 mmc->dev->name, host->last_slotid, slot->bus_id);
3336 octeontx_mmc_switch_io(mmc);
3337
3338 if (host->last_slotid >= 0 && slot->valid) {
3339 old_slot = &host->slots[host->last_slotid];
3340 old_slot->cached_switch.u = read_csr(mmc, MIO_EMM_SWITCH());
3341 old_slot->cached_rca.u = read_csr(mmc, MIO_EMM_RCA());
3342 }
3343 if (mmc->rca)
3344 write_csr(mmc, MIO_EMM_RCA(), mmc->rca);
3345 emm_switch = slot->cached_switch;
3346 do_switch(mmc, emm_switch);
3347 emm_rca.u = 0;
3348 emm_rca.s.card_rca = mmc->rca;
3349 write_csr(mmc, MIO_EMM_RCA(), emm_rca.u);
3350 mdelay(100);
3351
3352 set_wdog(mmc, 100000);
3353 if (octeontx_mmc_set_output_bus_timing(mmc) ||
3354 octeontx_mmc_set_input_bus_timing(mmc))
3355 pr_err("%s(%s): Error setting bus timing\n", __func__,
3356 mmc->dev->name);
3357 octeontx_mmc_io_drive_setup(mmc);
3358
3359 emm_sts_mask.u = 0;
3360 emm_sts_mask.s.sts_msk = 1 << 7 | 1 << 22 | 1 << 23 | 1 << 19;
3361 write_csr(mmc, MIO_EMM_STS_MASK(), emm_sts_mask.u);
3362 host->last_slotid = slot->bus_id;
3363 host->last_mmc = mmc;
3364 mdelay(10);
3365 }
3366
3367 /**
3368 * Perform initial timing configuration
3369 *
3370 * @param mmc mmc device
3371 *
3372 * @return 0 for success
3373 *
3374 * NOTE: This will need to be updated when new silicon comes out
3375 */
octeontx_mmc_init_timing(struct mmc * mmc)3376 static int octeontx_mmc_init_timing(struct mmc *mmc)
3377 {
3378 union mio_emm_timing timing;
3379
3380 if (mmc_to_slot(mmc)->is_asim || mmc_to_slot(mmc)->is_emul)
3381 return 0;
3382
3383 debug("%s(%s)\n", __func__, mmc->dev->name);
3384 timing.u = 0;
3385 timing.s.cmd_out_tap = MMC_DEFAULT_CMD_OUT_TAP;
3386 timing.s.data_out_tap = MMC_DEFAULT_DATA_OUT_TAP;
3387 timing.s.cmd_in_tap = MMC_DEFAULT_CMD_IN_TAP;
3388 timing.s.data_in_tap = MMC_DEFAULT_DATA_IN_TAP;
3389 octeontx_mmc_set_emm_timing(mmc, timing);
3390 return 0;
3391 }
3392
3393 /**
3394 * Perform low-level initialization
3395 *
3396 * @param mmc mmc device
3397 *
3398 * @return 0 for success, error otherwise
3399 */
octeontx_mmc_init_lowlevel(struct mmc * mmc)3400 static int octeontx_mmc_init_lowlevel(struct mmc *mmc)
3401 {
3402 struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
3403 struct octeontx_mmc_host *host = slot->host;
3404 union mio_emm_switch emm_switch;
3405 u32 clk_period;
3406
3407 debug("%s(%s): lowlevel init for slot %d\n", __func__,
3408 mmc->dev->name, slot->bus_id);
3409 host->emm_cfg.s.bus_ena &= ~(1 << slot->bus_id);
3410 write_csr(mmc, MIO_EMM_CFG(), host->emm_cfg.u);
3411 udelay(100);
3412 host->emm_cfg.s.bus_ena |= 1 << slot->bus_id;
3413 write_csr(mmc, MIO_EMM_CFG(), host->emm_cfg.u);
3414 udelay(10);
3415 slot->clock = mmc->cfg->f_min;
3416 octeontx_mmc_set_clock(&slot->mmc);
3417
3418 if (IS_ENABLED(CONFIG_ARCH_OCTEONTX2)) {
3419 if (host->cond_clock_glitch) {
3420 union mio_emm_debug emm_debug;
3421
3422 emm_debug.u = read_csr(mmc, MIO_EMM_DEBUG());
3423 emm_debug.s.clk_on = 1;
3424 write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
3425 }
3426 octeontx_mmc_calibrate_delay(&slot->mmc);
3427 }
3428
3429 clk_period = octeontx_mmc_calc_clk_period(mmc);
3430 emm_switch.u = 0;
3431 emm_switch.s.power_class = 10;
3432 emm_switch.s.clk_lo = clk_period / 2;
3433 emm_switch.s.clk_hi = clk_period / 2;
3434
3435 emm_switch.s.bus_id = slot->bus_id;
3436 debug("%s: Performing switch\n", __func__);
3437 do_switch(mmc, emm_switch);
3438 slot->cached_switch.u = emm_switch.u;
3439
3440 if (!IS_ENABLED(CONFIG_ARCH_OCTEONTX))
3441 octeontx_mmc_init_timing(mmc);
3442
3443 set_wdog(mmc, 1000000); /* Set to 1 second */
3444 write_csr(mmc, MIO_EMM_STS_MASK(), 0xe4390080ull);
3445 write_csr(mmc, MIO_EMM_RCA(), 1);
3446 mdelay(10);
3447 debug("%s: done\n", __func__);
3448 return 0;
3449 }
3450
3451 /**
3452 * Translates a voltage number to bits in MMC register
3453 *
3454 * @param voltage voltage in microvolts
3455 *
3456 * @return MMC register value for voltage
3457 */
xlate_voltage(u32 voltage)3458 static u32 xlate_voltage(u32 voltage)
3459 {
3460 u32 volt = 0;
3461
3462 /* Convert to millivolts. Only necessary on ARM Octeon TX/TX2 */
3463 if (!IS_ENABLED(CONFIG_ARCH_OCTEON))
3464 voltage /= 1000;
3465
3466 if (voltage >= 1650 && voltage <= 1950)
3467 volt |= MMC_VDD_165_195;
3468 if (voltage >= 2000 && voltage <= 2100)
3469 volt |= MMC_VDD_20_21;
3470 if (voltage >= 2100 && voltage <= 2200)
3471 volt |= MMC_VDD_21_22;
3472 if (voltage >= 2200 && voltage <= 2300)
3473 volt |= MMC_VDD_22_23;
3474 if (voltage >= 2300 && voltage <= 2400)
3475 volt |= MMC_VDD_23_24;
3476 if (voltage >= 2400 && voltage <= 2500)
3477 volt |= MMC_VDD_24_25;
3478 if (voltage >= 2500 && voltage <= 2600)
3479 volt |= MMC_VDD_25_26;
3480 if (voltage >= 2600 && voltage <= 2700)
3481 volt |= MMC_VDD_26_27;
3482 if (voltage >= 2700 && voltage <= 2800)
3483 volt |= MMC_VDD_27_28;
3484 if (voltage >= 2800 && voltage <= 2900)
3485 volt |= MMC_VDD_28_29;
3486 if (voltage >= 2900 && voltage <= 3000)
3487 volt |= MMC_VDD_29_30;
3488 if (voltage >= 3000 && voltage <= 3100)
3489 volt |= MMC_VDD_30_31;
3490 if (voltage >= 3100 && voltage <= 3200)
3491 volt |= MMC_VDD_31_32;
3492 if (voltage >= 3200 && voltage <= 3300)
3493 volt |= MMC_VDD_32_33;
3494 if (voltage >= 3300 && voltage <= 3400)
3495 volt |= MMC_VDD_33_34;
3496 if (voltage >= 3400 && voltage <= 3500)
3497 volt |= MMC_VDD_34_35;
3498 if (voltage >= 3500 && voltage <= 3600)
3499 volt |= MMC_VDD_35_36;
3500
3501 return volt;
3502 }
3503
3504 /**
3505 * Check if a slot is valid in the device tree
3506 *
3507 * @param dev slot device to check
3508 *
3509 * @return true if status reports "ok" or "okay" or if no status,
3510 * false otherwise.
3511 */
octeontx_mmc_get_valid(struct udevice * dev)3512 static bool octeontx_mmc_get_valid(struct udevice *dev)
3513 {
3514 const char *stat = ofnode_read_string(dev_ofnode(dev), "status");
3515
3516 if (!stat || !strncmp(stat, "ok", 2))
3517 return true;
3518 else
3519 return false;
3520 }
3521
3522 /**
3523 * Reads slot configuration from the device tree
3524 *
3525 * @param dev slot device
3526 *
3527 * @return 0 on success, otherwise error
3528 */
octeontx_mmc_get_config(struct udevice * dev)3529 static int octeontx_mmc_get_config(struct udevice *dev)
3530 {
3531 struct octeontx_mmc_slot *slot = dev_to_mmc_slot(dev);
3532 uint voltages[2];
3533 uint low, high;
3534 char env_name[32];
3535 int err;
3536 ofnode node = dev_ofnode(dev);
3537 int bus_width = 1;
3538 ulong new_max_freq;
3539
3540 debug("%s(%s)", __func__, dev->name);
3541 slot->cfg.name = dev->name;
3542
3543 slot->cfg.f_max = ofnode_read_s32_default(dev_ofnode(dev),
3544 "max-frequency",
3545 26000000);
3546 snprintf(env_name, sizeof(env_name), "mmc_max_frequency%d",
3547 slot->bus_id);
3548
3549 new_max_freq = env_get_ulong(env_name, 10, slot->cfg.f_max);
3550 debug("Reading %s, got %lu\n", env_name, new_max_freq);
3551
3552 if (new_max_freq != slot->cfg.f_max) {
3553 printf("Overriding device tree MMC maximum frequency %u to %lu\n",
3554 slot->cfg.f_max, new_max_freq);
3555 slot->cfg.f_max = new_max_freq;
3556 }
3557 slot->cfg.f_min = 400000;
3558 slot->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
3559
3560 if (IS_ENABLED(CONFIG_ARCH_OCTEONTX2)) {
3561 slot->hs400_tuning_block =
3562 ofnode_read_s32_default(dev_ofnode(dev),
3563 "marvell,hs400-tuning-block",
3564 -1);
3565 debug("%s(%s): mmc HS400 tuning block: %d\n", __func__,
3566 dev->name, slot->hs400_tuning_block);
3567
3568 slot->hs200_tap_adj =
3569 ofnode_read_s32_default(dev_ofnode(dev),
3570 "marvell,hs200-tap-adjust", 0);
3571 debug("%s(%s): hs200-tap-adjust: %d\n", __func__, dev->name,
3572 slot->hs200_tap_adj);
3573 slot->hs400_tap_adj =
3574 ofnode_read_s32_default(dev_ofnode(dev),
3575 "marvell,hs400-tap-adjust", 0);
3576 debug("%s(%s): hs400-tap-adjust: %d\n", __func__, dev->name,
3577 slot->hs400_tap_adj);
3578 }
3579
3580 err = ofnode_read_u32_array(dev_ofnode(dev), "voltage-ranges",
3581 voltages, 2);
3582 if (err) {
3583 slot->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
3584 } else {
3585 low = xlate_voltage(voltages[0]);
3586 high = xlate_voltage(voltages[1]);
3587 debug(" low voltage: 0x%x (%u), high: 0x%x (%u)\n",
3588 low, voltages[0], high, voltages[1]);
3589 if (low > high || !low || !high) {
3590 pr_err("Invalid MMC voltage range [%u-%u] specified for %s\n",
3591 low, high, dev->name);
3592 return -1;
3593 }
3594 slot->cfg.voltages = 0;
3595 do {
3596 slot->cfg.voltages |= low;
3597 low <<= 1;
3598 } while (low <= high);
3599 }
3600 debug("%s: config voltages: 0x%x\n", __func__, slot->cfg.voltages);
3601 slot->slew = ofnode_read_s32_default(node, "cavium,clk-slew", -1);
3602 slot->drive = ofnode_read_s32_default(node, "cavium,drv-strength", -1);
3603 gpio_request_by_name(dev, "cd-gpios", 0, &slot->cd_gpio, GPIOD_IS_IN);
3604 slot->cd_inverted = ofnode_read_bool(node, "cd-inverted");
3605 gpio_request_by_name(dev, "wp-gpios", 0, &slot->wp_gpio, GPIOD_IS_IN);
3606 slot->wp_inverted = ofnode_read_bool(node, "wp-inverted");
3607 if (slot->cfg.voltages & MMC_VDD_165_195) {
3608 slot->is_1_8v = true;
3609 slot->is_3_3v = false;
3610 } else if (slot->cfg.voltages & (MMC_VDD_30_31 | MMC_VDD_31_32 |
3611 MMC_VDD_33_34 | MMC_VDD_34_35 |
3612 MMC_VDD_35_36)) {
3613 slot->is_1_8v = false;
3614 slot->is_3_3v = true;
3615 }
3616
3617 bus_width = ofnode_read_u32_default(node, "bus-width", 1);
3618 /* Note fall-through */
3619 switch (bus_width) {
3620 case 8:
3621 slot->cfg.host_caps |= MMC_MODE_8BIT;
3622 case 4:
3623 slot->cfg.host_caps |= MMC_MODE_4BIT;
3624 case 1:
3625 slot->cfg.host_caps |= MMC_MODE_1BIT;
3626 break;
3627 }
3628 if (ofnode_read_bool(node, "no-1-8-v")) {
3629 slot->is_3_3v = true;
3630 slot->is_1_8v = false;
3631 if (!(slot->cfg.voltages & (MMC_VDD_32_33 | MMC_VDD_33_34)))
3632 pr_warn("%s(%s): voltages indicate 3.3v but 3.3v not supported\n",
3633 __func__, dev->name);
3634 }
3635 if (ofnode_read_bool(node, "mmc-ddr-3-3v")) {
3636 slot->is_3_3v = true;
3637 slot->is_1_8v = false;
3638 if (!(slot->cfg.voltages & (MMC_VDD_32_33 | MMC_VDD_33_34)))
3639 pr_warn("%s(%s): voltages indicate 3.3v but 3.3v not supported\n",
3640 __func__, dev->name);
3641 }
3642 if (ofnode_read_bool(node, "cap-sd-highspeed") ||
3643 ofnode_read_bool(node, "cap-mmc-highspeed") ||
3644 ofnode_read_bool(node, "sd-uhs-sdr25"))
3645 slot->cfg.host_caps |= MMC_MODE_HS;
3646 if (slot->cfg.f_max >= 50000000 &&
3647 slot->cfg.host_caps & MMC_MODE_HS)
3648 slot->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
3649 if (ofnode_read_bool(node, "sd-uhs-sdr50"))
3650 slot->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
3651 if (ofnode_read_bool(node, "sd-uhs-ddr50"))
3652 slot->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz |
3653 MMC_MODE_DDR_52MHz;
3654
3655 if (IS_ENABLED(CONFIG_ARCH_OCTEONTX2)) {
3656 if (!slot->is_asim && !slot->is_emul) {
3657 if (ofnode_read_bool(node, "mmc-hs200-1_8v"))
3658 slot->cfg.host_caps |= MMC_MODE_HS200 |
3659 MMC_MODE_HS_52MHz;
3660 if (ofnode_read_bool(node, "mmc-hs400-1_8v"))
3661 slot->cfg.host_caps |= MMC_MODE_HS400 |
3662 MMC_MODE_HS_52MHz |
3663 MMC_MODE_HS200 |
3664 MMC_MODE_DDR_52MHz;
3665 slot->cmd_out_hs200_delay =
3666 ofnode_read_u32_default(node,
3667 "marvell,cmd-out-hs200-dly",
3668 MMC_DEFAULT_HS200_CMD_OUT_DLY);
3669 debug("%s(%s): HS200 cmd out delay: %d\n",
3670 __func__, dev->name, slot->cmd_out_hs200_delay);
3671 slot->data_out_hs200_delay =
3672 ofnode_read_u32_default(node,
3673 "marvell,data-out-hs200-dly",
3674 MMC_DEFAULT_HS200_DATA_OUT_DLY);
3675 debug("%s(%s): HS200 data out delay: %d\n",
3676 __func__, dev->name, slot->data_out_hs200_delay);
3677 slot->cmd_out_hs400_delay =
3678 ofnode_read_u32_default(node,
3679 "marvell,cmd-out-hs400-dly",
3680 MMC_DEFAULT_HS400_CMD_OUT_DLY);
3681 debug("%s(%s): HS400 cmd out delay: %d\n",
3682 __func__, dev->name, slot->cmd_out_hs400_delay);
3683 slot->data_out_hs400_delay =
3684 ofnode_read_u32_default(node,
3685 "marvell,data-out-hs400-dly",
3686 MMC_DEFAULT_HS400_DATA_OUT_DLY);
3687 debug("%s(%s): HS400 data out delay: %d\n",
3688 __func__, dev->name, slot->data_out_hs400_delay);
3689 }
3690 }
3691
3692 slot->disable_ddr = ofnode_read_bool(node, "marvell,disable-ddr");
3693 slot->non_removable = ofnode_read_bool(node, "non-removable");
3694 slot->cmd_clk_skew = ofnode_read_u32_default(node,
3695 "cavium,cmd-clk-skew", 0);
3696 slot->dat_clk_skew = ofnode_read_u32_default(node,
3697 "cavium,dat-clk-skew", 0);
3698 debug("%s(%s): host caps: 0x%x\n", __func__,
3699 dev->name, slot->cfg.host_caps);
3700 return 0;
3701 }
3702
3703 /**
3704 * Probes a MMC slot
3705 *
3706 * @param dev mmc device
3707 *
3708 * @return 0 for success, error otherwise
3709 */
octeontx_mmc_slot_probe(struct udevice * dev)3710 static int octeontx_mmc_slot_probe(struct udevice *dev)
3711 {
3712 struct octeontx_mmc_slot *slot;
3713 struct mmc *mmc;
3714 int err;
3715
3716 debug("%s(%s)\n", __func__, dev->name);
3717 if (!host_probed) {
3718 pr_err("%s(%s): Error: host not probed yet\n",
3719 __func__, dev->name);
3720 }
3721 slot = dev_to_mmc_slot(dev);
3722 mmc = &slot->mmc;
3723 mmc->dev = dev;
3724
3725 slot->valid = false;
3726 if (!octeontx_mmc_get_valid(dev)) {
3727 debug("%s(%s): slot is invalid\n", __func__, dev->name);
3728 return -ENODEV;
3729 }
3730
3731 debug("%s(%s): Getting config\n", __func__, dev->name);
3732 err = octeontx_mmc_get_config(dev);
3733 if (err) {
3734 pr_err("probe(%s): Error getting config\n", dev->name);
3735 return err;
3736 }
3737
3738 debug("%s(%s): mmc bind, mmc: %p\n", __func__, dev->name, &slot->mmc);
3739 err = mmc_bind(dev, &slot->mmc, &slot->cfg);
3740 if (err) {
3741 pr_err("%s(%s): Error binding mmc\n", __func__, dev->name);
3742 return -1;
3743 }
3744
3745 /* For some reason, mmc_bind always assigns priv to the device */
3746 slot->mmc.priv = slot;
3747
3748 debug("%s(%s): lowlevel init\n", __func__, dev->name);
3749 err = octeontx_mmc_init_lowlevel(mmc);
3750 if (err) {
3751 pr_err("probe(%s): Low-level init failed\n", dev->name);
3752 return err;
3753 }
3754
3755 slot->valid = true;
3756
3757 debug("%s(%s):\n"
3758 " base address : %p\n"
3759 " bus id : %d\n", __func__, dev->name,
3760 slot->base_addr, slot->bus_id);
3761
3762 return err;
3763 }
3764
3765 /**
3766 * MMC slot driver operations
3767 */
3768 static const struct dm_mmc_ops octeontx_hsmmc_ops = {
3769 .send_cmd = octeontx_mmc_dev_send_cmd,
3770 .set_ios = octeontx_mmc_set_ios,
3771 .get_cd = octeontx_mmc_get_cd,
3772 .get_wp = octeontx_mmc_get_wp,
3773 #ifdef MMC_SUPPORTS_TUNING
3774 .execute_tuning = octeontx_mmc_execute_tuning,
3775 #endif
3776 };
3777
3778 static const struct udevice_id octeontx_hsmmc_ids[] = {
3779 { .compatible = "mmc-slot" },
3780 { }
3781 };
3782
3783 U_BOOT_DRIVER(octeontx_hsmmc_slot) = {
3784 .name = "octeontx_hsmmc_slot",
3785 .id = UCLASS_MMC,
3786 .of_match = of_match_ptr(octeontx_hsmmc_ids),
3787 .probe = octeontx_mmc_slot_probe,
3788 .ops = &octeontx_hsmmc_ops,
3789 };
3790
3791 /*****************************************************************
3792 * PCI host driver
3793 *
3794 * The PCI host driver contains the resources used by all of the
3795 * slot drivers.
3796 *
3797 * The slot drivers are pseudo drivers.
3798 */
3799
3800 /**
3801 * Probe the MMC host controller
3802 *
3803 * @param dev mmc host controller device
3804 *
3805 * @return 0 for success, -1 on error
3806 */
octeontx_mmc_host_probe(struct udevice * dev)3807 static int octeontx_mmc_host_probe(struct udevice *dev)
3808 {
3809 struct octeontx_mmc_host *host = dev_get_priv(dev);
3810 union mio_emm_int emm_int;
3811 struct clk clk;
3812 int ret;
3813 u8 rev;
3814
3815 debug("%s(%s): Entry host: %p\n", __func__, dev->name, host);
3816
3817 if (!octeontx_mmc_get_valid(dev)) {
3818 debug("%s(%s): mmc host not valid\n", __func__, dev->name);
3819 return -ENODEV;
3820 }
3821 memset(host, 0, sizeof(*host));
3822
3823 /* Octeon TX & TX2 use PCI based probing */
3824 if (device_is_compatible(dev, "cavium,thunder-8890-mmc")) {
3825 host->base_addr = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0,
3826 PCI_REGION_MEM);
3827 if (!host->base_addr) {
3828 pr_err("%s: Error: MMC base address not found\n",
3829 __func__);
3830 return -1;
3831 }
3832 } else {
3833 host->base_addr = dev_remap_addr(dev);
3834 }
3835
3836 host->dev = dev;
3837 debug("%s(%s): Base address: %p\n", __func__, dev->name,
3838 host->base_addr);
3839 if (!dev_has_ofnode(dev)) {
3840 pr_err("%s: No device tree information found\n", __func__);
3841 return -1;
3842 }
3843 host->node = dev_ofnode(dev);
3844 host->last_slotid = -1;
3845 #if !defined(CONFIG_ARCH_OCTEON)
3846 if (otx_is_platform(PLATFORM_ASIM))
3847 host->is_asim = true;
3848 if (otx_is_platform(PLATFORM_EMULATOR))
3849 host->is_emul = true;
3850 #endif
3851 host->dma_wait_delay =
3852 ofnode_read_u32_default(dev_ofnode(dev),
3853 "marvell,dma-wait-delay", 1);
3854 /* Force reset of eMMC */
3855 writeq(0, host->base_addr + MIO_EMM_CFG());
3856 debug("%s: Clearing MIO_EMM_CFG\n", __func__);
3857 udelay(100);
3858 emm_int.u = readq(host->base_addr + MIO_EMM_INT());
3859 debug("%s: Writing 0x%llx to MIO_EMM_INT\n", __func__, emm_int.u);
3860 writeq(emm_int.u, host->base_addr + MIO_EMM_INT());
3861
3862 debug("%s(%s): Getting I/O clock\n", __func__, dev->name);
3863 ret = clk_get_by_index(dev, 0, &clk);
3864 if (ret < 0)
3865 return ret;
3866
3867 ret = clk_enable(&clk);
3868 if (ret)
3869 return ret;
3870
3871 host->sys_freq = clk_get_rate(&clk);
3872 debug("%s(%s): I/O clock %llu\n", __func__, dev->name, host->sys_freq);
3873
3874 if (IS_ENABLED(CONFIG_ARCH_OCTEONTX2)) {
3875 /* Flags for issues to work around */
3876 dm_pci_read_config8(dev, PCI_REVISION_ID, &rev);
3877 if (otx_is_soc(CN96XX)) {
3878 debug("%s: CN96XX revision %d\n", __func__, rev);
3879 switch (rev) {
3880 case 0:
3881 host->calibrate_glitch = true;
3882 host->cond_clock_glitch = true;
3883 break;
3884 case 1:
3885 break;
3886 case 2:
3887 break;
3888 case 0x10: /* C0 */
3889 host->hs400_skew_needed = true;
3890 debug("HS400 skew support enabled\n");
3891 fallthrough;
3892 default:
3893 debug("CN96XX rev C0+ detected\n");
3894 host->tap_requires_noclk = true;
3895 break;
3896 }
3897 } else if (otx_is_soc(CN95XX)) {
3898 if (!rev)
3899 host->cond_clock_glitch = true;
3900 }
3901 }
3902
3903 host_probed = true;
3904
3905 return 0;
3906 }
3907
3908 /**
3909 * This performs some initial setup before a probe occurs.
3910 *
3911 * @param dev: MMC slot device
3912 *
3913 * @return 0 for success, -1 on failure
3914 *
3915 * Do some pre-initialization before probing a slot.
3916 */
octeontx_mmc_host_child_pre_probe(struct udevice * dev)3917 static int octeontx_mmc_host_child_pre_probe(struct udevice *dev)
3918 {
3919 struct octeontx_mmc_host *host = dev_get_priv(dev_get_parent(dev));
3920 struct octeontx_mmc_slot *slot;
3921 struct mmc_uclass_priv *upriv;
3922 ofnode node = dev_ofnode(dev);
3923 u32 bus_id;
3924 char name[16];
3925 int err;
3926
3927 debug("%s(%s) Pre-Probe\n", __func__, dev->name);
3928 if (ofnode_read_u32(node, "reg", &bus_id)) {
3929 pr_err("%s(%s): Error: \"reg\" not found in device tree\n",
3930 __func__, dev->name);
3931 return -1;
3932 }
3933 if (bus_id > OCTEONTX_MAX_MMC_SLOT) {
3934 pr_err("%s(%s): Error: \"reg\" out of range of 0..%d\n",
3935 __func__, dev->name, OCTEONTX_MAX_MMC_SLOT);
3936 return -1;
3937 }
3938
3939 slot = &host->slots[bus_id];
3940 dev_set_priv(dev, slot);
3941 slot->host = host;
3942 slot->bus_id = bus_id;
3943 slot->dev = dev;
3944 slot->base_addr = host->base_addr;
3945 slot->is_asim = host->is_asim;
3946 slot->is_emul = host->is_emul;
3947
3948 snprintf(name, sizeof(name), "octeontx-mmc%d", bus_id);
3949 err = device_set_name(dev, name);
3950
3951 /* FIXME: This code should not be needed */
3952 if (!dev_get_uclass_priv(dev)) {
3953 debug("%s(%s): Allocating uclass priv\n", __func__,
3954 dev->name);
3955 upriv = calloc(1, sizeof(struct mmc_uclass_priv));
3956 if (!upriv)
3957 return -ENOMEM;
3958
3959 /*
3960 * FIXME: This is not allowed
3961 * dev_set_uclass_priv(dev, upriv);
3962 * uclass_set_priv(dev->uclass, upriv);
3963 */
3964 } else {
3965 upriv = dev_get_uclass_priv(dev);
3966 }
3967
3968 upriv->mmc = &slot->mmc;
3969 debug("%s: uclass priv: %p, mmc: %p\n", dev->name, upriv, upriv->mmc);
3970
3971 debug("%s: ret: %d\n", __func__, err);
3972 return err;
3973 }
3974
3975 static const struct udevice_id octeontx_hsmmc_host_ids[] = {
3976 { .compatible = "cavium,thunder-8890-mmc" },
3977 { .compatible = "cavium,octeon-7360-mmc" },
3978 { }
3979 };
3980
3981 U_BOOT_DRIVER(octeontx_hsmmc_host) = {
3982 .name = "octeontx_hsmmc_host",
3983 /* FIXME: Why is this not UCLASS_MMC? */
3984 .id = UCLASS_MISC,
3985 .of_match = of_match_ptr(octeontx_hsmmc_host_ids),
3986 .probe = octeontx_mmc_host_probe,
3987 .priv_auto = sizeof(struct octeontx_mmc_host),
3988 .child_pre_probe = octeontx_mmc_host_child_pre_probe,
3989 .flags = DM_FLAG_PRE_RELOC,
3990 };
3991
3992 static struct pci_device_id octeontx_mmc_supported[] = {
3993 { PCI_VDEVICE(CAVIUM, PCI_DEVICE_ID_CAVIUM_EMMC) },
3994 { },
3995 };
3996
3997 U_BOOT_PCI_DEVICE(octeontx_hsmmc_host, octeontx_mmc_supported);
3998