1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2015 Toradex, Inc.
4 *
5 * Based on vf610twr:
6 * Copyright 2013 Freescale Semiconductor, Inc.
7 */
8
9 #include <common.h>
10 #include <asm/io.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/iomux-vf610.h>
13 #include <asm/arch/ddrmc-vf610.h>
14 #include <linux/delay.h>
15 #include "ddrmc-vf610-calibration.h"
16
ddrmc_setup_iomux(const iomux_v3_cfg_t * pads,int pads_count)17 void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count)
18 {
19 static const iomux_v3_cfg_t default_pads[] = {
20 VF610_PAD_DDR_A15__DDR_A_15,
21 VF610_PAD_DDR_A14__DDR_A_14,
22 VF610_PAD_DDR_A13__DDR_A_13,
23 VF610_PAD_DDR_A12__DDR_A_12,
24 VF610_PAD_DDR_A11__DDR_A_11,
25 VF610_PAD_DDR_A10__DDR_A_10,
26 VF610_PAD_DDR_A9__DDR_A_9,
27 VF610_PAD_DDR_A8__DDR_A_8,
28 VF610_PAD_DDR_A7__DDR_A_7,
29 VF610_PAD_DDR_A6__DDR_A_6,
30 VF610_PAD_DDR_A5__DDR_A_5,
31 VF610_PAD_DDR_A4__DDR_A_4,
32 VF610_PAD_DDR_A3__DDR_A_3,
33 VF610_PAD_DDR_A2__DDR_A_2,
34 VF610_PAD_DDR_A1__DDR_A_1,
35 VF610_PAD_DDR_A0__DDR_A_0,
36 VF610_PAD_DDR_BA2__DDR_BA_2,
37 VF610_PAD_DDR_BA1__DDR_BA_1,
38 VF610_PAD_DDR_BA0__DDR_BA_0,
39 VF610_PAD_DDR_CAS__DDR_CAS_B,
40 VF610_PAD_DDR_CKE__DDR_CKE_0,
41 VF610_PAD_DDR_CLK__DDR_CLK_0,
42 VF610_PAD_DDR_CS__DDR_CS_B_0,
43 VF610_PAD_DDR_D15__DDR_D_15,
44 VF610_PAD_DDR_D14__DDR_D_14,
45 VF610_PAD_DDR_D13__DDR_D_13,
46 VF610_PAD_DDR_D12__DDR_D_12,
47 VF610_PAD_DDR_D11__DDR_D_11,
48 VF610_PAD_DDR_D10__DDR_D_10,
49 VF610_PAD_DDR_D9__DDR_D_9,
50 VF610_PAD_DDR_D8__DDR_D_8,
51 VF610_PAD_DDR_D7__DDR_D_7,
52 VF610_PAD_DDR_D6__DDR_D_6,
53 VF610_PAD_DDR_D5__DDR_D_5,
54 VF610_PAD_DDR_D4__DDR_D_4,
55 VF610_PAD_DDR_D3__DDR_D_3,
56 VF610_PAD_DDR_D2__DDR_D_2,
57 VF610_PAD_DDR_D1__DDR_D_1,
58 VF610_PAD_DDR_D0__DDR_D_0,
59 VF610_PAD_DDR_DQM1__DDR_DQM_1,
60 VF610_PAD_DDR_DQM0__DDR_DQM_0,
61 VF610_PAD_DDR_DQS1__DDR_DQS_1,
62 VF610_PAD_DDR_DQS0__DDR_DQS_0,
63 VF610_PAD_DDR_RAS__DDR_RAS_B,
64 VF610_PAD_DDR_WE__DDR_WE_B,
65 VF610_PAD_DDR_ODT1__DDR_ODT_0,
66 VF610_PAD_DDR_ODT0__DDR_ODT_1,
67 VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1,
68 VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2,
69 VF610_PAD_DDR_RESETB,
70 };
71
72 if ((pads == NULL) || (pads_count == 0)) {
73 pads = default_pads;
74 pads_count = ARRAY_SIZE(default_pads);
75 }
76
77 imx_iomux_v3_setup_multiple_pads(pads, pads_count);
78 }
79
80 static struct ddrmc_phy_setting default_phy_settings[] = {
81 { DDRMC_PHY_DQ_TIMING, 0 },
82 { DDRMC_PHY_DQ_TIMING, 16 },
83 { DDRMC_PHY_DQ_TIMING, 32 },
84
85 { DDRMC_PHY_DQS_TIMING, 1 },
86 { DDRMC_PHY_DQS_TIMING, 17 },
87
88 { DDRMC_PHY_CTRL, 2 },
89 { DDRMC_PHY_CTRL, 18 },
90 { DDRMC_PHY_CTRL, 34 },
91
92 { DDRMC_PHY_MASTER_CTRL, 3 },
93 { DDRMC_PHY_MASTER_CTRL, 19 },
94 { DDRMC_PHY_MASTER_CTRL, 35 },
95
96 { DDRMC_PHY_SLAVE_CTRL, 4 },
97 { DDRMC_PHY_SLAVE_CTRL, 20 },
98 { DDRMC_PHY_SLAVE_CTRL, 36 },
99
100 /* LPDDR2 only parameter */
101 { DDRMC_PHY_OFF, 49 },
102
103 { DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, 50 },
104
105 /* Processor Pad ODT settings */
106 { DDRMC_PHY_PROC_PAD_ODT, 52 },
107
108 /* end marker */
109 { 0, -1 }
110 };
111
ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const * timings,struct ddrmc_cr_setting * board_cr_settings,struct ddrmc_phy_setting * board_phy_settings,int col_diff,int row_diff)112 void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
113 struct ddrmc_cr_setting *board_cr_settings,
114 struct ddrmc_phy_setting *board_phy_settings,
115 int col_diff, int row_diff)
116 {
117 struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
118 struct ddrmc_cr_setting *cr_setting;
119 struct ddrmc_phy_setting *phy_setting;
120
121 writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]);
122 writel(DDRMC_CR02_DRAM_TINIT(timings->tinit), &ddrmr->cr[2]);
123 writel(DDRMC_CR10_TRST_PWRON(timings->trst_pwron), &ddrmr->cr[10]);
124
125 writel(DDRMC_CR11_CKE_INACTIVE(timings->cke_inactive), &ddrmr->cr[11]);
126 writel(DDRMC_CR12_WRLAT(timings->wrlat) |
127 DDRMC_CR12_CASLAT_LIN(timings->caslat_lin), &ddrmr->cr[12]);
128 writel(DDRMC_CR13_TRC(timings->trc) | DDRMC_CR13_TRRD(timings->trrd) |
129 DDRMC_CR13_TCCD(timings->tccd) |
130 DDRMC_CR13_TBST_INT_INTERVAL(timings->tbst_int_interval),
131 &ddrmr->cr[13]);
132 writel(DDRMC_CR14_TFAW(timings->tfaw) | DDRMC_CR14_TRP(timings->trp) |
133 DDRMC_CR14_TWTR(timings->twtr) |
134 DDRMC_CR14_TRAS_MIN(timings->tras_min), &ddrmr->cr[14]);
135 writel(DDRMC_CR16_TMRD(timings->tmrd) |
136 DDRMC_CR16_TRTP(timings->trtp), &ddrmr->cr[16]);
137 writel(DDRMC_CR17_TRAS_MAX(timings->tras_max) |
138 DDRMC_CR17_TMOD(timings->tmod), &ddrmr->cr[17]);
139 writel(DDRMC_CR18_TCKESR(timings->tckesr) |
140 DDRMC_CR18_TCKE(timings->tcke), &ddrmr->cr[18]);
141
142 writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]);
143 writel(DDRMC_CR21_TRCD_INT(timings->trcd_int) | DDRMC_CR21_CCMAP_EN |
144 DDRMC_CR21_TRAS_LOCKOUT(timings->tras_lockout),
145 &ddrmr->cr[21]);
146
147 writel(DDRMC_CR22_TDAL(timings->tdal), &ddrmr->cr[22]);
148 writel(DDRMC_CR23_BSTLEN(timings->bstlen) |
149 DDRMC_CR23_TDLL(timings->tdll), &ddrmr->cr[23]);
150 writel(DDRMC_CR24_TRP_AB(timings->trp_ab), &ddrmr->cr[24]);
151
152 writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]);
153 writel(DDRMC_CR26_TREF(timings->tref) |
154 DDRMC_CR26_TRFC(timings->trfc), &ddrmr->cr[26]);
155 writel(DDRMC_CR28_TREF_INT(timings->tref_int), &ddrmr->cr[28]);
156 writel(DDRMC_CR29_TPDEX(timings->tpdex), &ddrmr->cr[29]);
157
158 writel(DDRMC_CR30_TXPDLL(timings->txpdll), &ddrmr->cr[30]);
159 writel(DDRMC_CR31_TXSNR(timings->txsnr) |
160 DDRMC_CR31_TXSR(timings->txsr), &ddrmr->cr[31]);
161 writel(DDRMC_CR33_EN_QK_SREF, &ddrmr->cr[33]);
162 writel(DDRMC_CR34_CKSRX(timings->cksrx) |
163 DDRMC_CR34_CKSRE(timings->cksre), &ddrmr->cr[34]);
164
165 writel(DDRMC_CR38_FREQ_CHG_EN(timings->freq_chg_en), &ddrmr->cr[38]);
166 writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) |
167 DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]);
168
169 writel(DDRMC_CR41_PHY_INI_STRT_INI_DIS, &ddrmr->cr[41]);
170 writel(DDRMC_CR48_MR1_DA_0(70) |
171 DDRMC_CR48_MR0_DA_0(1056), &ddrmr->cr[48]);
172
173 writel(DDRMC_CR66_ZQCL(timings->zqcl) |
174 DDRMC_CR66_ZQINIT(timings->zqinit), &ddrmr->cr[66]);
175 writel(DDRMC_CR67_ZQCS(timings->zqcs), &ddrmr->cr[67]);
176 writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]);
177
178 writel(DDRMC_CR70_REF_PER_ZQ(timings->ref_per_zq), &ddrmr->cr[70]);
179 writel(DDRMC_CR72_ZQCS_ROTATE(timings->zqcs_rotate), &ddrmr->cr[72]);
180
181 writel(DDRMC_CR73_APREBIT(timings->aprebit) |
182 DDRMC_CR73_COL_DIFF(col_diff) |
183 DDRMC_CR73_ROW_DIFF(row_diff), &ddrmr->cr[73]);
184 writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN |
185 DDRMC_CR74_CMD_AGE_CNT(timings->cmd_age_cnt) |
186 DDRMC_CR74_AGE_CNT(timings->age_cnt),
187 &ddrmr->cr[74]);
188 writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN |
189 DDRMC_CR75_PLEN, &ddrmr->cr[75]);
190 writel(DDRMC_CR76_NQENT_ACTDIS(3) | DDRMC_CR76_D_RW_G_BKCN(3) |
191 DDRMC_CR76_W2R_SPLT_EN, &ddrmr->cr[76]);
192 writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE |
193 DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]);
194 writel(DDRMC_CR78_Q_FULLNESS(timings->q_fullness) |
195 DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]);
196
197 writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
198
199 writel(DDRMC_CR87_ODT_RD_MAPCS0(timings->odt_rd_mapcs0) |
200 DDRMC_CR87_ODT_WR_MAPCS0(timings->odt_wr_mapcs0),
201 &ddrmr->cr[87]);
202 writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]);
203 writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]);
204
205 writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr->cr[91]);
206 writel(DDRMC_CR96_WLMRD(timings->wlmrd) |
207 DDRMC_CR96_WLDQSEN(timings->wldqsen), &ddrmr->cr[96]);
208
209 /* execute custom CR setting sequence (may be NULL) */
210 cr_setting = board_cr_settings;
211 if (cr_setting != NULL)
212 while (cr_setting->cr_rnum >= 0) {
213 writel(cr_setting->setting,
214 &ddrmr->cr[cr_setting->cr_rnum]);
215 cr_setting++;
216 }
217
218 /* perform default PHY settings (may be overridden by custom settings */
219 phy_setting = default_phy_settings;
220 while (phy_setting->phy_rnum >= 0) {
221 writel(phy_setting->setting,
222 &ddrmr->phy[phy_setting->phy_rnum]);
223 phy_setting++;
224 }
225
226 /* execute custom PHY setting sequence (may be NULL) */
227 phy_setting = board_phy_settings;
228 if (phy_setting != NULL)
229 while (phy_setting->phy_rnum >= 0) {
230 writel(phy_setting->setting,
231 &ddrmr->phy[phy_setting->phy_rnum]);
232 phy_setting++;
233 }
234
235 /* all inits done, start the DDR controller */
236 writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]);
237
238 while (!(readl(&ddrmr->cr[80]) & DDRMC_CR80_MC_INIT_COMPLETE))
239 udelay(10);
240 writel(DDRMC_CR80_MC_INIT_COMPLETE, &ddrmr->cr[81]);
241
242 #ifdef CONFIG_DDRMC_VF610_CALIBRATION
243 ddrmc_calibration(ddrmr);
244 #endif
245 }
246