1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2013-2017 Altera Corporation <www.altera.com> 4 */ 5 6 #ifndef _CLOCK_MANAGER_GEN5_H_ 7 #define _CLOCK_MANAGER_GEN5_H_ 8 9 #ifndef __ASSEMBLY__ 10 11 #include <linux/bitops.h> 12 13 struct cm_config { 14 /* main group */ 15 u32 main_vco_base; 16 u32 mpuclk; 17 u32 mainclk; 18 u32 dbgatclk; 19 u32 mainqspiclk; 20 u32 mainnandsdmmcclk; 21 u32 cfg2fuser0clk; 22 u32 maindiv; 23 u32 dbgdiv; 24 u32 tracediv; 25 u32 l4src; 26 27 /* peripheral group */ 28 u32 peri_vco_base; 29 u32 emac0clk; 30 u32 emac1clk; 31 u32 perqspiclk; 32 u32 pernandsdmmcclk; 33 u32 perbaseclk; 34 u32 s2fuser1clk; 35 u32 perdiv; 36 u32 gpiodiv; 37 u32 persrc; 38 39 /* sdram pll group */ 40 u32 sdram_vco_base; 41 u32 ddrdqsclk; 42 u32 ddr2xdqsclk; 43 u32 ddrdqclk; 44 u32 s2fuser2clk; 45 46 /* altera group */ 47 u32 altera_grp_mpuclk; 48 }; 49 50 /* Clock manager group */ 51 #define CLKMGR_GEN5_CTRL 0x00 52 #define CLKMGR_GEN5_BYPASS 0x04 53 #define CLKMGR_GEN5_INTER 0x08 54 #define CLKMGR_GEN5_STAT 0x14 55 /* MainPLL group */ 56 #define CLKMGR_GEN5_MAINPLL_VCO 0x40 57 #define CLKMGR_GEN5_MAINPLL_MISC 0x44 58 #define CLKMGR_GEN5_MAINPLL_MPUCLK 0x48 59 #define CLKMGR_GEN5_MAINPLL_MAINCLK 0x4c 60 #define CLKMGR_GEN5_MAINPLL_DBGATCLK 0x50 61 #define CLKMGR_GEN5_MAINPLL_MAINQSPICLK 0x54 62 #define CLKMGR_GEN5_MAINPLL_MAINNANDSDMMCCLK 0x58 63 #define CLKMGR_GEN5_MAINPLL_CFGS2FUSER0CLK 0x5c 64 #define CLKMGR_GEN5_MAINPLL_EN 0x60 65 #define CLKMGR_GEN5_MAINPLL_MAINDIV 0x64 66 #define CLKMGR_GEN5_MAINPLL_DBGDIV 0x68 67 #define CLKMGR_GEN5_MAINPLL_TRACEDIV 0x6c 68 #define CLKMGR_GEN5_MAINPLL_L4SRC 0x70 69 /* Peripheral PLL group */ 70 #define CLKMGR_GEN5_PERPLL_VCO 0x80 71 #define CLKMGR_GEN5_PERPLL_MISC 0x84 72 #define CLKMGR_GEN5_PERPLL_EMAC0CLK 0x88 73 #define CLKMGR_GEN5_PERPLL_EMAC1CLK 0x8c 74 #define CLKMGR_GEN5_PERPLL_PERQSPICLK 0x90 75 #define CLKMGR_GEN5_PERPLL_PERNANDSDMMCCLK 0x94 76 #define CLKMGR_GEN5_PERPLL_PERBASECLK 0x98 77 #define CLKMGR_GEN5_PERPLL_S2FUSER1CLK 0x9c 78 #define CLKMGR_GEN5_PERPLL_EN 0xa0 79 #define CLKMGR_GEN5_PERPLL_DIV 0xa4 80 #define CLKMGR_GEN5_PERPLL_GPIODIV 0xa8 81 #define CLKMGR_GEN5_PERPLL_SRC 0xac 82 /* SDRAM PLL group */ 83 #define CLKMGR_GEN5_SDRPLL_VCO 0xc0 84 #define CLKMGR_GEN5_SDRPLL_CTRL 0xc4 85 #define CLKMGR_GEN5_SDRPLL_DDRDQSCLK 0xc8 86 #define CLKMGR_GEN5_SDRPLL_DDR2XDQSCLK 0xcc 87 #define CLKMGR_GEN5_SDRPLL_DDRDQCLK 0xd0 88 #define CLKMGR_GEN5_SDRPLL_S2FUSER2CLK 0xd4 89 #define CLKMGR_GEN5_SDRPLL_EN 0xd8 90 /* Altera group */ 91 #define CLKMGR_GEN5_ALTR_MPUCLK 0xe0 92 #define CLKMGR_GEN5_ALTR_MAINCLK 0xe4 93 94 #define CLKMGR_STAT CLKMGR_GEN5_STAT 95 #define CLKMGR_INTER CLKMGR_GEN5_INTER 96 #define CLKMGR_PERPLL_EN CLKMGR_GEN5_PERPLL_EN 97 98 /* Clock speed accessors */ 99 unsigned long cm_get_mpu_clk_hz(void); 100 unsigned long cm_get_sdram_clk_hz(void); 101 unsigned int cm_get_l4_sp_clk_hz(void); 102 unsigned int cm_get_mmc_controller_clk_hz(void); 103 unsigned int cm_get_spi_controller_clk_hz(void); 104 const unsigned int cm_get_osc_clk_hz(const int osc); 105 const unsigned int cm_get_f2s_per_ref_clk_hz(void); 106 const unsigned int cm_get_f2s_sdr_ref_clk_hz(void); 107 108 /* Clock configuration accessors */ 109 int cm_basic_init(const struct cm_config * const cfg); 110 const struct cm_config * const cm_get_default_config(void); 111 #endif /* __ASSEMBLY__ */ 112 113 #include <linux/bitops.h> 114 #define LOCKED_MASK \ 115 (CLKMGR_INTER_SDRPLLLOCKED_MASK | \ 116 CLKMGR_INTER_PERPLLLOCKED_MASK | \ 117 CLKMGR_INTER_MAINPLLLOCKED_MASK) 118 119 #define CLKMGR_CTRL_SAFEMODE BIT(0) 120 #define CLKMGR_CTRL_SAFEMODE_OFFSET 0 121 122 #define CLKMGR_BYPASS_PERPLLSRC BIT(4) 123 #define CLKMGR_BYPASS_PERPLLSRC_OFFSET 4 124 #define CLKMGR_BYPASS_PERPLL BIT(3) 125 #define CLKMGR_BYPASS_PERPLL_OFFSET 3 126 #define CLKMGR_BYPASS_SDRPLLSRC BIT(2) 127 #define CLKMGR_BYPASS_SDRPLLSRC_OFFSET 2 128 #define CLKMGR_BYPASS_SDRPLL BIT(1) 129 #define CLKMGR_BYPASS_SDRPLL_OFFSET 1 130 #define CLKMGR_BYPASS_MAINPLL BIT(0) 131 #define CLKMGR_BYPASS_MAINPLL_OFFSET 0 132 133 #define CLKMGR_INTER_MAINPLLLOST_MASK BIT(3) 134 #define CLKMGR_INTER_PERPLLLOST_MASK BIT(4) 135 #define CLKMGR_INTER_SDRPLLLOST_MASK BIT(5) 136 #define CLKMGR_INTER_MAINPLLLOCKED_MASK BIT(6) 137 #define CLKMGR_INTER_PERPLLLOCKED_MASK BIT(7) 138 #define CLKMGR_INTER_SDRPLLLOCKED_MASK BIT(8) 139 140 #define CLKMGR_STAT_BUSY BIT(0) 141 142 /* Main PLL */ 143 #define CLKMGR_MAINPLLGRP_VCO_BGPWRDN BIT(0) 144 #define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_OFFSET 0 145 #define CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET 16 146 #define CLKMGR_MAINPLLGRP_VCO_DENOM_MASK 0x003f0000 147 #define CLKMGR_MAINPLLGRP_VCO_EN BIT(1) 148 #define CLKMGR_MAINPLLGRP_VCO_EN_OFFSET 1 149 #define CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET 3 150 #define CLKMGR_MAINPLLGRP_VCO_NUMER_MASK 0x0000fff8 151 #define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 152 #define CLKMGR_MAINPLLGRP_VCO_PWRDN BIT(2) 153 #define CLKMGR_MAINPLLGRP_VCO_PWRDN_OFFSET 2 154 #define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 155 #define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d 156 157 #define CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET 0 158 #define CLKMGR_MAINPLLGRP_MPUCLK_CNT_MASK 0x000001ff 159 160 #define CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET 0 161 #define CLKMGR_MAINPLLGRP_MAINCLK_CNT_MASK 0x000001ff 162 163 #define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET 0 164 #define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_MASK 0x000001ff 165 166 #define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET 0 167 #define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_MASK 0x000001ff 168 169 #define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_OFFSET 0 170 #define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_MASK 0x000001ff 171 172 #define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET 0 173 #define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_MASK 0x000001ff 174 175 #define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK BIT(2) 176 #define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK BIT(4) 177 #define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK BIT(5) 178 #define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK BIT(6) 179 #define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK BIT(7) 180 #define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK BIT(9) 181 182 #define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET 0 183 #define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_MASK 0x00000003 184 #define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET 2 185 #define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_MASK 0x0000000c 186 #define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET 4 187 #define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_MASK 0x00000070 188 #define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET 7 189 #define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK 0x00000380 190 191 #define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET 0 192 #define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_MASK 0x00000003 193 #define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET 2 194 #define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_MASK 0x0000000c 195 196 #define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET 0 197 #define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_MASK 0x00000007 198 199 #define CLKMGR_MAINPLLGRP_L4SRC_L4MP BIT(0) 200 #define CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET 0 201 #define CLKMGR_MAINPLLGRP_L4SRC_L4SP BIT(1) 202 #define CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET 1 203 #define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000 204 #define CLKMGR_L4_SP_CLK_SRC_MAINPLL 0x0 205 #define CLKMGR_L4_SP_CLK_SRC_PERPLL 0x1 206 207 /* Per PLL */ 208 #define CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET 16 209 #define CLKMGR_PERPLLGRP_VCO_DENOM_MASK 0x003f0000 210 #define CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET 3 211 #define CLKMGR_PERPLLGRP_VCO_NUMER_MASK 0x0000fff8 212 #define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 213 #define CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET 22 214 #define CLKMGR_PERPLLGRP_VCO_PSRC_MASK 0x00c00000 215 #define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 216 #define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d 217 #define CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET 22 218 #define CLKMGR_PERPLLGRP_VCO_SSRC_MASK 0x00c00000 219 220 #define CLKMGR_VCO_SSRC_EOSC1 0x0 221 #define CLKMGR_VCO_SSRC_EOSC2 0x1 222 #define CLKMGR_VCO_SSRC_F2S 0x2 223 224 #define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET 0 225 #define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_MASK 0x000001ff 226 227 #define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET 0 228 #define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_MASK 0x000001ff 229 230 #define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET 0 231 #define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_MASK 0x000001ff 232 233 #define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET 0 234 #define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_MASK 0x000001ff 235 236 #define CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET 0 237 #define CLKMGR_PERPLLGRP_PERBASECLK_CNT_MASK 0x000001ff 238 239 #define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET 0 240 #define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_MASK 0x000001ff 241 242 #define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400 243 #define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000100 244 245 #define CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET 6 246 #define CLKMGR_PERPLLGRP_DIV_CAN0CLK_MASK 0x000001c0 247 #define CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET 9 248 #define CLKMGR_PERPLLGRP_DIV_CAN1CLK_MASK 0x00000e00 249 #define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3 250 #define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3 251 #define CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET 0 252 #define CLKMGR_PERPLLGRP_DIV_USBCLK_MASK 0x00000007 253 254 #define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET 0 255 #define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_MASK 0x00ffffff 256 257 #define CLKMGR_PERPLLGRP_SRC_NAND_OFFSET 2 258 #define CLKMGR_PERPLLGRP_SRC_NAND_MASK 0x0000000c 259 #define CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET 4 260 #define CLKMGR_PERPLLGRP_SRC_QSPI_MASK 0x00000030 261 #define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015 262 #define CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET 0 263 #define CLKMGR_PERPLLGRP_SRC_SDMMC_MASK 0x00000003 264 #define CLKMGR_SDMMC_CLK_SRC_F2S 0x0 265 #define CLKMGR_SDMMC_CLK_SRC_MAIN 0x1 266 #define CLKMGR_SDMMC_CLK_SRC_PER 0x2 267 #define CLKMGR_QSPI_CLK_SRC_F2S 0x0 268 #define CLKMGR_QSPI_CLK_SRC_MAIN 0x1 269 #define CLKMGR_QSPI_CLK_SRC_PER 0x2 270 271 /* SDR PLL */ 272 #define CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET 16 273 #define CLKMGR_SDRPLLGRP_VCO_DENOM_MASK 0x003f0000 274 #define CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET 3 275 #define CLKMGR_SDRPLLGRP_VCO_NUMER_MASK 0x0000fff8 276 #define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL BIT(24) 277 #define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_OFFSET 24 278 #define CLKMGR_SDRPLLGRP_VCO_OUTRESET_OFFSET 25 279 #define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000 280 #define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK BIT(31) 281 #define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d 282 #define CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET 22 283 #define CLKMGR_SDRPLLGRP_VCO_SSRC_MASK 0x00c00000 284 285 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET 0 286 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff 287 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET 9 288 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x00000e00 289 290 #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET 0 291 #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff 292 #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET 9 293 #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x00000e00 294 295 #define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET 0 296 #define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff 297 #define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET 9 298 #define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x00000e00 299 300 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET 0 301 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff 302 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET 9 303 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x00000e00 304 305 #endif /* _CLOCK_MANAGER_GEN5_H_ */ 306