1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /*
3 * Cadence DDR Driver
4 *
5 * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
6 * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
7 */
8
9 #ifndef LPDDR4_32BIT_SANITY_H
10 #define LPDDR4_32BIT_SANITY_H
11
12 #include <errno.h>
13 #include <linux/types.h>
14 #include <lpddr4_if.h>
15 #ifdef __cplusplus
16 extern "C" {
17 #endif
18
19 static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus);
20 static inline u32 lpddr4_intr_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr);
21 static inline u32 lpddr4_intr_sanityfunction3(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr, const bool *irqstatus);
22 static inline u32 lpddr4_intr_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr);
23
24 #define LPDDR4_INTR_CheckCtlIntSF lpddr4_intr_sanityfunction1
25 #define LPDDR4_INTR_AckCtlIntSF lpddr4_intr_sanityfunction2
26 #define LPDDR4_INTR_CheckPhyIndepIntSF lpddr4_intr_sanityfunction3
27 #define LPDDR4_INTR_AckPhyIndepIntSF lpddr4_intr_sanityfunction4
28
lpddr4_intr_sanityfunction1(const lpddr4_privatedata * pd,const lpddr4_intr_ctlinterrupt intr,const bool * irqstatus)29 static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus)
30 {
31 u32 ret = 0;
32
33 if (pd == NULL) {
34 ret = EINVAL;
35 } else if (irqstatus == NULL) {
36 ret = EINVAL;
37 } else if (
38 (intr != LPDDR4_INTR_RESET_DONE) &&
39 (intr != LPDDR4_INTR_BUS_ACCESS_ERROR) &&
40 (intr != LPDDR4_INTR_MULTIPLE_BUS_ACCESS_ERROR) &&
41 (intr != LPDDR4_INTR_ECC_MULTIPLE_CORR_ERROR) &&
42 (intr != LPDDR4_INTR_ECC_MULTIPLE_UNCORR_ERROR) &&
43 (intr != LPDDR4_INTR_ECC_WRITEBACK_EXEC_ERROR) &&
44 (intr != LPDDR4_INTR_ECC_SCRUB_DONE) &&
45 (intr != LPDDR4_INTR_ECC_SCRUB_ERROR) &&
46 (intr != LPDDR4_INTR_PORT_COMMAND_ERROR) &&
47 (intr != LPDDR4_INTR_MC_INIT_DONE) &&
48 (intr != LPDDR4_INTR_LP_DONE) &&
49 (intr != LPDDR4_INTR_BIST_DONE) &&
50 (intr != LPDDR4_INTR_WRAP_ERROR) &&
51 (intr != LPDDR4_INTR_INVALID_BURST_ERROR) &&
52 (intr != LPDDR4_INTR_RDLVL_ERROR) &&
53 (intr != LPDDR4_INTR_RDLVL_GATE_ERROR) &&
54 (intr != LPDDR4_INTR_WRLVL_ERROR) &&
55 (intr != LPDDR4_INTR_CA_TRAINING_ERROR) &&
56 (intr != LPDDR4_INTR_DFI_UPDATE_ERROR) &&
57 (intr != LPDDR4_INTR_MRR_ERROR) &&
58 (intr != LPDDR4_INTR_PHY_MASTER_ERROR) &&
59 (intr != LPDDR4_INTR_WRLVL_REQ) &&
60 (intr != LPDDR4_INTR_RDLVL_REQ) &&
61 (intr != LPDDR4_INTR_RDLVL_GATE_REQ) &&
62 (intr != LPDDR4_INTR_CA_TRAINING_REQ) &&
63 (intr != LPDDR4_INTR_LEVELING_DONE) &&
64 (intr != LPDDR4_INTR_PHY_ERROR) &&
65 (intr != LPDDR4_INTR_MR_READ_DONE) &&
66 (intr != LPDDR4_INTR_TEMP_CHANGE) &&
67 (intr != LPDDR4_INTR_TEMP_ALERT) &&
68 (intr != LPDDR4_INTR_SW_DQS_COMPLETE) &&
69 (intr != LPDDR4_INTR_DQS_OSC_BV_UPDATED) &&
70 (intr != LPDDR4_INTR_DQS_OSC_OVERFLOW) &&
71 (intr != LPDDR4_INTR_DQS_OSC_VAR_OUT) &&
72 (intr != LPDDR4_INTR_MR_WRITE_DONE) &&
73 (intr != LPDDR4_INTR_INHIBIT_DRAM_DONE) &&
74 (intr != LPDDR4_INTR_DFI_INIT_STATE) &&
75 (intr != LPDDR4_INTR_DLL_RESYNC_DONE) &&
76 (intr != LPDDR4_INTR_TDFI_TO) &&
77 (intr != LPDDR4_INTR_DFS_DONE) &&
78 (intr != LPDDR4_INTR_DFS_STATUS) &&
79 (intr != LPDDR4_INTR_REFRESH_STATUS) &&
80 (intr != LPDDR4_INTR_ZQ_STATUS) &&
81 (intr != LPDDR4_INTR_SW_REQ_MODE) &&
82 (intr != LPDDR4_INTR_LOR_BITS)
83 ) {
84 ret = EINVAL;
85 } else {
86 }
87
88 return ret;
89 }
90
lpddr4_intr_sanityfunction2(const lpddr4_privatedata * pd,const lpddr4_intr_ctlinterrupt intr)91 static inline u32 lpddr4_intr_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr)
92 {
93 u32 ret = 0;
94
95 if (pd == NULL) {
96 ret = EINVAL;
97 } else if (
98 (intr != LPDDR4_INTR_RESET_DONE) &&
99 (intr != LPDDR4_INTR_BUS_ACCESS_ERROR) &&
100 (intr != LPDDR4_INTR_MULTIPLE_BUS_ACCESS_ERROR) &&
101 (intr != LPDDR4_INTR_ECC_MULTIPLE_CORR_ERROR) &&
102 (intr != LPDDR4_INTR_ECC_MULTIPLE_UNCORR_ERROR) &&
103 (intr != LPDDR4_INTR_ECC_WRITEBACK_EXEC_ERROR) &&
104 (intr != LPDDR4_INTR_ECC_SCRUB_DONE) &&
105 (intr != LPDDR4_INTR_ECC_SCRUB_ERROR) &&
106 (intr != LPDDR4_INTR_PORT_COMMAND_ERROR) &&
107 (intr != LPDDR4_INTR_MC_INIT_DONE) &&
108 (intr != LPDDR4_INTR_LP_DONE) &&
109 (intr != LPDDR4_INTR_BIST_DONE) &&
110 (intr != LPDDR4_INTR_WRAP_ERROR) &&
111 (intr != LPDDR4_INTR_INVALID_BURST_ERROR) &&
112 (intr != LPDDR4_INTR_RDLVL_ERROR) &&
113 (intr != LPDDR4_INTR_RDLVL_GATE_ERROR) &&
114 (intr != LPDDR4_INTR_WRLVL_ERROR) &&
115 (intr != LPDDR4_INTR_CA_TRAINING_ERROR) &&
116 (intr != LPDDR4_INTR_DFI_UPDATE_ERROR) &&
117 (intr != LPDDR4_INTR_MRR_ERROR) &&
118 (intr != LPDDR4_INTR_PHY_MASTER_ERROR) &&
119 (intr != LPDDR4_INTR_WRLVL_REQ) &&
120 (intr != LPDDR4_INTR_RDLVL_REQ) &&
121 (intr != LPDDR4_INTR_RDLVL_GATE_REQ) &&
122 (intr != LPDDR4_INTR_CA_TRAINING_REQ) &&
123 (intr != LPDDR4_INTR_LEVELING_DONE) &&
124 (intr != LPDDR4_INTR_PHY_ERROR) &&
125 (intr != LPDDR4_INTR_MR_READ_DONE) &&
126 (intr != LPDDR4_INTR_TEMP_CHANGE) &&
127 (intr != LPDDR4_INTR_TEMP_ALERT) &&
128 (intr != LPDDR4_INTR_SW_DQS_COMPLETE) &&
129 (intr != LPDDR4_INTR_DQS_OSC_BV_UPDATED) &&
130 (intr != LPDDR4_INTR_DQS_OSC_OVERFLOW) &&
131 (intr != LPDDR4_INTR_DQS_OSC_VAR_OUT) &&
132 (intr != LPDDR4_INTR_MR_WRITE_DONE) &&
133 (intr != LPDDR4_INTR_INHIBIT_DRAM_DONE) &&
134 (intr != LPDDR4_INTR_DFI_INIT_STATE) &&
135 (intr != LPDDR4_INTR_DLL_RESYNC_DONE) &&
136 (intr != LPDDR4_INTR_TDFI_TO) &&
137 (intr != LPDDR4_INTR_DFS_DONE) &&
138 (intr != LPDDR4_INTR_DFS_STATUS) &&
139 (intr != LPDDR4_INTR_REFRESH_STATUS) &&
140 (intr != LPDDR4_INTR_ZQ_STATUS) &&
141 (intr != LPDDR4_INTR_SW_REQ_MODE) &&
142 (intr != LPDDR4_INTR_LOR_BITS)
143 ) {
144 ret = EINVAL;
145 } else {
146 }
147
148 return ret;
149 }
150
lpddr4_intr_sanityfunction3(const lpddr4_privatedata * pd,const lpddr4_intr_phyindepinterrupt intr,const bool * irqstatus)151 static inline u32 lpddr4_intr_sanityfunction3(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr, const bool *irqstatus)
152 {
153 u32 ret = 0;
154
155 if (pd == NULL) {
156 ret = EINVAL;
157 } else if (irqstatus == NULL) {
158 ret = EINVAL;
159 } else if (
160 (intr != LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT) &&
161 (intr != LPDDR4_INTR_PHY_INDEP_CONTROL_ERROR_BIT) &&
162 (intr != LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT) &&
163 (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT) &&
164 (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT) &&
165 (intr != LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT) &&
166 (intr != LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT) &&
167 (intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT) &&
168 (intr != LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT) &&
169 (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT) &&
170 (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT) &&
171 (intr != LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT) &&
172 (intr != LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT) &&
173 (intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT) &&
174 (intr != LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT) &&
175 (intr != LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT) &&
176 (intr != LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT) &&
177 (intr != LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT)
178 ) {
179 ret = EINVAL;
180 } else {
181 }
182
183 return ret;
184 }
185
lpddr4_intr_sanityfunction4(const lpddr4_privatedata * pd,const lpddr4_intr_phyindepinterrupt intr)186 static inline u32 lpddr4_intr_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr)
187 {
188 u32 ret = 0;
189
190 if (pd == NULL) {
191 ret = EINVAL;
192 } else if (
193 (intr != LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT) &&
194 (intr != LPDDR4_INTR_PHY_INDEP_CONTROL_ERROR_BIT) &&
195 (intr != LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT) &&
196 (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT) &&
197 (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT) &&
198 (intr != LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT) &&
199 (intr != LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT) &&
200 (intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT) &&
201 (intr != LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT) &&
202 (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT) &&
203 (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT) &&
204 (intr != LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT) &&
205 (intr != LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT) &&
206 (intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT) &&
207 (intr != LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT) &&
208 (intr != LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT) &&
209 (intr != LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT) &&
210 (intr != LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT)
211 ) {
212 ret = EINVAL;
213 } else {
214 }
215
216 return ret;
217 }
218
219 #ifdef __cplusplus
220 }
221 #endif
222
223 #endif /* LPDDR4_32BIT_SANITY_H */
224